Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Stefano Babic
102
include/asm-generic/global_data.h
Normal file
102
include/asm-generic/global_data.h
Normal file
@@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Copyright (c) 2012 The Chromium OS Authors.
|
||||
* (C) Copyright 2002-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_GENERIC_GBL_DATA_H
|
||||
#define __ASM_GENERIC_GBL_DATA_H
|
||||
/*
|
||||
* The following data structure is placed in some memory which is
|
||||
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
|
||||
* some locked parts of the data cache) to allow for a minimum set of
|
||||
* global variables during system initialization (until we have set
|
||||
* up the memory controller so that we can use RAM).
|
||||
*
|
||||
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
|
||||
*
|
||||
* Each architecture has its own private fields. For now all are private
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct global_data {
|
||||
bd_t *bd;
|
||||
unsigned long flags;
|
||||
unsigned long baudrate;
|
||||
unsigned long cpu_clk; /* CPU clock in Hz! */
|
||||
unsigned long bus_clk;
|
||||
/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
|
||||
unsigned long pci_clk;
|
||||
unsigned long mem_clk;
|
||||
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
|
||||
unsigned long fb_base; /* Base address of framebuffer mem */
|
||||
#endif
|
||||
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
|
||||
unsigned long post_log_word; /* Record POST activities */
|
||||
unsigned long post_log_res; /* success of POST test */
|
||||
unsigned long post_init_f_time; /* When post_init_f started */
|
||||
#endif
|
||||
#ifdef CONFIG_BOARD_TYPES
|
||||
unsigned long board_type;
|
||||
#endif
|
||||
unsigned long have_console; /* serial_init() was called */
|
||||
#ifdef CONFIG_PRE_CONSOLE_BUFFER
|
||||
unsigned long precon_buf_idx; /* Pre-Console buffer index */
|
||||
#endif
|
||||
#ifdef CONFIG_MODEM_SUPPORT
|
||||
unsigned long do_mdm_init;
|
||||
unsigned long be_quiet;
|
||||
#endif
|
||||
unsigned long env_addr; /* Address of Environment struct */
|
||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||
|
||||
/* TODO: is this the same as relocaddr, or something else? */
|
||||
unsigned long dest_addr; /* Post-relocation address of U-Boot */
|
||||
unsigned long dest_addr_sp;
|
||||
unsigned long ram_top; /* Top address of RAM used by U-Boot */
|
||||
|
||||
unsigned long relocaddr; /* Start address of U-Boot in RAM */
|
||||
phys_size_t ram_size; /* RAM size */
|
||||
unsigned long mon_len; /* monitor len */
|
||||
unsigned long irq_sp; /* irq stack pointer */
|
||||
unsigned long start_addr_sp; /* start_addr_stackpointer */
|
||||
unsigned long reloc_off;
|
||||
struct global_data *new_gd; /* relocated global data */
|
||||
const void *fdt_blob; /* Our device tree, NULL if none */
|
||||
void **jt; /* jump table */
|
||||
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||
struct arch_global_data arch; /* architecture-specific data */
|
||||
} gd_t;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Global Data Flags
|
||||
*/
|
||||
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
|
||||
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
|
||||
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
||||
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
|
||||
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
|
||||
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
|
||||
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
|
||||
#define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
|
||||
|
||||
#endif /* __ASM_GENERIC_GBL_DATA_H */
|
||||
@@ -139,10 +139,12 @@ enum command_ret_t {
|
||||
* @param repeatable This function sets this to 0 if the command is not
|
||||
* repeatable. If the command is repeatable, the value
|
||||
* is left unchanged.
|
||||
* @param ticks If ticks is not null, this function set it to the
|
||||
* number of ticks the command took to complete.
|
||||
* @return 0 if the command succeeded, 1 if it failed
|
||||
*/
|
||||
int cmd_process(int flag, int argc, char * const argv[],
|
||||
int *repeatable);
|
||||
int *repeatable, unsigned long *ticks);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
820
include/configs/B4860QDS.h
Normal file
820
include/configs/B4860QDS.h
Normal file
@@ -0,0 +1,820 @@
|
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* B4860 QDS board configuration file
|
||||
*/
|
||||
#define CONFIG_B4860QDS
|
||||
#define CONFIG_PHYS_64BIT
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE
|
||||
#define CONFIG_E6500
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_E500MC /* BOOKE e500mc family */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#ifndef CONFIG_PPC_B4420
|
||||
#define CONFIG_SYS_SRIO
|
||||
#define CONFIG_SRIO1 /* SRIO port 1 */
|
||||
#define CONFIG_SRIO2 /* SRIO port 2 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR 0x77
|
||||
|
||||
/* VSC Crossbar switches */
|
||||
#define CONFIG_VSC_CROSSBAR
|
||||
#define I2C_CH_DEFAULT 0x8
|
||||
#define I2C_CH_VSC3316 0xc
|
||||
#define I2C_CH_VSC3308 0xd
|
||||
|
||||
#define VSC3316_TX_ADDRESS 0x70
|
||||
#define VSC3316_RX_ADDRESS 0x71
|
||||
#define VSC3308_TX_ADDRESS 0x02
|
||||
#define VSC3308_RX_ADDRESS 0x03
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#else
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_OFFSET (512 * 1097)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
#else /* CONFIG_SYS_NO_FLASH */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned long get_board_sys_clk(void);
|
||||
unsigned long get_board_ddr_clk(void);
|
||||
#endif
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_DDR_ECC
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
|
||||
#endif
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_DDR_RAW_TIMING
|
||||
#define CONFIG_FSL_DDR3
|
||||
#define CONFIG_FSL_DDR_INTERACTIVE
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS1 0x51
|
||||
#define SPD_EEPROM_ADDRESS2 0x53
|
||||
|
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
|
||||
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
|
||||
+ 0x8000000) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
|
||||
FTIM0_NOR_TEADC(0x01) | \
|
||||
FTIM0_NOR_TEAHC(0x20))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
|
||||
FTIM2_NOR_TCH(0x0E) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
|
||||
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
|
||||
#define CONFIG_FSL_QIXIS_V2
|
||||
#define QIXIS_BASE 0xffdf0000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
|
||||
#else
|
||||
#define QIXIS_BASE_PHYS QIXIS_BASE
|
||||
#endif
|
||||
#define QIXIS_LBMAP_SWITCH 0x01
|
||||
#define QIXIS_LBMAP_MASK 0x0f
|
||||
#define QIXIS_LBMAP_SHIFT 0
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x02
|
||||
#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
|
||||
#define CONFIG_SYS_CSPR3_EXT (0xf)
|
||||
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
|
||||
#define CONFIG_SYS_CSOR3 0x0
|
||||
/* QIXIS Timing parameters for IFC CS3 */
|
||||
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x0) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS3_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
#if defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
|
||||
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x119000
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define RTC
|
||||
#define CONFIG_RTC_DS3231 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
*/
|
||||
#ifdef CONFIG_SYS_SRIO
|
||||
#ifdef CONFIG_SRIO1
|
||||
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SRIO2
|
||||
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* for slave u-boot IMAGE instored in master memory space,
|
||||
* PHYS must be aligned based on the SIZE
|
||||
*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
|
||||
/*
|
||||
* for slave UCODE and ENV instored in master memory space,
|
||||
* PHYS must be aligned based on the SIZE
|
||||
*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
|
||||
|
||||
/* slave core release by master*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
|
||||
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
|
||||
|
||||
/*
|
||||
* SRIO_PCIE_BOOT - SLAVE
|
||||
*/
|
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
|
||||
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SST
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE 0
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
||||
* env, so we got 0x110000.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
|
||||
#endif
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
#endif /* CONFIG_NOBQFMAN */
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
#define CONFIG_PHYLIB_10G
|
||||
#define CONFIG_PHY_VITESSE
|
||||
#define CONFIG_PHY_TERANETICS
|
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x10
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x11
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_E1000
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
|
||||
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
|
||||
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
|
||||
|
||||
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
|
||||
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
|
||||
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
|
||||
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define __USB_PHY_TYPE ulpi
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=null," \
|
||||
"bank_intlv=cs0_cs1;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=b4860qds/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=b4860qds/b4860qds.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"c=ffe\0"
|
||||
|
||||
/* For emulation this causes u-boot to jump to the start of the proof point
|
||||
app code automatically */
|
||||
#define CONFIG_PROOF_POINTS \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"cpu 1 release 0x29000000 - - -;" \
|
||||
"cpu 2 release 0x29000000 - - -;" \
|
||||
"cpu 3 release 0x29000000 - - -;" \
|
||||
"cpu 4 release 0x29000000 - - -;" \
|
||||
"cpu 5 release 0x29000000 - - -;" \
|
||||
"cpu 6 release 0x29000000 - - -;" \
|
||||
"cpu 7 release 0x29000000 - - -;" \
|
||||
"go 0x29000000"
|
||||
|
||||
#define CONFIG_HVBOOT \
|
||||
"setenv bootargs config-addr=0x60000000; " \
|
||||
"bootm 0x01000000 - 0x00f00000"
|
||||
|
||||
#define CONFIG_ALU \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"cpu 1 release 0x01000000 - - -;" \
|
||||
"cpu 2 release 0x01000000 - - -;" \
|
||||
"cpu 3 release 0x01000000 - - -;" \
|
||||
"cpu 4 release 0x01000000 - - -;" \
|
||||
"cpu 5 release 0x01000000 - - -;" \
|
||||
"cpu 6 release 0x01000000 - - -;" \
|
||||
"cpu 7 release 0x01000000 - - -;" \
|
||||
"go 0x01000000"
|
||||
|
||||
#define CONFIG_LINUX \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
667
include/configs/BSC9132QDS.h
Normal file
667
include/configs/BSC9132QDS.h
Normal file
@@ -0,0 +1,667 @@
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* BSC9132 QDS board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_BSC9132QDS
|
||||
#define CONFIG_BSC9132
|
||||
#endif
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_RAMBOOT_SDCARD
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11000000
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
|
||||
#ifdef CONFIG_SPIFLASH
|
||||
#define CONFIG_RAMBOOT_SPIFLASH
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11000000
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0x8ff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE /* BOOKE */
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
|
||||
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#define CONFIG_E1000 /* E1000 pci Ethernet card*/
|
||||
|
||||
/*
|
||||
* PCI Windows
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
/* controller 1, Slot 1, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_TSEC_ENET /* ethernet */
|
||||
|
||||
#if defined(CONFIG_SYS_CLK_100_DDR_100)
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 100000000
|
||||
#elif defined(CONFIG_SYS_CLK_100_DDR_133)
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 133000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_MP
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* enable branch predition */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x01ffffff
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_FSL_DDR3
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
|
||||
#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
|
||||
#define CONFIG_FSL_DDR_INTERACTIVE
|
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE (1024)
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
|
||||
/* DDR3 Controller Settings */
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
|
||||
#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
|
||||
|
||||
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
|
||||
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_1 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
|
||||
#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
|
||||
#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
|
||||
#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
|
||||
|
||||
#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
|
||||
#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
|
||||
#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
|
||||
#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
|
||||
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
|
||||
#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
|
||||
#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
|
||||
#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
|
||||
#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
|
||||
#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
|
||||
#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
|
||||
#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
|
||||
#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
|
||||
#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
|
||||
|
||||
/*FIXME: the following params are constant w.r.t diff freq
|
||||
combinations. this should be removed later
|
||||
*/
|
||||
#if CONFIG_DDR_CLK_FREQ == 100000000
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
|
||||
#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
|
||||
#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
|
||||
#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
|
||||
#elif CONFIG_DDR_CLK_FREQ == 133000000
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
|
||||
#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
|
||||
#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
|
||||
#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
|
||||
#else
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
|
||||
#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
|
||||
#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
|
||||
#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
|
||||
#endif
|
||||
|
||||
|
||||
/* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
/* NOR Flash on IFC */
|
||||
#define CONFIG_SYS_FLASH_BASE 0x88000000
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
|
||||
#define CONFIG_SYS_NOR_CSPR 0x88000101
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
|
||||
/* NOR Flash Timing Params */
|
||||
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
|
||||
| FTIM0_NOR_TEADC(0x03) \
|
||||
| FTIM0_NOR_TAVDS(0x00) \
|
||||
| FTIM0_NOR_TEAHC(0x0f))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
|
||||
| FTIM1_NOR_TRAD_NOR(0x09) \
|
||||
| FTIM1_NOR_TSEQRAD_NOR(0x09))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
|
||||
| FTIM2_NOR_TCH(0x4) \
|
||||
| FTIM2_NOR_TWPH(0x7) \
|
||||
| FTIM2_NOR_TWP(0x1e))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
/* CFI for NOR Flash */
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
/* NAND Flash Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
|
||||
| FTIM0_NAND_TWP(0x05) \
|
||||
| FTIM0_NAND_TWCHT(0x02) \
|
||||
| FTIM0_NAND_TWH(0x04))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
|
||||
| FTIM1_NAND_TWBE(0x1e) \
|
||||
| FTIM1_NAND_TRR(0x07) \
|
||||
| FTIM1_NAND_TRP(0x05))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
|
||||
| FTIM2_NAND_TREH(0x04) \
|
||||
| FTIM2_NAND_TWHRE(0x11))
|
||||
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
|
||||
/* NAND */
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
#define CONFIG_FSL_QIXIS
|
||||
#ifdef CONFIG_FSL_QIXIS
|
||||
#define CONFIG_SYS_FPGA_BASE 0xffb00000
|
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
|
||||
#define QIXIS_LBMAP_SWITCH 9
|
||||
#define QIXIS_LBMAP_MASK 0x07
|
||||
#define QIXIS_LBMAP_SHIFT 0
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x04
|
||||
#define QIXIS_RST_CTL_RESET 0x83
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
|
||||
#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
|
||||
|
||||
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_CSOR2 0x0
|
||||
/* CPLD Timing parameters for IFC CS3 */
|
||||
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x0) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
#endif
|
||||
|
||||
/* Set up IFC registers for boot location NOR/NAND */
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* hush parser */
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#ifdef CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
|
||||
/* enable read and write access to EEPROM */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* I2C FPGA */
|
||||
#define CONFIG_I2C_FPGA
|
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
|
||||
#define CONFIG_RTC_DS3231
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* SPI interface will not be available in case of NAND boot SPI CS0 will be
|
||||
* used for SLIC
|
||||
*/
|
||||
/* eSPI - Enhanced SPI */
|
||||
#define CONFIG_FSL_ESPI /* SPI */
|
||||
#ifdef CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
|
||||
/* TBI PHY configuration for SGMII mode */
|
||||
#define CONFIG_TSEC_TBICR_SETTINGS ( \
|
||||
TBICR_PHY_RESET \
|
||||
| TBICR_ANEG_ENABLE \
|
||||
| TBICR_FULL_DUPLEX \
|
||||
| TBICR_SPEED1_SET \
|
||||
)
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
#define CONFIG_MMC
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#endif
|
||||
|
||||
#define CONFIG_USB_EHCI /* USB */
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_SDCARD)
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */
|
||||
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
#define CONFIG_HOSTNAME BSC9132qds
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin"
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
|
||||
#else
|
||||
#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" CONFIG_UBOOTPATH "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=bsc9132qds.dtb\0" \
|
||||
"bdev=sda1\0" \
|
||||
CONFIG_DEF_HWCONFIG\
|
||||
"othbootargs=mem=880M ramdisk_size=600000 " \
|
||||
"default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
|
||||
"isolcpus=0\0" \
|
||||
"usbext2boot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
"debug_halt_off=mw ff7e0e30 0xf0000000;"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
|
||||
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -35,6 +35,25 @@
|
||||
#define CONFIG_MPC8313 1
|
||||
#define CONFIG_MPC8313ERDB 1
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_INIT_MINIMAL
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_NAND_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
|
||||
#define CONFIG_SPL_PAD_TO 0xfff04000
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
|
||||
@@ -42,13 +61,11 @@
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
|
||||
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
|
||||
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
#endif /* CONFIG_NAND_U_BOOT */
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_NAND */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||
@@ -87,7 +104,7 @@
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
|
||||
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
|
||||
#endif
|
||||
|
||||
@@ -227,7 +244,7 @@
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
|
||||
!defined(CONFIG_NAND_SPL)
|
||||
!defined(CONFIG_SPL_BUILD)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
@@ -256,7 +273,7 @@
|
||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
|
||||
|
||||
/* drivers/mtd/nand/nand.c */
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
|
||||
#define CONFIG_SYS_NAND_BASE 0xFFF00000
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xE2800000
|
||||
@@ -292,7 +309,7 @@
|
||||
| OR_FCM_EHTR)
|
||||
/* 0xFFFF8396 */
|
||||
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
@@ -449,7 +466,7 @@
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_NAND_U_BOOT)
|
||||
#if defined(CONFIG_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET (512 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
@@ -496,7 +513,7 @@
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
@@ -570,7 +587,7 @@
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN)
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_ROM_LOC_NAND_SP_8BIT |\
|
||||
|
||||
@@ -415,6 +415,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_USB_EHCI
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI_PCI
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_PCI_EHCI_DEVICE 0
|
||||
#endif
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
|
||||
@@ -735,7 +735,7 @@
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
|
||||
@@ -490,7 +490,7 @@
|
||||
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
|
||||
|
||||
/* video */
|
||||
#define CONFIG_VIDEO
|
||||
#undef CONFIG_VIDEO
|
||||
|
||||
#if defined(CONFIG_VIDEO)
|
||||
#define CONFIG_BIOSEMU
|
||||
|
||||
@@ -34,6 +34,8 @@
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
|
||||
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
||||
|
||||
@@ -52,6 +52,7 @@
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x80200000\0" \
|
||||
"fdtaddr=0x80F80000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"rdaddr=0x81000000\0" \
|
||||
"bootfile=/boot/uImage\0" \
|
||||
"fdtfile=\0" \
|
||||
@@ -60,12 +61,38 @@
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
|
||||
"nandrootfstype=ubifs rootwait=1\0" \
|
||||
"nandsrcaddr=0x280000\0" \
|
||||
"nandimgsize=0x500000\0" \
|
||||
"rootpath=/export/rootfs\0" \
|
||||
"nfsopts=nolock\0" \
|
||||
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
|
||||
"::off\0" \
|
||||
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
|
||||
"ramrootfstype=ext2\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"spiroot=/dev/mtdblock4 rw\0" \
|
||||
"spirootfstype=jffs2\0" \
|
||||
"spisrcaddr=0xe0000\0" \
|
||||
"spiimgsize=0x362000\0" \
|
||||
"spibusno=0\0" \
|
||||
"spiargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${spiroot} " \
|
||||
"rootfstype=${spirootfstype}\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
||||
"ip=dhcp\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
@@ -80,6 +107,21 @@
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"spiboot=echo Booting from spi ...; " \
|
||||
"run spiargs; " \
|
||||
"sf probe ${spibusno}:0; " \
|
||||
"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"setenv autoload no; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} ${bootfile}; " \
|
||||
"run netargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"ramboot=echo Booting from ramdisk ...; " \
|
||||
"run ramargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
@@ -105,6 +147,8 @@
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"else " \
|
||||
"run nandboot;" \
|
||||
"fi;" \
|
||||
|
||||
/* Clock Defines */
|
||||
@@ -236,8 +280,8 @@
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000
|
||||
#define CONFIG_SPL_MUSB_NEW_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
|
||||
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
@@ -311,8 +355,41 @@
|
||||
#ifdef CONFIG_MUSB_GADGET
|
||||
#define CONFIG_USB_ETHER
|
||||
#define CONFIG_USB_ETH_RNDIS
|
||||
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
|
||||
#endif /* CONFIG_MUSB_GADGET */
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
|
||||
/* disable host part of MUSB in SPL */
|
||||
#undef CONFIG_MUSB_HOST
|
||||
/*
|
||||
* Disable UART, CPSW ethernet support and extra environment settings so we
|
||||
* will fit within 101KiB.
|
||||
*/
|
||||
#undef CONFIG_SPL_ETH_SUPPORT
|
||||
#undef CONFIG_SPL_YMODEM_SUPPORT
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Default to using SPI for environment, etc. We have multiple copies
|
||||
* of SPL as the ROM will check these locations.
|
||||
* 0x0 - 0x20000 : First copy of SPL
|
||||
* 0x20000 - 0x40000 : Second copy of SPL
|
||||
* 0x40000 - 0x60000 : Third copy of SPL
|
||||
* 0x60000 - 0x80000 : Fourth copy of SPL
|
||||
* 0x80000 - 0xDF000 : U-Boot
|
||||
* 0xDF000 - 0xE0000 : U-Boot Environment
|
||||
* 0xE0000 - 0x442000 : Linux Kernel
|
||||
* 0x442000 - 0x800000 : Userland
|
||||
*/
|
||||
#if defined(CONFIG_SPI_BOOT)
|
||||
# undef CONFIG_ENV_IS_NOWHERE
|
||||
# define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */
|
||||
# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
|
||||
#endif /* SPI support */
|
||||
|
||||
/* Unsupported features */
|
||||
#undef CONFIG_USE_IRQ
|
||||
|
||||
@@ -345,10 +422,12 @@
|
||||
/* CS0 */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
|
||||
devices */
|
||||
#if !defined(CONFIG_SPI_BOOT)
|
||||
#undef CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* ! __CONFIG_AM335X_EVM_H */
|
||||
|
||||
@@ -156,8 +156,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
#undef CONFIG_CMD_NET
|
||||
|
||||
@@ -150,8 +150,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
#undef CONFIG_CMD_NET
|
||||
|
||||
@@ -175,7 +175,6 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
#define IMX_FEC_BASE MXS_ENET0_BASE
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#endif
|
||||
|
||||
|
||||
65
include/configs/cardhu.h
Normal file
65
include/configs/cardhu.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include "tegra30-common.h"
|
||||
|
||||
/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra30 (Cardhu) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_TEGRA_ENABLE_UARTA
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_TEGRA_I2C
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_TEGRA_SLINK
|
||||
#define CONFIG_TEGRA_SLINK_CTRLS 6
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -157,8 +157,6 @@
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
|
||||
@@ -37,7 +37,6 @@
|
||||
#define CONFIG_SYS_COREBOOT
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
#define CONFIG_X86_NO_RESET_VECTOR
|
||||
#define CONFIG_SYS_VSNPRINTF
|
||||
#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */
|
||||
#define CONFIG_ZBOOT_32
|
||||
|
||||
50
include/configs/dalmore.h
Normal file
50
include/configs/dalmore.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include "tegra114-common.h"
|
||||
|
||||
/* Must be off for Dalmore to boot !?!? FIXME */
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra114 (Dalmore) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_TEGRA_ENABLE_UARTD
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -108,8 +108,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/* TWL4030 */
|
||||
|
||||
@@ -141,8 +141,6 @@
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/*
|
||||
|
||||
@@ -1,619 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Graeme Russ, graeme.russ@gmail.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/ibmpc.h>
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_SYS_SC520
|
||||
#define CONFIG_SYS_SC520_SSI
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Watchdog Configuration
|
||||
* NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
|
||||
* bottom (processor) board MUST be removed!
|
||||
*/
|
||||
#undef CONFIG_WATCHDOG
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Real Time Clock Configuration
|
||||
*/
|
||||
#define CONFIG_RTC_MC146818
|
||||
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK 1843200
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
|
||||
9600, 19200, 38400, 115200}
|
||||
#define CONFIG_SYS_NS16550_COM1 UART0_BASE
|
||||
#define CONFIG_SYS_NS16550_COM2 UART1_BASE
|
||||
#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
|
||||
#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
|
||||
#define CONFIG_SYS_NS16550_PORT_MAPPED
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Video Configuration
|
||||
*/
|
||||
#undef CONFIG_VIDEO
|
||||
#undef CONFIG_CFB_CONSOLE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_BDI
|
||||
#define CONFIG_CMD_BOOTD
|
||||
#define CONFIG_CMD_CONSOLE
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_FPGA
|
||||
#define CONFIG_CMD_IMI
|
||||
#define CONFIG_CMD_IMLS
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_ITEST
|
||||
#define CONFIG_CMD_LOADB
|
||||
#define CONFIG_CMD_LOADS
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_MISC
|
||||
#define CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_RUN
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_SETGETDCR
|
||||
#define CONFIG_CMD_SOURCE
|
||||
#define CONFIG_CMD_XIMG
|
||||
#define CONFIG_CMD_ZBOOT
|
||||
|
||||
#define CONFIG_BOOTDELAY 15
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200
|
||||
#define CONFIG_KGDB_SER_INDEX 2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_PROMPT "boot > "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + \
|
||||
16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x01000000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
|
||||
#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
|
||||
/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
|
||||
#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
|
||||
#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
|
||||
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
|
||||
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CPU Features
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_HIGH_SPEED 0
|
||||
#define CONFIG_SYS_SC520_RESET
|
||||
#define CONFIG_SYS_SC520_TIMER
|
||||
#undef CONFIG_SYS_GENERIC_TIMER
|
||||
#define CONFIG_SYS_PCAT_INTERRUPTS
|
||||
#define CONFIG_SYS_NUM_IRQS 16
|
||||
#define CONFIG_SYS_PC_BIOS
|
||||
#define CONFIG_SYS_PCI_BIOS
|
||||
#define CONFIG_SYS_X86_REALMODE
|
||||
#define CONFIG_SYS_X86_ISR_TIMER
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory organization:
|
||||
* 32kB Stack
|
||||
* 16kB Cache-As-RAM @ 0x19200000
|
||||
* 256kB Monitor
|
||||
* (128kB + Environment Sector Size) malloc pool
|
||||
*/
|
||||
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
|
||||
#define CONFIG_SYS_CAR_ADDR 0x19200000
|
||||
#define CONFIG_SYS_CAR_SIZE (16 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \
|
||||
128*1024)
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH configuration
|
||||
* 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
|
||||
* 16MB StrataFlash #1 @ 0x10000000
|
||||
* 16MB StrataFlash #2 @ 0x11000000
|
||||
*/
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_FLASH_CFI_LEGACY
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 3
|
||||
#define CONFIG_SYS_FLASH_BASE 0x38000000
|
||||
#define CONFIG_SYS_FLASH_BASE_1 0x10000000
|
||||
#define CONFIG_SYS_FLASH_BASE_2 0x11000000
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
|
||||
CONFIG_SYS_FLASH_BASE_1, \
|
||||
CONFIG_SYS_FLASH_BASE_2}
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
|
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment configuration
|
||||
* - Boot flash is 512kB with 64kB sectors
|
||||
* - StrataFlash is 32MB with 128kB sectors
|
||||
* - Redundant embedded environment is 25% of the Boot flash
|
||||
* - Redundant StrataFlash environment is <1% of the StrataFlash
|
||||
* - Environment is therefore located in StrataFlash
|
||||
* - Primary copy is located in first sector of first flash
|
||||
* - Redundant copy is located in second sector of first flash
|
||||
* - Stack is only 32kB, so environment size is limited to 4kB
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_SIZE 0x01000
|
||||
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI configuration
|
||||
*/
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_SYS_FIRST_PCI_IRQ 10
|
||||
#define CONFIG_SYS_SECOND_PCI_IRQ 9
|
||||
#define CONFIG_SYS_THIRD_PCI_IRQ 11
|
||||
#define CONFIG_SYS_FORTH_PCI_IRQ 15
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Network device (TRL8100B) support
|
||||
*/
|
||||
#define CONFIG_RTL8139
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BOOTCS Control (for AM29LV040B-120JC)
|
||||
*
|
||||
* 000 0 00 0 000 11 0 011 }- 0x0033
|
||||
* \ / | \| | \ / \| | \ /
|
||||
* | | | | | | | |
|
||||
* | | | | | | | +---- 3 Wait States (First Access)
|
||||
* | | | | | | +------- Reserved
|
||||
* | | | | | +--------- 3 Wait States (Subsequent Access)
|
||||
* | | | | +------------- Reserved
|
||||
* | | | +---------------- Non-Paged Mode
|
||||
* | | +------------------ 8 Bit Wide
|
||||
* | +--------------------- GP Bus
|
||||
* +------------------------ Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* ROMCS Control (for E28F128J3A-150 StrataFlash)
|
||||
*
|
||||
* 000 0 01 1 000 01 0 101 }- 0x0615
|
||||
* \ / | \| | \ / \| | \ /
|
||||
* | | | | | | | |
|
||||
* | | | | | | | +---- 5 Wait States (First Access)
|
||||
* | | | | | | +------- Reserved
|
||||
* | | | | | +--------- 1 Wait State (Subsequent Access)
|
||||
* | | | | +------------- Reserved
|
||||
* | | | +---------------- Paged Mode
|
||||
* | | +------------------ 16 Bit Wide
|
||||
* | +--------------------- GP Bus
|
||||
* +------------------------ Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
|
||||
#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SC520 General Purpose Bus configuration
|
||||
*
|
||||
* Chip Select Offset 1 Clock Cycle
|
||||
* Chip Select Pulse Width 8 Clock Cycles
|
||||
* Chip Select Read Offset 2 Clock Cycles
|
||||
* Chip Select Read Width 6 Clock Cycles
|
||||
* Chip Select Write Offset 2 Clock Cycles
|
||||
* Chip Select Write Width 6 Clock Cycles
|
||||
* Chip Select Recovery Time 2 Clock Cycles
|
||||
*
|
||||
* Timing Diagram (from SC520 Register Set Manual - Order #22005B)
|
||||
*
|
||||
* |<-------------General Purpose Bus Cycle---------------->|
|
||||
* | |
|
||||
* ----------------------\__________________/------------------
|
||||
* |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
|
||||
*
|
||||
* ------------------------\_______________/-------------------
|
||||
* |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
|
||||
*
|
||||
* --------------------------\_______________/-----------------
|
||||
* |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
|
||||
*
|
||||
* ________/-----------\_______________________________________
|
||||
* |<--->|<--------->|
|
||||
* ^ ^
|
||||
* (GPALEOFF + 1) |
|
||||
* |
|
||||
* (GPALEW + 1)
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_GPCSOFF 0x00
|
||||
#define CONFIG_SYS_SC520_GPCSPW 0x07
|
||||
#define CONFIG_SYS_SC520_GPRDOFF 0x01
|
||||
#define CONFIG_SYS_SC520_GPRDW 0x05
|
||||
#define CONFIG_SYS_SC520_GPWROFF 0x01
|
||||
#define CONFIG_SYS_SC520_GPWRW 0x05
|
||||
#define CONFIG_SYS_SC520_GPCSRT 0x01
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SC520 Programmable I/O configuration
|
||||
*
|
||||
* Pin Mode Dir. Description
|
||||
* ----------------------------------------------------------------------
|
||||
* PIO0 PIO Output Unused
|
||||
* PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
|
||||
* PIO2 PIO Output Auxiliary power output enable
|
||||
* PIO3 GPAEN Output GP Bus Address Enable
|
||||
* PIO4 PIO Output Top Board Enable (active low)
|
||||
* PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
|
||||
* PIO6 PIO Input Data output of Power Supply ADC
|
||||
* PIO7 PIO Output Clock input to Power Supply ADC
|
||||
* PIO8 PIO Output Chip Select input of Power Supply ADC
|
||||
* PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
|
||||
* PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
|
||||
* PIO11 PIO Input StrataFlash 1 Status
|
||||
* PIO12 PIO Input StrataFlash 2 Status
|
||||
* PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
|
||||
* PIO14 PIO Input Low Input Voltage Warning (active low)
|
||||
* PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
|
||||
* PIO16 PIO Input Power Fail
|
||||
* PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
|
||||
* PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
|
||||
* PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
|
||||
* PIO20 GPIRQ3 Input UART D IRQ
|
||||
* PIO21 GPIRQ2 Input UART C IRQ
|
||||
* PIO22 GPIRQ1 Input UART B IRQ
|
||||
* PIO23 GPIRQ0 Input UART A IRQ
|
||||
* PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
|
||||
* PIO25 PIO Input Battery OK Indication
|
||||
* PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
|
||||
* PIO27 GPCS0# Output SRAM 1 Chip Select
|
||||
* PIO28 PIO Input Top Board UART CTS
|
||||
* PIO29 PIO Output FPGA Program Mode (active low)
|
||||
* PIO30 PIO Input FPGA Initialised (active low)
|
||||
* PIO31 PIO Input FPGA Done (active low)
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
|
||||
#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
|
||||
#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
|
||||
#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PIO Pin defines
|
||||
*/
|
||||
#define CONFIG_SYS_ENET_AUX_PWR 0x0004
|
||||
#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
|
||||
#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
|
||||
#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
|
||||
#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
|
||||
#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
|
||||
#define CONFIG_SYS_ENET_SF1_MODE 0x0200
|
||||
#define CONFIG_SYS_ENET_SF2_MODE 0x0400
|
||||
#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
|
||||
#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
|
||||
#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
|
||||
#define CONFIG_SYS_ENET_WATCHDOG 0x8000
|
||||
|
||||
#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
|
||||
#define CONFIG_SYS_ENET_BAT_OK 0x0200
|
||||
#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
|
||||
#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
|
||||
#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
|
||||
#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chip Select Pin Function Select
|
||||
*
|
||||
* 1 1 1 1 1 0 0 0 }- 0xf8
|
||||
* | | | | | | | |
|
||||
* | | | | | | | +--- Reserved
|
||||
* | | | | | | +----- GPCS1_SEL = ROMCS1#
|
||||
* | | | | | +------- GPCS2_SEL = ROMCS2#
|
||||
* | | | | +--------- GPCS3_SEL = GPCS3
|
||||
* | | | +----------- GPCS4_SEL = GPCS4
|
||||
* | | +------------- GPCS5_SEL = GPCS5
|
||||
* | +--------------- GPCS6_SEL = GPCS6
|
||||
* +----------------- GPCS7_SEL = GPCS7
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_CSPFS 0xf8
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clock Select (CLKTIMER[CLKTEST] pin)
|
||||
*
|
||||
* 0 111 00 1 0 }- 0x72
|
||||
* | \ / \| | |
|
||||
* | | | | +--- Pin Disabled
|
||||
* | | | +----- Pin is an output
|
||||
* | | +------- Reserved
|
||||
* | +----------- Disabled (pin stays Low)
|
||||
* +-------------- Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_CLKSEL 0x72
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Address Decode Control
|
||||
*
|
||||
* 0 00 0 0 0 0 0 }- 0x00
|
||||
* | \| | | | | |
|
||||
* | | | | | | +--- Integrated UART 1 is enabled
|
||||
* | | | | | +----- Integrated UART 2 is enabled
|
||||
* | | | | +------- Integrated RTC is enabled
|
||||
* | | | +--------- Reserved
|
||||
* | | +----------- I/O Hole accesses are forwarded to the external GP bus
|
||||
* | +------------- Reserved
|
||||
* +---------------- Write-protect violations do not generate an IRQ
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_ADDDECCTL 0x00
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* UART Control
|
||||
*
|
||||
* 00000 1 1 1 }- 0x07
|
||||
* \___/ | | |
|
||||
* | | | +--- Transmit TC interrupt enable
|
||||
* | | +----- Receive TC interrupt enable
|
||||
* | +------- 1.8432 MHz
|
||||
* +----------- Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_UART1CTL 0x07
|
||||
#define CONFIG_SYS_SC520_UART2CTL 0x07
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* System Arbiter Control
|
||||
*
|
||||
* 00000 1 1 0 }- 0x06
|
||||
* \___/ | | |
|
||||
* | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
|
||||
* | | +----- The system arbiter operates in concurrent mode
|
||||
* | +------- Park the PCI bus on the last master that acquired the bus
|
||||
* +----------- Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SYSARBCTL 0x06
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* System Arbiter Master Enable
|
||||
*
|
||||
* 00000000000 0 0 0 1 1 }- 0x06
|
||||
* \_________/ | | | | |
|
||||
* | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
|
||||
* | | | | +----- PCI master REQ1 enabled (Ethernet 2)
|
||||
* | | | +------- PCI master REQ2 disabled
|
||||
* | | +--------- PCI master REQ3 disabled
|
||||
* | +----------- PCI master REQ4 disabled
|
||||
* +------------------ Reserved
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* System Arbiter Master Enable
|
||||
*
|
||||
* 0 0000 0 00 0000 1 000 }- 0x06
|
||||
* | \__/ | \| \__/ | \_/
|
||||
* | | | | | | +---- Reserved
|
||||
* | | | | | +------- Enable CPU-to-PCI bus write posting
|
||||
* | | | | +---------- Reserved
|
||||
* | | | +-------------- PCI bus reads to SDRAM are not automatically
|
||||
* | | | retried
|
||||
* | | +----------------- Target read FIFOs are not snooped during write
|
||||
* | | transactions
|
||||
* | +-------------------- Reserved
|
||||
* +------------------------ Deassert the PCI bus reset signal
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_HBCTL 0x08
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
|
||||
* 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
|
||||
* \ / | | | | \----+----/ \-----+------/
|
||||
* | | | | | | +---------- Start at 0x38000000
|
||||
* | | | | | +----------------------- 512kB Region Size
|
||||
* | | | | | ((7 + 1) * 64kB)
|
||||
* | | | | +------------------------------ 64kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled (So it can be
|
||||
* | | | reprogrammed!)
|
||||
* | | +---------------------------------- Caching Disabled
|
||||
* | +------------------------------------ Execution Enabled
|
||||
* +--------------------------------------- BOOTCS
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache-As-RAM (Targets Boot Flash)
|
||||
*
|
||||
* 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
|
||||
* \ / | | | | \--+--/ \-------+--------/
|
||||
* | | | | | | +------------ Start at 0x19200000
|
||||
* | | | | | +------------------------- 64k Region Size
|
||||
* | | | | | ((15 + 1) * 4kB)
|
||||
* | | | | +------------------------------ 4kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled
|
||||
* | | +---------------------------------- Caching Enabled
|
||||
* | +------------------------------------ Execution Prevented
|
||||
* +--------------------------------------- BOOTCS
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
|
||||
*
|
||||
* 001 110 0 000100000 0001000000000000 }- 0x38201000
|
||||
* \ / \ / | \---+---/ \------+-------/
|
||||
* | | | | +----------- Start at 0x00001000
|
||||
* | | | +------------------------ 33 Bytes (0x20 + 1)
|
||||
* | | +------------------------------ Ignored
|
||||
* | +--------------------------------- GPCS6
|
||||
* +------------------------------------- GP Bus I/O
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
|
||||
* PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
|
||||
*
|
||||
* 010 101 0 0000000 100000000000000000 }- 0x54020000
|
||||
* 010 111 0 0000000 100000000000000001 }- 0x5c020001
|
||||
* \ / \ / | \--+--/ \-------+--------/
|
||||
* | | | | +------------ Start at 0x200000000
|
||||
* | | | | 0x200010000
|
||||
* | | | +------------------------- 4kB Region Size
|
||||
* | | | ((0 + 1) * 4kB)
|
||||
* | | +------------------------------ 4k Page Size
|
||||
* | +--------------------------------- GPCS5
|
||||
* | GPCS7
|
||||
* +------------------------------------- GP Bus Memory
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
|
||||
#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
|
||||
* PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
|
||||
* PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
|
||||
* PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
|
||||
*
|
||||
* 001 000 0 000000111 0001001111111000 }- 0x200713f8
|
||||
* 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
|
||||
* 001 011 0 000000111 0001001011111000 }- 0x300711f8
|
||||
* 001 011 0 000000111 0001001011111000 }- 0x340710f8
|
||||
* \ / \ / | \---+---/ \------+-------/
|
||||
* | | | | +----------- Start at 0x013f8
|
||||
* | | | | 0x012f8
|
||||
* | | | | 0x011f8
|
||||
* | | | | 0x010f8
|
||||
* | | | +------------------------ 33 Bytes (32 + 1)
|
||||
* | | +------------------------------ Ignored
|
||||
* | +--------------------------------- GPCS6
|
||||
* +------------------------------------- GP Bus I/O
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
|
||||
#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
|
||||
#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
|
||||
#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
|
||||
* PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
|
||||
*
|
||||
* 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
|
||||
* 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
|
||||
* \ / | | | | \----+----/ \-----+------/
|
||||
* | | | | | | +---------- Start at 0x10000000
|
||||
* | | | | | | 0x11000000
|
||||
* | | | | | +----------------------- 16MB Region Size
|
||||
* | | | | | ((255 + 1) * 64kB)
|
||||
* | | | | +------------------------------ 64kB Page Size
|
||||
* | | | +-------------------------------- Writes Enabled
|
||||
* | | +---------------------------------- Caching Disabled
|
||||
* | +------------------------------------ Execution Enabled
|
||||
* +--------------------------------------- ROMCS1
|
||||
* ROMCS2
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
|
||||
#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
|
||||
* PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
|
||||
*
|
||||
* 010 000 1 00000001111 01100100000000 }- 0x4203d900
|
||||
* 010 011 1 00000001111 01100100010000 }- 0x4e03d910
|
||||
* \ / \ / | \----+----/ \-----+------/
|
||||
* | | | | +---------- Start at 0x19000000
|
||||
* | | | | 0x19100000
|
||||
* | | | +----------------------- 1MB Region Size
|
||||
* | | | ((15 + 1) * 64kB)
|
||||
* | | +------------------------------ 64kB Page Size
|
||||
* | +--------------------------------- GPCS0
|
||||
* | GPCS3
|
||||
* +------------------------------------- GP Bus Memory
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
|
||||
#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
|
||||
*
|
||||
* 010 100 0 00000000 11000000100000000 }- 0x50018100
|
||||
* \ / \ / | \---+--/ \-------+-------/
|
||||
* | | | | +----------- Start at 0x18100000
|
||||
* | | | +------------------------ 4kB Region Size
|
||||
* | | | ((0 + 1) * 4kB)
|
||||
* | | +------------------------------ 4kB Page Size
|
||||
* | +--------------------------------- GPCS4
|
||||
* +------------------------------------- GP Bus Memory
|
||||
*/
|
||||
#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -42,6 +42,7 @@
|
||||
#define CONFIG_MACH_DAVINCI_DA850_EVM
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
|
||||
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
|
||||
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
|
||||
#define CONFIG_SYS_OSCIN_FREQ 24000000
|
||||
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/omap3.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
@@ -85,6 +86,12 @@
|
||||
#define CONFIG_OMAP_HSMMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
/* define to enable boot progress via leds */
|
||||
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
|
||||
(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_MUSB_UDC 1
|
||||
#define CONFIG_USB_OMAP3 1
|
||||
@@ -115,7 +122,10 @@
|
||||
#ifdef CONFIG_BOOT_NAND
|
||||
#define CONFIG_CMD_NAND
|
||||
#endif
|
||||
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
|
||||
(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
|
||||
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
|
||||
#endif
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_NFS /* NFS support */
|
||||
@@ -129,8 +139,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/*
|
||||
|
||||
@@ -151,7 +151,6 @@
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C
|
||||
|
||||
/* RTC */
|
||||
|
||||
@@ -42,6 +42,7 @@
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
@@ -77,6 +78,13 @@
|
||||
"ext2load mmc 0 0x17000000 /boot/uImage;" \
|
||||
"bootm"
|
||||
|
||||
/* LCD support */
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_PWM_TEGRA
|
||||
#define CONFIG_VIDEO_TEGRA
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -120,10 +120,6 @@
|
||||
# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
|
||||
#endif
|
||||
|
||||
/* FSL */
|
||||
/* #define CONFIG_SYS_FSL_2 */
|
||||
/* #define FSL_INTR_2 1 */
|
||||
|
||||
/*
|
||||
* memory layout - Example
|
||||
* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
|
||||
|
||||
@@ -178,8 +178,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
|
||||
|
||||
@@ -100,8 +100,6 @@
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
|
||||
/*
|
||||
* PISMO support
|
||||
|
||||
@@ -138,8 +138,6 @@
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/*
|
||||
|
||||
@@ -90,9 +90,9 @@
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3 3 /* UART3 */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
|
||||
#define CONFIG_SERIAL1 1 /* UART1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
@@ -102,6 +102,10 @@
|
||||
#define CONFIG_OMAP_HSMMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
/* silent console by default */
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1
|
||||
#define CONFIG_SILENT_CONSOLE 1
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_MUSB_UDC 1
|
||||
#define CONFIG_USB_OMAP3 1
|
||||
@@ -142,8 +146,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
|
||||
@@ -154,19 +156,23 @@
|
||||
|
||||
/* Environment information */
|
||||
#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTDELAY 0
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "S"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"silent=true\0" \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"usbtty=cdc_acm\0" \
|
||||
"console=ttyO2,115200n8\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"mpurate=600\0" \
|
||||
"vram=12M\0" \
|
||||
"dvimode=1024x768-24@60\0" \
|
||||
"defaultdisplay=dvi\0" \
|
||||
"fpgafilename=mvbluelynx_x.rbf\0" \
|
||||
"loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
|
||||
"fpga load 0 ${loadaddr} ${filesize}; " \
|
||||
"loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
|
||||
"/lib/firmware/mvblx/${fpgafilename}; then " \
|
||||
"fpga load 0 ${loadaddr} ${filesize}; " \
|
||||
"fi;\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
@@ -179,6 +185,7 @@
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype} " \
|
||||
"mvfw.fpgavers=${fpgavers} " \
|
||||
"${cmdline_suffix}\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
|
||||
@@ -126,8 +126,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/*
|
||||
|
||||
@@ -132,8 +132,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
|
||||
|
||||
@@ -136,8 +136,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/*
|
||||
|
||||
@@ -156,8 +156,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/*
|
||||
|
||||
@@ -91,8 +91,6 @@
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
|
||||
@@ -159,6 +157,9 @@
|
||||
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
|
||||
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
|
||||
"env import -t ${loadaddr} ${filesize}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc${mmcdev} ...; " \
|
||||
"run mmcargs; " \
|
||||
@@ -166,12 +167,20 @@
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"fi; " \
|
||||
"if run loadbootenv; then " \
|
||||
"run importbootenv; " \
|
||||
"fi;" \
|
||||
"if test -n ${uenvcmd}; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"fi; " \
|
||||
"fi"
|
||||
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
/* SD/MMC */
|
||||
#define CONFIG_MMC
|
||||
@@ -71,6 +72,14 @@
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
||||
/* LCD support */
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_PWM_TEGRA
|
||||
#define CONFIG_VIDEO_TEGRA
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||
#define CONFIG_CONSOLE_SCROLL_LINES 10
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
301
include/configs/pcm051.h
Normal file
301
include/configs/pcm051.h
Normal file
@@ -0,0 +1,301 @@
|
||||
/*
|
||||
* pcm051.h
|
||||
*
|
||||
* Phytec phyCORE-AM335x (pcm051) boards information header
|
||||
*
|
||||
* Copyright (C) 2013 Lemonage Software GmbH
|
||||
* Author Lars Poeschel <poeschel@lemonage.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PCM051_H
|
||||
#define __CONFIG_PCM051_H
|
||||
|
||||
#define CONFIG_AM33XX
|
||||
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define CONFIG_DMA_COHERENT
|
||||
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
|
||||
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT "U-Boot# "
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define MACH_TYPE_PCM051 4144 /* Until the next sync */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
/* set to negative value for no autoboot */
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x80007fc0\0" \
|
||||
"fdtaddr=0x80000000\0" \
|
||||
"rdaddr=0x81000000\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"fdtfile=pcm051.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
|
||||
"ramrootfstype=ext2\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
"ramargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${ramroot} " \
|
||||
"rootfstype=${ramrootfstype}\0" \
|
||||
"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
||||
"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
|
||||
"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"ramboot=echo Booting from ramdisk ...; " \
|
||||
"run ramargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 25000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#define CONFIG_CMD_ECHO
|
||||
|
||||
/* max number of command args */
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 512
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/*
|
||||
* memtest works on 8 MB in DRAM after skipping 32MB from
|
||||
* start addr of ram disk
|
||||
*/
|
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
|
||||
+ (8 * 1024 * 1024))
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */
|
||||
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_OMAP_HSMMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_OMAP3_SPI
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
|
||||
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
/* Platform/Board specific defs */
|
||||
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
/* NS16550 Configuration */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK (48000000)
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
|
||||
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
|
||||
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
|
||||
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
|
||||
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
|
||||
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_DRIVER_OMAP24XX_I2C
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
|
||||
#define CONFIG_OMAP_GPIO
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
|
||||
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x402F0400
|
||||
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
|
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
||||
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
||||
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||
#define CONFIG_SPL_NET_SUPPORT
|
||||
#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
|
||||
#define CONFIG_SPL_ETH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
|
||||
|
||||
/*
|
||||
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
|
||||
* 64 bytes before this address should be set aside for u-boot.img's
|
||||
* header. That is 0x800FFFC0--0x80100000 should not be used for any
|
||||
* other needs.
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||
|
||||
/* Since SPL did pll and ddr initialization for us,
|
||||
* we don't need to do it twice.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB configuration
|
||||
*/
|
||||
#define CONFIG_USB_MUSB_DSPS
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
#define CONFIG_MUSB_GADGET
|
||||
#define CONFIG_MUSB_PIO_ONLY
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_MUSB_HOST
|
||||
#define CONFIG_AM335X_USB0
|
||||
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
|
||||
#define CONFIG_AM335X_USB1
|
||||
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
||||
|
||||
#ifdef CONFIG_MUSB_HOST
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MUSB_GADGET
|
||||
#define CONFIG_USB_ETHER
|
||||
#define CONFIG_USB_ETH_RNDIS
|
||||
#endif /* CONFIG_MUSB_GADGET */
|
||||
|
||||
/* Unsupported features */
|
||||
#undef CONFIG_USE_IRQ
|
||||
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_DRIVER_TI_CPSW
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#endif /* ! __CONFIG_PCM051_H */
|
||||
@@ -159,7 +159,6 @@
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
@@ -213,14 +213,14 @@ unsigned long get_board_ddr_clk(void);
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
|
||||
FTIM0_NOR_TEADC(0x01) | \
|
||||
FTIM0_NOR_TEAHC(0x20))
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
|
||||
FTIM2_NOR_TCH(0x0E) | \
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
@@ -259,7 +259,7 @@ unsigned long get_board_ddr_clk(void);
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
|
||||
#define CONFIG_SYS_CSOR3 0x0
|
||||
/* QIXIS Timing parameters for IFC CS3 */
|
||||
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
|
||||
@@ -131,8 +131,6 @@
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
|
||||
@@ -36,13 +36,13 @@
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra20 (TEC) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
|
||||
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
/* SD/MMC */
|
||||
#define CONFIG_MMC
|
||||
@@ -85,6 +85,13 @@
|
||||
"ext2load mmc 0 0x17000000 /boot/uImage;" \
|
||||
"bootm"
|
||||
|
||||
/* LCD support */
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_PWM_TEGRA
|
||||
#define CONFIG_VIDEO_TEGRA
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -119,33 +119,6 @@
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x10000000\0" \
|
||||
"kernel_addr_r=0x01000000\0" \
|
||||
"fdt_addr_r=0x02000000\0" \
|
||||
"ramdisk_addr_r=0x02100000\0" \
|
||||
|
||||
#ifdef CONFIG_TEGRA_KEYBOARD
|
||||
#define STDIN_KBD_KBC ",tegra-kbc"
|
||||
#else
|
||||
@@ -160,10 +133,17 @@
|
||||
#define STDIN_KBD_USB ""
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_TEGRA
|
||||
#define STDOUT_LCD ",lcd"
|
||||
#else
|
||||
#define STDOUT_LCD ""
|
||||
#endif
|
||||
|
||||
#define TEGRA_DEVICE_SETTINGS \
|
||||
"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
|
||||
"stdout=serial,lcd\0" \
|
||||
"stderr=serial,lcd\0" \
|
||||
"stdout=serial" STDOUT_LCD "\0" \
|
||||
"stderr=serial" STDOUT_LCD "\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
TEGRA_DEVICE_SETTINGS \
|
||||
|
||||
160
include/configs/tegra-common.h
Normal file
160
include/configs/tegra-common.h
Normal file
@@ -0,0 +1,160 @@
|
||||
/*
|
||||
* (C) Copyright 2010-2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA_COMMON_H
|
||||
#define __TEGRA_COMMON_H
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
|
||||
#define CONFIG_TEGRA /* which is a Tegra generic machine */
|
||||
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#include <asm/arch/tegra.h> /* get chip and board defs */
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
|
||||
|
||||
/*
|
||||
* PllX Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* include default commands */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
/* remove unused commands */
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration support */
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NFS /* NFS support */
|
||||
#undef CONFIG_CMD_NET /* network support */
|
||||
|
||||
/* turn on command-line edit/hist/auto */
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_COMMAND_HISTORY
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
/*
|
||||
* Increasing the size of the IO buffer as default nfsargs size is more
|
||||
* than 256 and so it is not possible to edit it
|
||||
*/
|
||||
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
||||
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_TEGRA_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_ENTERRCM
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_RAM_DEVICE
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_NAND_SIMPLE
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
|
||||
#endif /* _TEGRA_COMMON_H_ */
|
||||
79
include/configs/tegra114-common.h
Normal file
79
include/configs/tegra114-common.h
Normal file
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_COMMON_H_
|
||||
#define _TEGRA114_COMMON_H_
|
||||
#include "tegra-common.h"
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
|
||||
|
||||
/* Environment information, boards can override if required */
|
||||
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
|
||||
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x8010E000
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x90000000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80108000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
|
||||
#define CONFIG_SPL_STACK 0x800ffffc
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra114/u-boot-spl.lds"
|
||||
|
||||
#endif /* _TEGRA114_COMMON_H_ */
|
||||
@@ -21,80 +21,81 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA20_COMMON_H
|
||||
#define __TEGRA20_COMMON_H
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#ifndef _TEGRA20_COMMON_H_
|
||||
#define _TEGRA20_COMMON_H_
|
||||
#include "tegra-common.h"
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
|
||||
#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
|
||||
#define CONFIG_TEGRA /* which is a Tegra generic machine */
|
||||
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
|
||||
#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
/* Environment information, boards can override if required */
|
||||
#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
|
||||
|
||||
#include <asm/arch/tegra.h> /* get chip and board defs */
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
|
||||
#define CONFIG_STACKBASE 0x02800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0010E000
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x10000000\0" \
|
||||
"kernel_addr_r=0x01000000\0" \
|
||||
"fdt_addr_r=0x02000000\0" \
|
||||
"ramdisk_addr_r=0x02100000\0"
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00108000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
|
||||
#define CONFIG_SPL_STACK 0x000ffffc
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
|
||||
|
||||
/* Align LCD to 1MB boundary */
|
||||
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
|
||||
|
||||
#ifdef CONFIG_TEGRA_LP0
|
||||
#define TEGRA_LP0_ADDR 0x1C406000
|
||||
#define TEGRA_LP0_SIZE 0x2000
|
||||
#define TEGRA_LP0_VEC \
|
||||
"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
|
||||
"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
|
||||
"@" __stringify(TEGRA_LP0_ADDR) " "
|
||||
#else
|
||||
#define TEGRA_LP0_VEC
|
||||
#endif
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
|
||||
|
||||
/*
|
||||
* PllX Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
/*
|
||||
* This parameter affects a TXFILLTUNING field that controls how much data is
|
||||
* sent to the latency fifo before it is sent to the wire. Without this
|
||||
@@ -107,105 +108,13 @@
|
||||
/* Total I2C ports on Tegra20 */
|
||||
#define TEGRA_I2C_NUM_CONTROLLERS 4
|
||||
|
||||
/* include default commands */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
#define CONFIG_CMD_PART
|
||||
|
||||
/* remove unused commands */
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration support */
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NFS /* NFS support */
|
||||
#undef CONFIG_CMD_NET /* network support */
|
||||
|
||||
/* turn on command-line edit/hist/auto */
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_COMMAND_HISTORY
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
|
||||
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
/*
|
||||
* Increasing the size of the IO buffer as default nfsargs size is more
|
||||
* than 256 and so it is not possible to edit it
|
||||
*/
|
||||
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_STACKBASE 0x2800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0010c000
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_TEGRA_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_ENTERRCM
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_RAM_DEVICE
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_NAND_SIMPLE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00108000
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
|
||||
#define CONFIG_SPL_STACK 0x000ffffc
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
|
||||
|
||||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* Misc utility code */
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
#endif /* __TEGRA20_COMMON_H */
|
||||
#endif /* _TEGRA20_COMMON_H_ */
|
||||
|
||||
89
include/configs/tegra30-common.h
Normal file
89
include/configs/tegra30-common.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* (C) Copyright 2010-2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_COMMON_H_
|
||||
#define _TEGRA30_COMMON_H_
|
||||
#include "tegra-common.h"
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
|
||||
|
||||
/* Environment information, boards can override if required */
|
||||
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
|
||||
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x8010E000
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x90000000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80108000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
|
||||
#define CONFIG_SPL_STACK 0x800ffffc
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
|
||||
|
||||
/* Total I2C ports on Tegra30 */
|
||||
#define TEGRA_I2C_NUM_CONTROLLERS 5
|
||||
|
||||
#endif /* _TEGRA30_COMMON_H_ */
|
||||
@@ -98,8 +98,6 @@
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
/* TWL4030 */
|
||||
|
||||
@@ -58,6 +58,11 @@
|
||||
#define CONFIG_ZYNQ_GEM
|
||||
#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
|
||||
|
||||
#if defined(CONFIG_ZYNQ_DCC)
|
||||
# define CONFIG_ARM_DCC
|
||||
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTP_SERVERIP
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
|
||||
@@ -98,9 +98,6 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');}
|
||||
#define TOUPPER(c) if ((c) >= 'a' && (c) <= 'z') \
|
||||
(c) -= ('a' - 'A');
|
||||
#define START(dent) (FAT2CPU16((dent)->start) \
|
||||
+ (mydata->fatsize != 32 ? 0 : \
|
||||
(FAT2CPU16((dent)->starthi) << 16)))
|
||||
|
||||
@@ -4,45 +4,45 @@
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct fdt_header {
|
||||
uint32_t magic; /* magic word FDT_MAGIC */
|
||||
uint32_t totalsize; /* total size of DT block */
|
||||
uint32_t off_dt_struct; /* offset to structure */
|
||||
uint32_t off_dt_strings; /* offset to strings */
|
||||
uint32_t off_mem_rsvmap; /* offset to memory reserve map */
|
||||
uint32_t version; /* format version */
|
||||
uint32_t last_comp_version; /* last compatible version */
|
||||
fdt32_t magic; /* magic word FDT_MAGIC */
|
||||
fdt32_t totalsize; /* total size of DT block */
|
||||
fdt32_t off_dt_struct; /* offset to structure */
|
||||
fdt32_t off_dt_strings; /* offset to strings */
|
||||
fdt32_t off_mem_rsvmap; /* offset to memory reserve map */
|
||||
fdt32_t version; /* format version */
|
||||
fdt32_t last_comp_version; /* last compatible version */
|
||||
|
||||
/* version 2 fields below */
|
||||
uint32_t boot_cpuid_phys; /* Which physical CPU id we're
|
||||
fdt32_t boot_cpuid_phys; /* Which physical CPU id we're
|
||||
booting on */
|
||||
/* version 3 fields below */
|
||||
uint32_t size_dt_strings; /* size of the strings block */
|
||||
fdt32_t size_dt_strings; /* size of the strings block */
|
||||
|
||||
/* version 17 fields below */
|
||||
uint32_t size_dt_struct; /* size of the structure block */
|
||||
fdt32_t size_dt_struct; /* size of the structure block */
|
||||
};
|
||||
|
||||
struct fdt_reserve_entry {
|
||||
uint64_t address;
|
||||
uint64_t size;
|
||||
fdt64_t address;
|
||||
fdt64_t size;
|
||||
};
|
||||
|
||||
struct fdt_node_header {
|
||||
uint32_t tag;
|
||||
fdt32_t tag;
|
||||
char name[0];
|
||||
};
|
||||
|
||||
struct fdt_property {
|
||||
uint32_t tag;
|
||||
uint32_t len;
|
||||
uint32_t nameoff;
|
||||
fdt32_t tag;
|
||||
fdt32_t len;
|
||||
fdt32_t nameoff;
|
||||
char data[0];
|
||||
};
|
||||
|
||||
#endif /* !__ASSEMBLY */
|
||||
|
||||
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
|
||||
#define FDT_TAGSIZE sizeof(uint32_t)
|
||||
#define FDT_TAGSIZE sizeof(fdt32_t)
|
||||
|
||||
#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
|
||||
#define FDT_END_NODE 0x2 /* End node */
|
||||
@@ -51,11 +51,11 @@ struct fdt_property {
|
||||
#define FDT_NOP 0x4 /* nop */
|
||||
#define FDT_END 0x9
|
||||
|
||||
#define FDT_V1_SIZE (7*sizeof(uint32_t))
|
||||
#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t))
|
||||
#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t))
|
||||
#define FDT_V1_SIZE (7*sizeof(fdt32_t))
|
||||
#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t))
|
||||
#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t))
|
||||
#define FDT_V16_SIZE FDT_V3_SIZE
|
||||
#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t))
|
||||
#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t))
|
||||
|
||||
/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
|
||||
#define FDT_RAMDISK_OVERHEAD 0x80
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
|
||||
#include <fdt.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
|
||||
const char *prop, const u32 dflt);
|
||||
@@ -92,7 +92,7 @@ int fdt_fixup_nor_flash_size(void *blob);
|
||||
|
||||
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
|
||||
void fdt_del_node_and_alias(void *blob, const char *alias);
|
||||
u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
|
||||
u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr);
|
||||
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
|
||||
phys_addr_t compat_off);
|
||||
int fdt_alloc_phandle(void *blob);
|
||||
|
||||
@@ -70,6 +70,8 @@ enum fdt_compat_id {
|
||||
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
|
||||
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
|
||||
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
|
||||
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
|
||||
COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */
|
||||
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
|
||||
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
|
||||
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
|
||||
|
||||
@@ -52,7 +52,6 @@
|
||||
#endif /* USE_HOSTCC */
|
||||
|
||||
#if defined(CONFIG_FIT)
|
||||
#include <fdt.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#define CONFIG_MD5 /* FIT images need MD5 support */
|
||||
|
||||
@@ -882,8 +882,8 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
|
||||
static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
|
||||
const char *name, uint32_t val)
|
||||
{
|
||||
val = cpu_to_fdt32(val);
|
||||
return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
|
||||
fdt32_t tmp = cpu_to_fdt32(val);
|
||||
return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -917,8 +917,8 @@ static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
|
||||
static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
|
||||
const char *name, uint64_t val)
|
||||
{
|
||||
val = cpu_to_fdt64(val);
|
||||
return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
|
||||
fdt64_t tmp = cpu_to_fdt64(val);
|
||||
return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -993,13 +993,13 @@ int fdt_begin_node(void *fdt, const char *name);
|
||||
int fdt_property(void *fdt, const char *name, const void *val, int len);
|
||||
static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
|
||||
{
|
||||
val = cpu_to_fdt32(val);
|
||||
return fdt_property(fdt, name, &val, sizeof(val));
|
||||
fdt32_t tmp = cpu_to_fdt32(val);
|
||||
return fdt_property(fdt, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
|
||||
{
|
||||
val = cpu_to_fdt64(val);
|
||||
return fdt_property(fdt, name, &val, sizeof(val));
|
||||
fdt64_t tmp = cpu_to_fdt64(val);
|
||||
return fdt_property(fdt, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
|
||||
{
|
||||
@@ -1154,8 +1154,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
|
||||
static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
|
||||
uint32_t val)
|
||||
{
|
||||
val = cpu_to_fdt32(val);
|
||||
return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
|
||||
fdt32_t tmp = cpu_to_fdt32(val);
|
||||
return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1189,8 +1189,8 @@ static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
|
||||
static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
|
||||
uint64_t val)
|
||||
{
|
||||
val = cpu_to_fdt64(val);
|
||||
return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
|
||||
fdt64_t tmp = cpu_to_fdt64(val);
|
||||
return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1296,8 +1296,8 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
|
||||
static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
|
||||
const char *name, uint32_t val)
|
||||
{
|
||||
val = cpu_to_fdt32(val);
|
||||
return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
|
||||
fdt32_t tmp = cpu_to_fdt32(val);
|
||||
return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1331,8 +1331,8 @@ static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
|
||||
static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
|
||||
const char *name, uint64_t val)
|
||||
{
|
||||
val = cpu_to_fdt64(val);
|
||||
return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
|
||||
fdt64_t tmp = cpu_to_fdt64(val);
|
||||
return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -22,9 +22,14 @@
|
||||
#define _LIBFDT_ENV_H
|
||||
|
||||
#include "compiler.h"
|
||||
#include "linux/types.h"
|
||||
|
||||
extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
|
||||
|
||||
typedef __be16 fdt16_t;
|
||||
typedef __be32 fdt32_t;
|
||||
typedef __be64 fdt64_t;
|
||||
|
||||
#define fdt32_to_cpu(x) be32_to_cpu(x)
|
||||
#define cpu_to_fdt32(x) cpu_to_be32(x)
|
||||
#define fdt64_to_cpu(x) be64_to_cpu(x)
|
||||
|
||||
@@ -32,7 +32,7 @@ extern struct serial_device *default_serial_console(void);
|
||||
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
|
||||
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
|
||||
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
|
||||
defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
|
||||
defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
|
||||
defined(CONFIG_MICROBLAZE)
|
||||
extern struct serial_device serial0_device;
|
||||
extern struct serial_device serial1_device;
|
||||
|
||||
@@ -99,7 +99,7 @@ struct list_head* stdio_get_list(void);
|
||||
struct stdio_dev* stdio_get_by_name(const char* name);
|
||||
struct stdio_dev* stdio_clone(struct stdio_dev *dev);
|
||||
|
||||
#ifdef CONFIG_ARM_DCC_MULTI
|
||||
#ifdef CONFIG_ARM_DCC
|
||||
int drv_arm_dcc_init(void);
|
||||
#endif
|
||||
#ifdef CONFIG_LCD
|
||||
|
||||
Reference in New Issue
Block a user