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arm: nuvoton: Add support for Nuvoton NPCM845 BMC

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Add basic support for the Nuvoton NPCM845 EVB (Arbel).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
2022-09-27 16:45:15 +08:00
committed by Tom Rini
parent d0fc818259
commit 9ca71c9c19
21 changed files with 1112 additions and 0 deletions
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35
include/configs/arbel.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
#ifndef __CONFIG_ARBEL_H
#define __CONFIG_ARBEL_H
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"ethact=gmac1\0" \
"autostart=no\0" \
"ethaddr=00:00:F7:A0:00:FC\0" \
"eth1addr=00:00:F7:A0:00:FD\0" \
"eth2addr=00:00:F7:A0:00:FE\0" \
"eth3addr=00:00:F7:A0:00:FF\0" \
"serverip=192.168.0.1\0" \
"ipaddr=192.168.0.2\0" \
"romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
"echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
"earlycon=uart8250,mmio32,0xf0000000\0" \
"console=ttyS0,115200n8\0" \
"common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
"console=${console} ramdisk_size=48000\0" \
"\0"
#endif

52
include/dt-bindings/clock/nuvoton,npcm845-clk.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022 Nuvoton Technology Corp.
*
* Device Tree binding constants for NPCM8XX clock controller.
*/
#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
#define __DT_BINDINGS_CLOCK_NPCM8XX_H
#define NPCM8XX_CLK_CPU 0
#define NPCM8XX_CLK_GFX_PIXEL 1
#define NPCM8XX_CLK_MC 2
#define NPCM8XX_CLK_ADC 3
#define NPCM8XX_CLK_AHB 4
#define NPCM8XX_CLK_TIMER 5
#define NPCM8XX_CLK_UART 6
#define NPCM8XX_CLK_UART2 7
#define NPCM8XX_CLK_MMC 8
#define NPCM8XX_CLK_SPI3 9
#define NPCM8XX_CLK_PCI 10
#define NPCM8XX_CLK_AXI 11
#define NPCM8XX_CLK_APB4 12
#define NPCM8XX_CLK_APB3 13
#define NPCM8XX_CLK_APB2 14
#define NPCM8XX_CLK_APB1 15
#define NPCM8XX_CLK_APB5 16
#define NPCM8XX_CLK_CLKOUT 17
#define NPCM8XX_CLK_GFX 18
#define NPCM8XX_CLK_SU 19
#define NPCM8XX_CLK_SU48 20
#define NPCM8XX_CLK_SDHC 21
#define NPCM8XX_CLK_SPI0 22
#define NPCM8XX_CLK_SPI1 23
#define NPCM8XX_CLK_SPIX 24
#define NPCM8XX_CLK_RG 25
#define NPCM8XX_CLK_RCP 26
#define NPCM8XX_CLK_PRE_ADC 27
#define NPCM8XX_CLK_ATB 28
#define NPCM8XX_CLK_PRE_CLK 29
#define NPCM8XX_CLK_TH 30
#define NPCM8XX_CLK_REFCLK 31
#define NPCM8XX_CLK_SYSBYPCK 32
#define NPCM8XX_CLK_MCBYPCK 33
#define NPCM8XX_CLK_PLL0 34
#define NPCM8XX_CLK_PLL1 35
#define NPCM8XX_CLK_PLL2 36
#define NPCM8XX_CLK_PLL2DIV2 37
#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_PLL2DIV2 + 1)
#endif

124
include/dt-bindings/reset/nuvoton,npcm8xx-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
// Copyright (c) 2020 Nuvoton Technology corporation.
#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
#define _DT_BINDINGS_NPCM8XX_RESET_H
#define NPCM8XX_RESET_IPSRST1 0x20
#define NPCM8XX_RESET_IPSRST2 0x24
#define NPCM8XX_RESET_IPSRST3 0x34
#define NPCM8XX_RESET_IPSRST4 0x74
/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
#define NPCM8XX_RESET_GDMA0 3
#define NPCM8XX_RESET_UDC1 5
#define NPCM8XX_RESET_GMAC3 6
#define NPCM8XX_RESET_UART_2_3 7
#define NPCM8XX_RESET_UDC2 8
#define NPCM8XX_RESET_PECI 9
#define NPCM8XX_RESET_AES 10
#define NPCM8XX_RESET_UART_0_1 11
#define NPCM8XX_RESET_MC 12
#define NPCM8XX_RESET_SMB2 13
#define NPCM8XX_RESET_SMB3 14
#define NPCM8XX_RESET_SMB4 15
#define NPCM8XX_RESET_SMB5 16
#define NPCM8XX_RESET_PWM_M0 18
#define NPCM8XX_RESET_TIMER_0_4 19
#define NPCM8XX_RESET_TIMER_5_9 20
#define NPCM8XX_RESET_GMAC4 21
#define NPCM8XX_RESET_UDC4 22
#define NPCM8XX_RESET_UDC5 23
#define NPCM8XX_RESET_UDC6 24
#define NPCM8XX_RESET_UDC3 25
#define NPCM8XX_RESET_ADC 27
#define NPCM8XX_RESET_SMB6 28
#define NPCM8XX_RESET_SMB7 29
#define NPCM8XX_RESET_SMB0 30
#define NPCM8XX_RESET_SMB1 31
/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
#define NPCM8XX_RESET_MFT0 0
#define NPCM8XX_RESET_MFT1 1
#define NPCM8XX_RESET_MFT2 2
#define NPCM8XX_RESET_MFT3 3
#define NPCM8XX_RESET_MFT4 4
#define NPCM8XX_RESET_MFT5 5
#define NPCM8XX_RESET_MFT6 6
#define NPCM8XX_RESET_MFT7 7
#define NPCM8XX_RESET_MMC 8
#define NPCM8XX_RESET_GFX_SYS 10
#define NPCM8XX_RESET_AHB_PCIBRG 11
#define NPCM8XX_RESET_VDMA 12
#define NPCM8XX_RESET_ECE 13
#define NPCM8XX_RESET_VCD 14
#define NPCM8XX_RESET_VIRUART1 16
#define NPCM8XX_RESET_VIRUART2 17
#define NPCM8XX_RESET_SIOX1 18
#define NPCM8XX_RESET_SIOX2 19
#define NPCM8XX_RESET_BT 20
#define NPCM8XX_RESET_3DES 21
#define NPCM8XX_RESET_PSPI2 23
#define NPCM8XX_RESET_GMAC2 25
#define NPCM8XX_RESET_USBH1 26
#define NPCM8XX_RESET_GMAC1 28
#define NPCM8XX_RESET_CP1 31
/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
#define NPCM8XX_RESET_PWM_M1 0
#define NPCM8XX_RESET_SMB12 1
#define NPCM8XX_RESET_SPIX 2
#define NPCM8XX_RESET_SMB13 3
#define NPCM8XX_RESET_UDC0 4
#define NPCM8XX_RESET_UDC7 5
#define NPCM8XX_RESET_UDC8 6
#define NPCM8XX_RESET_UDC9 7
#define NPCM8XX_RESET_USBHUB 8
#define NPCM8XX_RESET_PCI_MAILBOX 9
#define NPCM8XX_RESET_GDMA1 10
#define NPCM8XX_RESET_GDMA2 11
#define NPCM8XX_RESET_SMB14 12
#define NPCM8XX_RESET_SHA 13
#define NPCM8XX_RESET_SEC_ECC 14
#define NPCM8XX_RESET_PCIE_RC 15
#define NPCM8XX_RESET_TIMER_10_14 16
#define NPCM8XX_RESET_RNG 17
#define NPCM8XX_RESET_SMB15 18
#define NPCM8XX_RESET_SMB8 19
#define NPCM8XX_RESET_SMB9 20
#define NPCM8XX_RESET_SMB10 21
#define NPCM8XX_RESET_SMB11 22
#define NPCM8XX_RESET_ESPI 23
#define NPCM8XX_RESET_USBPHY1 24
#define NPCM8XX_RESET_USBPHY2 25
/* Reset lines on IP4 reset module (NPCM8XX_RESET_IPSRST4) */
#define NPCM8XX_RESET_SMB16 0
#define NPCM8XX_RESET_SMB17 1
#define NPCM8XX_RESET_SMB18 2
#define NPCM8XX_RESET_SMB19 3
#define NPCM8XX_RESET_SMB20 4
#define NPCM8XX_RESET_SMB21 5
#define NPCM8XX_RESET_SMB22 6
#define NPCM8XX_RESET_SMB23 7
#define NPCM8XX_RESET_I3C0 8
#define NPCM8XX_RESET_I3C1 9
#define NPCM8XX_RESET_I3C2 10
#define NPCM8XX_RESET_I3C3 11
#define NPCM8XX_RESET_I3C4 12
#define NPCM8XX_RESET_I3C5 13
#define NPCM8XX_RESET_UART4 16
#define NPCM8XX_RESET_UART5 17
#define NPCM8XX_RESET_UART6 18
#define NPCM8XX_RESET_PCIMBX2 19
#define NPCM8XX_RESET_SMB24 22
#define NPCM8XX_RESET_SMB25 23
#define NPCM8XX_RESET_SMB26 24
#define NPCM8XX_RESET_USBPHY3 25
#define NPCM8XX_RESET_PCIRCPHY 27
#define NPCM8XX_RESET_PWM_M2 28
#define NPCM8XX_RESET_JTM1 29
#define NPCM8XX_RESET_JTM2 30
#define NPCM8XX_RESET_USBH2 31
#endif