arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
140
arch/arm/include/asm/arch-npcm8xx/gcr.h
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140
arch/arm/include/asm/arch-npcm8xx/gcr.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* System Global Control Register definitions
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#ifndef _NPCM_GCR_H_
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#define _NPCM_GCR_H_
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#define NPCM_GCR_BA 0xF0800000
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/* On-Chip ARBEL NPCM8XX VERSIONS */
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#define ARBEL_Z1 0x00A35850
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#define ARBEL_A1 0x04a35850
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#define ARBEL_NPCM845 0x00000000
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#define ARBEL_NPCM830 0x00300395
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#define ARBEL_NPCM810 0x00000220
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#define MFSEL4_ESPISEL BIT(8)
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#define MFSEL1_LPCSEL BIT(26)
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#define INTCR2_WDC BIT(21)
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struct npcm_gcr {
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unsigned int pdid;
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unsigned int pwron;
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unsigned int swstrps;
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unsigned int rsvd1[2];
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unsigned int miscpe;
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unsigned int spldcnt;
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unsigned int rsvd2[1];
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unsigned int flockr2;
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unsigned int flockr3;
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unsigned int rsvd3[3];
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unsigned int a35_mode;
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unsigned int spswc;
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unsigned int intcr;
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unsigned int intsr;
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unsigned int obscr1;
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unsigned int obsdr1;
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unsigned int rsvd4[1];
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unsigned int hifcr;
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unsigned int rsvd5[3];
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unsigned int intcr2;
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unsigned int rsvd6[1];
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unsigned int srcnt;
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unsigned int ressr;
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unsigned int rlockr1;
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unsigned int flockr1;
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unsigned int dscnt;
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unsigned int mdlr;
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unsigned int scrpad_c;
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unsigned int scrpad_b;
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unsigned int rsvd7[4];
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unsigned int daclvlr;
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unsigned int intcr3;
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unsigned int pcirctl;
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unsigned int rsvd8[2];
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unsigned int vsintr;
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unsigned int rsvd9[1];
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unsigned int sd2sur1;
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unsigned int sd2sur2;
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unsigned int sd2irv3;
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unsigned int intcr4;
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unsigned int obscr2;
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unsigned int obsdr2;
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unsigned int rsvd10[5];
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unsigned int i2csegsel;
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unsigned int i2csegctl;
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unsigned int vsrcr;
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unsigned int mlockr;
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unsigned int rsvd11[8];
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unsigned int etsr;
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unsigned int dft1r;
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unsigned int dft2r;
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unsigned int dft3r;
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unsigned int edffsr;
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unsigned int rsvd12[1];
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unsigned int intcrpce3;
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unsigned int intcrpce2;
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unsigned int intcrpce0;
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unsigned int intcrpce1;
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unsigned int dactest;
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unsigned int scrpad;
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unsigned int usb1phyctl;
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unsigned int usb2phyctl;
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unsigned int usb3phyctl;
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unsigned int intsr2;
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unsigned int intcrpce2b;
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unsigned int intcrpce0b;
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unsigned int intcrpce1b;
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unsigned int intcrpce3b;
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unsigned int rsvd13[4];
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unsigned int intcrpce2c;
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unsigned int intcrpce0c;
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unsigned int intcrpce1c;
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unsigned int intcrpce3c;
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unsigned int rsvd14[40];
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unsigned int sd2irv4;
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unsigned int sd2irv5;
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unsigned int sd2irv6;
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unsigned int sd2irv7;
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unsigned int sd2irv8;
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unsigned int sd2irv9;
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unsigned int sd2irv10;
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unsigned int sd2irv11;
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unsigned int rsvd15[8];
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unsigned int mfsel1;
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unsigned int mfsel2;
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unsigned int mfsel3;
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unsigned int mfsel4;
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unsigned int mfsel5;
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unsigned int mfsel6;
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unsigned int mfsel7;
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unsigned int rsvd16[1];
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unsigned int mfsel_lk1;
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unsigned int mfsel_lk2;
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unsigned int mfsel_lk3;
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unsigned int mfsel_lk4;
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unsigned int mfsel_lk5;
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unsigned int mfsel_lk6;
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unsigned int mfsel_lk7;
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unsigned int rsvd17[1];
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unsigned int mfsel_set1;
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unsigned int mfsel_set2;
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unsigned int mfsel_set3;
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unsigned int mfsel_set4;
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unsigned int mfsel_set5;
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unsigned int mfsel_set6;
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unsigned int mfsel_set7;
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unsigned int rsvd18[1];
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unsigned int mfsel_clr1;
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unsigned int mfsel_clr2;
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unsigned int mfsel_clr3;
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unsigned int mfsel_clr4;
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unsigned int mfsel_clr5;
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unsigned int mfsel_clr6;
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unsigned int mfsel_clr7;
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};
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#endif
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26
arch/arm/include/asm/arch-npcm8xx/rst.h
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26
arch/arm/include/asm/arch-npcm8xx/rst.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_RST_H_
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#define _NPCM_RST_H_
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/* Watchdog Timer Controller Register */
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#define WTCR0_REG 0xF000801C
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#define WTCR_WTR BIT(0)
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#define WTCR_WTRE BIT(1)
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#define WTCR_WTE BIT(7)
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/* Reset status bits */
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#define PORST BIT(31)
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#define CORST BIT(30)
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#define WD0RST BIT(29)
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#define SW1RST BIT(28)
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#define SW2RST BIT(27)
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#define SW3RST BIT(26)
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#define SW4RST BIT(25)
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#define WD1RST BIT(24)
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#define WD2RST BIT(23)
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#define RST_STS_MASK GENMASK(31, 23)
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int npcm_get_reset_status(void);
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#endif
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