arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
This commit is contained in:
Jim Liu
Tom Rini
@@ -1252,6 +1252,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt8518-ap1-emmc.dtb
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dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
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dtb-$(CONFIG_ARCH_NPCM8XX) += nuvoton-npcm845-evb.dtb
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dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
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dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
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170
arch/arm/dts/nuvoton-common-npcm8xx.dtsi
Normal file
170
arch/arm/dts/nuvoton-common-npcm8xx.dtsi
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@@ -0,0 +1,170 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
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#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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gcr: system-controller@f0800000 {
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compatible = "nuvoton,npcm845-gcr", "syscon";
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reg = <0x0 0xf0800000 0x0 0x1000>;
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};
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gic: interrupt-controller@dfff9000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xdfff9000 0x0 0x1000>,
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<0x0 0xdfffa000 0x0 0x2000>,
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<0x0 0xdfffc000 0x0 0x2000>,
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<0x0 0xdfffe000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
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};
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};
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};
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};
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ahb {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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rstc: reset-controller@f0801000 {
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compatible = "nuvoton,npcm845-reset";
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reg = <0x0 0xf0801000 0x0 0x78>;
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#reset-cells = <2>;
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nuvoton,sysgcr = <&gcr>;
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};
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm845-clk";
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#clock-cells = <1>;
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reg = <0x0 0xf0801000 0x0 0x1000>;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf0000000 0x00300000>,
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<0xfff00000 0x0 0xfff00000 0x00016000>;
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timer0: timer@8000 {
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compatible = "nuvoton,npcm845-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x8000 0x1C>;
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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clock-names = "refclk";
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};
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serial0: serial@0 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x0 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial1: serial@1000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x1000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial2: serial@2000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x2000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial3: serial@3000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x3000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial4: serial@4000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x4000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial5: serial@5000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x5000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial6: serial@6000 {
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compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
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reg = <0x6000 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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watchdog0: watchdog@801c {
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compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x801c 0x4>;
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status = "disabled";
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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syscon = <&gcr>;
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};
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watchdog1: watchdog@901c {
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compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x901c 0x4>;
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status = "disabled";
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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syscon = <&gcr>;
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};
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watchdog2: watchdog@a01c {
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compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xa01c 0x4>;
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status = "disabled";
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clocks = <&clk NPCM8XX_CLK_REFCLK>;
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syscon = <&gcr>;
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};
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};
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};
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};
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30
arch/arm/dts/nuvoton-npcm845-evb.dts
Normal file
30
arch/arm/dts/nuvoton-npcm845-evb.dts
Normal file
@@ -0,0 +1,30 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
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/dts-v1/;
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#include "nuvoton-npcm845.dtsi"
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/ {
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model = "Nuvoton npcm845 Development Board (Device Tree)";
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compatible = "nuvoton,npcm845-evb", "nuvoton,npcm845";
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aliases {
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serial0 = &serial0;
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};
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chosen {
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stdout-path = &serial0;
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};
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memory {
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reg = <0x0 0x0 0x0 0x40000000>;
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};
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};
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&serial0 {
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status = "okay";
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};
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&watchdog1 {
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status = "okay";
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};
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77
arch/arm/dts/nuvoton-npcm845.dtsi
Normal file
77
arch/arm/dts/nuvoton-npcm845.dtsi
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@@ -0,0 +1,77 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
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#include "nuvoton-common-npcm8xx.dtsi"
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#include "nuvoton-npcm8xx-u-boot.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x0>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x1>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x2>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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clocks = <&clk NPCM8XX_CLK_CPU>;
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reg = <0x0 0x3>;
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next-level-cache = <&l2>;
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enable-method = "psci";
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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136
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
Normal file
136
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
Normal file
@@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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/* external reference clock */
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clk_refclk: clk-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "refclk";
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};
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ahb {
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rstc: reset-controller@f0801000 {
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compatible = "nuvoton,npcm845-reset", "syscon",
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"simple-mfd";
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reg = <0x0 0xf0801000 0x0 0xC4>;
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rstc1: reset-controller1 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST1>;
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mask = <0xFFFFFFFF>;
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};
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rstc2: reset-controller2 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST2>;
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mask = <0xFFFFFFFF>;
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};
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rstc3: reset-controller3 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST3>;
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mask = <0xFFFFFFFF>;
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};
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rstc4: reset-controller4 {
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compatible = "syscon-reset";
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#reset-cells = <1>;
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regmap = <&rstc>;
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offset = <NPCM8XX_RESET_IPSRST4>;
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mask = <0xFFFFFFFF>;
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};
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};
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm845-clk", "syscon";
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#clock-cells = <1>;
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clock-controller;
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reg = <0x0 0xf0801000 0x0 0x1000>;
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clock-names = "refclk";
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clocks = <&clk_refclk>;
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};
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apb {
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serial0: serial@0 {
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compatible = "nuvoton,npcm845-uart";
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reg = <0x0 0x1000>;
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clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
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clock-frequency = <24000000>;
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status = "disabled";
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};
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gpio0: gpio0@10000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x10000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio0";
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};
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gpio1: gpio1@11000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x11000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio1";
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};
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gpio2: gpio2@12000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x12000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio2";
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};
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gpio3: gpio3@13000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x13000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio3";
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};
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gpio4: gpio4@14000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x14000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio4";
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};
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gpio5: gpio5@15000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x15000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio5";
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};
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gpio6: gpio6@16000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x16000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio6";
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};
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gpio7: gpio7@17000 {
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compatible = "nuvoton,npcm-gpio";
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reg = <0x17000 0xB0>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "gpio7";
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};
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};
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};
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};
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140
arch/arm/include/asm/arch-npcm8xx/gcr.h
Normal file
140
arch/arm/include/asm/arch-npcm8xx/gcr.h
Normal file
@@ -0,0 +1,140 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* System Global Control Register definitions
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#ifndef _NPCM_GCR_H_
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#define _NPCM_GCR_H_
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#define NPCM_GCR_BA 0xF0800000
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/* On-Chip ARBEL NPCM8XX VERSIONS */
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#define ARBEL_Z1 0x00A35850
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#define ARBEL_A1 0x04a35850
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#define ARBEL_NPCM845 0x00000000
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#define ARBEL_NPCM830 0x00300395
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#define ARBEL_NPCM810 0x00000220
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#define MFSEL4_ESPISEL BIT(8)
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#define MFSEL1_LPCSEL BIT(26)
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#define INTCR2_WDC BIT(21)
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||||
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struct npcm_gcr {
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||||
unsigned int pdid;
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||||
unsigned int pwron;
|
||||
unsigned int swstrps;
|
||||
unsigned int rsvd1[2];
|
||||
unsigned int miscpe;
|
||||
unsigned int spldcnt;
|
||||
unsigned int rsvd2[1];
|
||||
unsigned int flockr2;
|
||||
unsigned int flockr3;
|
||||
unsigned int rsvd3[3];
|
||||
unsigned int a35_mode;
|
||||
unsigned int spswc;
|
||||
unsigned int intcr;
|
||||
unsigned int intsr;
|
||||
unsigned int obscr1;
|
||||
unsigned int obsdr1;
|
||||
unsigned int rsvd4[1];
|
||||
unsigned int hifcr;
|
||||
unsigned int rsvd5[3];
|
||||
unsigned int intcr2;
|
||||
unsigned int rsvd6[1];
|
||||
unsigned int srcnt;
|
||||
unsigned int ressr;
|
||||
unsigned int rlockr1;
|
||||
unsigned int flockr1;
|
||||
unsigned int dscnt;
|
||||
unsigned int mdlr;
|
||||
unsigned int scrpad_c;
|
||||
unsigned int scrpad_b;
|
||||
unsigned int rsvd7[4];
|
||||
unsigned int daclvlr;
|
||||
unsigned int intcr3;
|
||||
unsigned int pcirctl;
|
||||
unsigned int rsvd8[2];
|
||||
unsigned int vsintr;
|
||||
unsigned int rsvd9[1];
|
||||
unsigned int sd2sur1;
|
||||
unsigned int sd2sur2;
|
||||
unsigned int sd2irv3;
|
||||
unsigned int intcr4;
|
||||
unsigned int obscr2;
|
||||
unsigned int obsdr2;
|
||||
unsigned int rsvd10[5];
|
||||
unsigned int i2csegsel;
|
||||
unsigned int i2csegctl;
|
||||
unsigned int vsrcr;
|
||||
unsigned int mlockr;
|
||||
unsigned int rsvd11[8];
|
||||
unsigned int etsr;
|
||||
unsigned int dft1r;
|
||||
unsigned int dft2r;
|
||||
unsigned int dft3r;
|
||||
unsigned int edffsr;
|
||||
unsigned int rsvd12[1];
|
||||
unsigned int intcrpce3;
|
||||
unsigned int intcrpce2;
|
||||
unsigned int intcrpce0;
|
||||
unsigned int intcrpce1;
|
||||
unsigned int dactest;
|
||||
unsigned int scrpad;
|
||||
unsigned int usb1phyctl;
|
||||
unsigned int usb2phyctl;
|
||||
unsigned int usb3phyctl;
|
||||
unsigned int intsr2;
|
||||
unsigned int intcrpce2b;
|
||||
unsigned int intcrpce0b;
|
||||
unsigned int intcrpce1b;
|
||||
unsigned int intcrpce3b;
|
||||
unsigned int rsvd13[4];
|
||||
unsigned int intcrpce2c;
|
||||
unsigned int intcrpce0c;
|
||||
unsigned int intcrpce1c;
|
||||
unsigned int intcrpce3c;
|
||||
unsigned int rsvd14[40];
|
||||
unsigned int sd2irv4;
|
||||
unsigned int sd2irv5;
|
||||
unsigned int sd2irv6;
|
||||
unsigned int sd2irv7;
|
||||
unsigned int sd2irv8;
|
||||
unsigned int sd2irv9;
|
||||
unsigned int sd2irv10;
|
||||
unsigned int sd2irv11;
|
||||
unsigned int rsvd15[8];
|
||||
unsigned int mfsel1;
|
||||
unsigned int mfsel2;
|
||||
unsigned int mfsel3;
|
||||
unsigned int mfsel4;
|
||||
unsigned int mfsel5;
|
||||
unsigned int mfsel6;
|
||||
unsigned int mfsel7;
|
||||
unsigned int rsvd16[1];
|
||||
unsigned int mfsel_lk1;
|
||||
unsigned int mfsel_lk2;
|
||||
unsigned int mfsel_lk3;
|
||||
unsigned int mfsel_lk4;
|
||||
unsigned int mfsel_lk5;
|
||||
unsigned int mfsel_lk6;
|
||||
unsigned int mfsel_lk7;
|
||||
unsigned int rsvd17[1];
|
||||
unsigned int mfsel_set1;
|
||||
unsigned int mfsel_set2;
|
||||
unsigned int mfsel_set3;
|
||||
unsigned int mfsel_set4;
|
||||
unsigned int mfsel_set5;
|
||||
unsigned int mfsel_set6;
|
||||
unsigned int mfsel_set7;
|
||||
unsigned int rsvd18[1];
|
||||
unsigned int mfsel_clr1;
|
||||
unsigned int mfsel_clr2;
|
||||
unsigned int mfsel_clr3;
|
||||
unsigned int mfsel_clr4;
|
||||
unsigned int mfsel_clr5;
|
||||
unsigned int mfsel_clr6;
|
||||
unsigned int mfsel_clr7;
|
||||
};
|
||||
|
||||
#endif
|
||||
26
arch/arm/include/asm/arch-npcm8xx/rst.h
Normal file
26
arch/arm/include/asm/arch-npcm8xx/rst.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef _NPCM_RST_H_
|
||||
#define _NPCM_RST_H_
|
||||
|
||||
/* Watchdog Timer Controller Register */
|
||||
#define WTCR0_REG 0xF000801C
|
||||
#define WTCR_WTR BIT(0)
|
||||
#define WTCR_WTRE BIT(1)
|
||||
#define WTCR_WTE BIT(7)
|
||||
|
||||
/* Reset status bits */
|
||||
#define PORST BIT(31)
|
||||
#define CORST BIT(30)
|
||||
#define WD0RST BIT(29)
|
||||
#define SW1RST BIT(28)
|
||||
#define SW2RST BIT(27)
|
||||
#define SW3RST BIT(26)
|
||||
#define SW4RST BIT(25)
|
||||
#define WD1RST BIT(24)
|
||||
#define WD2RST BIT(23)
|
||||
#define RST_STS_MASK GENMASK(31, 23)
|
||||
|
||||
int npcm_get_reset_status(void);
|
||||
|
||||
#endif
|
||||
@@ -19,8 +19,16 @@ config ARCH_NPCM7xx
|
||||
General support for NPCM7xx BMC (Poleg).
|
||||
Nuvoton NPCM7xx BMC is based on the Cortex A9.
|
||||
|
||||
config ARCH_NPCM8XX
|
||||
bool "Support Nuvoton NPCM8xx SoC"
|
||||
select ARM64
|
||||
help
|
||||
General support for NPCM8xx BMC (Arbel).
|
||||
Nuvoton NPCM8xx BMC is based on the Cortex A35.
|
||||
|
||||
endchoice
|
||||
|
||||
source "arch/arm/mach-npcm/npcm7xx/Kconfig"
|
||||
source "arch/arm/mach-npcm/npcm8xx/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
@@ -1 +1,2 @@
|
||||
obj-$(CONFIG_ARCH_NPCM7xx) += npcm7xx/
|
||||
obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
|
||||
|
||||
18
arch/arm/mach-npcm/npcm8xx/Kconfig
Normal file
18
arch/arm/mach-npcm/npcm8xx/Kconfig
Normal file
@@ -0,0 +1,18 @@
|
||||
if ARCH_NPCM8XX
|
||||
|
||||
config SYS_CPU
|
||||
default "armv8"
|
||||
|
||||
config SYS_SOC
|
||||
default "npcm8xx"
|
||||
|
||||
config TARGET_ARBEL_EVB
|
||||
bool "Arbel Evaluation Board"
|
||||
help
|
||||
ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
|
||||
supports general functions of Basebase Management Controller
|
||||
(BMC).
|
||||
|
||||
source "board/nuvoton/arbel_evb/Kconfig"
|
||||
|
||||
endif
|
||||
1
arch/arm/mach-npcm/npcm8xx/Makefile
Normal file
1
arch/arm/mach-npcm/npcm8xx/Makefile
Normal file
@@ -0,0 +1 @@
|
||||
obj-y += cpu.o reset.o
|
||||
135
arch/arm/mach-npcm/npcm8xx/cpu.c
Normal file
135
arch/arm/mach-npcm/npcm8xx/cpu.c
Normal file
@@ -0,0 +1,135 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2022 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/arch/gcr.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
|
||||
#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
|
||||
#define SC_CNTCR_ENABLE BIT(0)
|
||||
#define SC_CNTCR_HDBG BIT(1)
|
||||
#define SC_CNTCR_FREQ0 BIT(8)
|
||||
#define SC_CNTCR_FREQ1 BIT(9)
|
||||
|
||||
/* System Counter register map */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 cntfid2;
|
||||
u32 resv2[1001];
|
||||
u32 counterid[1];
|
||||
};
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
|
||||
unsigned int val;
|
||||
unsigned long mpidr_val;
|
||||
|
||||
asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
|
||||
|
||||
val = readl(&gcr->mdlr);
|
||||
|
||||
printf("CPU-%lu: ", mpidr_val & 0x3);
|
||||
|
||||
switch (val) {
|
||||
case ARBEL_NPCM845:
|
||||
printf("NPCM845 ");
|
||||
break;
|
||||
case ARBEL_NPCM830:
|
||||
printf("NPCM830 ");
|
||||
break;
|
||||
case ARBEL_NPCM810:
|
||||
printf("NPCM810 ");
|
||||
break;
|
||||
default:
|
||||
printf("NPCM8XX ");
|
||||
break;
|
||||
}
|
||||
|
||||
val = readl(&gcr->pdid);
|
||||
switch (val) {
|
||||
case ARBEL_Z1:
|
||||
printf("Z1 @ ");
|
||||
break;
|
||||
case ARBEL_A1:
|
||||
printf("A1 @ ");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
|
||||
/* Enable cache to speed up system running */
|
||||
if (get_sctlr() & CR_M)
|
||||
return 0;
|
||||
|
||||
icache_enable();
|
||||
__asm_invalidate_dcache_all();
|
||||
__asm_invalidate_tlb_all();
|
||||
set_sctlr(get_sctlr() | CR_C);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
|
||||
{
|
||||
/* DRAM */
|
||||
.phys = 0x0UL,
|
||||
.virt = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
},
|
||||
{
|
||||
.phys = 0x80000000UL,
|
||||
.virt = 0x80000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = npcm_mem_map;
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
|
||||
u32 cntfrq_el0;
|
||||
|
||||
/* Enable system counter */
|
||||
__asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
|
||||
writel(cntfrq_el0, &sctr->cntfid0);
|
||||
clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
|
||||
SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
|
||||
|
||||
gd->arch.tbl = 0;
|
||||
gd->arch.tbu = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
37
arch/arm/mach-npcm/npcm8xx/reset.c
Normal file
37
arch/arm/mach-npcm/npcm8xx/reset.c
Normal file
@@ -0,0 +1,37 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2022 Nuvoton Technology Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gcr.h>
|
||||
#include <asm/arch/rst.h>
|
||||
|
||||
void reset_cpu(void)
|
||||
{
|
||||
/* Generate a watchdog0 reset */
|
||||
writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG);
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void reset_misc(void)
|
||||
{
|
||||
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
|
||||
|
||||
clrbits_le32(&gcr->intcr2, INTCR2_WDC);
|
||||
}
|
||||
|
||||
int npcm_get_reset_status(void)
|
||||
{
|
||||
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
|
||||
u32 val;
|
||||
|
||||
val = readl(&gcr->ressr);
|
||||
if (!val)
|
||||
val = readl(&gcr->intcr2);
|
||||
|
||||
return val & RST_STS_MASK;
|
||||
}
|
||||
Reference in New Issue
Block a user