Merge tag 'u-boot-atmel-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2021.04 cycle This feature set includes the new board SAMA7G5 EK, the new evaluation kit for Microchip AT91 SAMA7G5 SoC . The current board support includes two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and support for two Ethernet interfaces.
This commit is contained in:
Tom Rini
@@ -890,6 +890,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
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dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
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omap5-uevm.dtb
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dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
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sama7g5ek.dtb
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dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
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at91-sama5d2_ptc_ek.dtb
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170
arch/arm/dts/sama7g5.dtsi
Normal file
170
arch/arm/dts/sama7g5.dtsi
Normal file
@@ -0,0 +1,170 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clk/at91.h>
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/ {
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model = "Microchip SAMA7G5 family SoC";
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compatible = "microchip,sama7g5";
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clocks {
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slow_rc_osc: slow_rc_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A7_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
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clock-names = "cpu", "master", "xtal";
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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pioA: pinctrl@e0014000 {
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compatible = "atmel,sama5d2-gpio";
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reg = <0xe0014000 0x800>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
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status = "okay";
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pinctrl: pinctrl_default {
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compatible = "microchip,sama7g5-pinctrl";
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};
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};
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pmc: pmc@e0018000 {
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compatible = "microchip,sama7g5-pmc";
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reg = <0xe0018000 0x200>;
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#clock-cells = <2>;
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clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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status = "okay";
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};
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clk32: sckc@e001d050 {
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compatible = "microchip,sam9x60-sckc";
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reg = <0xe001d050 0x4>;
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clocks = <&slow_rc_osc>, <&slow_xtal>;
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#clock-cells = <1>;
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};
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sdmmc0: sdio-host@e1204000 {
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compatible = "microchip,sama7g5-sdhci";
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reg = <0xe1204000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
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assigned-clock-rates = <200000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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status = "disabled";
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};
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sdmmc1: sdio-host@e1208000 {
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compatible = "microchip,sama7g5-sdhci";
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reg = <0xe1208000 0x300>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
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assigned-clock-rates = <200000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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status = "disabled";
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};
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pit64b0: timer@e1800000 {
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compatible = "microchip,sama7g5-pit64b";
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reg = <0xe1800000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
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clock-names = "pclk", "gclk";
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status = "okay";
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};
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flx1: flexcom@e181c000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe181c000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe181c000 0x800>;
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status = "disabled";
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i2c1: i2c@600 {
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compatible = "atmel,sama5d2-i2c";
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reg = <0x600 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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};
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};
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uart0: serial@e1824200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xe1824200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "usart";
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status = "disabled";
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};
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gmac0: ethernet@e2800000 {
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compatible = "cdns,sama7g5-gem";
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reg = <0xe2800000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
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clock-names = "hclk", "pclk", "tx_clk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
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assigned-clock-rates = <125000000>;
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status = "disabled";
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};
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gmac1: ethernet@e2804000 {
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compatible = "cdns,sama7g5-emac";
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reg = <0xe2804000 0x1000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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};
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};
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};
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65
arch/arm/dts/sama7g5ek-u-boot.dtsi
Normal file
65
arch/arm/dts/sama7g5ek-u-boot.dtsi
Normal file
@@ -0,0 +1,65 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5ek-u-boot.dts - Device Tree file for SAMA7G5 SoC u-boot properties.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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/ {
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chosen {
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u-boot,dm-pre-reloc;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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};
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};
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};
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&main_rc {
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u-boot,dm-pre-reloc;
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};
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&main_xtal {
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u-boot,dm-pre-reloc;
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};
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&pioA {
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u-boot,dm-pre-reloc;
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pinctrl {
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u-boot,dm-pre-reloc;
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};
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};
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&pinctrl_flx3_default {
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u-boot,dm-pre-reloc;
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};
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&pit64b0 {
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u-boot,dm-pre-reloc;
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};
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&pmc {
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u-boot,dm-pre-reloc;
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};
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&slow_rc_osc {
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u-boot,dm-pre-reloc;
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};
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&slow_xtal {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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202
arch/arm/dts/sama7g5ek.dts
Normal file
202
arch/arm/dts/sama7g5ek.dts
Normal file
@@ -0,0 +1,202 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* sama7g5ek.dts - Device Tree file for SAMA7G5 EK
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* SAMA7G5 Evaluation Kit
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*
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* Copyright (c) 2020, Microchip Technology Inc.
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* 2020, Eugen Hristev <eugen.hristev@microchip.com>
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* 2020, Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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/dts-v1/;
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#include "sama7g5.dtsi"
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#include "sama7g5-pinfunc.h"
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/ {
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model = "Microchip SAMA7G5 Evaluation Kit";
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compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
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aliases {
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serial0 = &uart0;
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i2c0 = &i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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clocks {
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slow_xtal: slow_xtal {
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clock-frequency = <32768>;
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};
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main_xtal: main_xtal {
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clock-frequency = <24000000>;
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};
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};
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ahb {
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apb {
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sdmmc0: sdio-host@e1204000 {
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default
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&pinctrl_sdmmc0_ck_rstn_ds_cd_default>;
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status = "okay";
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};
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sdmmc1: sdio-host@e1208000 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
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&pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
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status = "okay";
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};
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uart0: serial@e1824200 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx3_default>;
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status = "okay";
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};
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};
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};
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};
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&flx1 {
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atmel,flexcom-mode = <3>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flx1_default>;
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status = "okay";
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eeprom@52 {
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compatible = "microchip,24aa02e48";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "microchip,24aa02e48";
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reg = <0x53>;
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pagesize = <16>;
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};
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};
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&gmac0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txc_default>;
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phy-mode = "rgmii-id";
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status = "okay";
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ethernet-phy@7 {
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reg = <0x7>;
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};
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};
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&gmac1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gmac1_default>;
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phy-mode = "rmii";
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status = "okay";
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ethernet-phy@0 {
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reg = <0x0>;
|
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};
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};
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&pinctrl {
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pinctrl_flx1_default: flx1_default {
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pinmux = <PIN_PC9__FLEXCOM1_IO0>,
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<PIN_PC10__FLEXCOM1_IO1>;
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bias-disable;
|
||||
};
|
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|
||||
pinctrl_flx3_default: flx3_default {
|
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pinmux = <PIN_PD16__FLEXCOM3_IO0>,
|
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<PIN_PD17__FLEXCOM3_IO1>;
|
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bias-disable;
|
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};
|
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|
||||
pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
|
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pinmux = <PIN_PA1__SDMMC0_CMD>,
|
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<PIN_PA3__SDMMC0_DAT0>,
|
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<PIN_PA4__SDMMC0_DAT1>,
|
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<PIN_PA5__SDMMC0_DAT2>,
|
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<PIN_PA6__SDMMC0_DAT3>,
|
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<PIN_PA7__SDMMC0_DAT4>,
|
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<PIN_PA8__SDMMC0_DAT5>,
|
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<PIN_PA9__SDMMC0_DAT6>,
|
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<PIN_PA10__SDMMC0_DAT7>;
|
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bias-pull-up;
|
||||
};
|
||||
|
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pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default {
|
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pinmux = <PIN_PA0__SDMMC0_CK>,
|
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<PIN_PA2__SDMMC0_RSTN>,
|
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<PIN_PA11__SDMMC0_DS>,
|
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<PIN_PA14__SDMMC0_CD>;
|
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bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
|
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pinmux = <PIN_PB29__SDMMC1_CMD>,
|
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<PIN_PB31__SDMMC1_DAT0>,
|
||||
<PIN_PC0__SDMMC1_DAT1>,
|
||||
<PIN_PC1__SDMMC1_DAT2>,
|
||||
<PIN_PC2__SDMMC1_DAT3>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
|
||||
pinmux = <PIN_PB30__SDMMC1_CK>,
|
||||
<PIN_PB28__SDMMC1_RSTN>,
|
||||
<PIN_PC5__SDMMC1_1V8SEL>,
|
||||
<PIN_PC4__SDMMC1_CD>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_gmac0_default: gmac0_default {
|
||||
pinmux = <PIN_PA16__G0_TX0>,
|
||||
<PIN_PA17__G0_TX1>,
|
||||
<PIN_PA26__G0_TX2>,
|
||||
<PIN_PA27__G0_TX3>,
|
||||
<PIN_PA19__G0_RX0>,
|
||||
<PIN_PA20__G0_RX1>,
|
||||
<PIN_PA28__G0_RX2>,
|
||||
<PIN_PA29__G0_RX3>,
|
||||
<PIN_PA15__G0_TXEN>,
|
||||
<PIN_PA30__G0_RXCK>,
|
||||
<PIN_PA18__G0_RXDV>,
|
||||
<PIN_PA22__G0_MDC>,
|
||||
<PIN_PA23__G0_MDIO>,
|
||||
<PIN_PA25__G0_125CK>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_gmac0_txc_default: gmac0_txc_default {
|
||||
pinmux = <PIN_PA24__G0_TXCK>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_gmac1_default: gmac1_default {
|
||||
pinmux = <PIN_PD30__G1_TXCK>,
|
||||
<PIN_PD22__G1_TX0>,
|
||||
<PIN_PD23__G1_TX1>,
|
||||
<PIN_PD21__G1_TXEN>,
|
||||
<PIN_PD25__G1_RX0>,
|
||||
<PIN_PD26__G1_RX1>,
|
||||
<PIN_PD27__G1_RXER>,
|
||||
<PIN_PD24__G1_RXDV>,
|
||||
<PIN_PD28__G1_MDC>,
|
||||
<PIN_PD29__G1_MDIO>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
@@ -265,6 +265,13 @@ config TARGET_CORVUS
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_SAMA7G5EK
|
||||
bool "SAMA7G5 EK board"
|
||||
select SAMA7G5
|
||||
select BOARD_EARLY_INIT_F
|
||||
select BOARD_LATE_INIT
|
||||
|
||||
|
||||
config TARGET_TAURUS
|
||||
bool "Support taurus"
|
||||
select AT91SAM9G20
|
||||
@@ -327,6 +334,7 @@ source "board/atmel/at91sam9n12ek/Kconfig"
|
||||
source "board/atmel/at91sam9rlek/Kconfig"
|
||||
source "board/atmel/at91sam9x5ek/Kconfig"
|
||||
source "board/atmel/sam9x60ek/Kconfig"
|
||||
source "board/atmel/sama7g5ek/Kconfig"
|
||||
source "board/atmel/sama5d2_ptc_ek/Kconfig"
|
||||
source "board/atmel/sama5d2_xplained/Kconfig"
|
||||
source "board/atmel/sama5d27_som1_ek/Kconfig"
|
||||
|
||||
Reference in New Issue
Block a user