arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC
Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
This commit is contained in:
Patrick Bruenn
committed by
Stefano Babic
Stefano Babic
parent
8e1d92fdbc
commit
98d62e618b
198
include/configs/mx53cx9020.h
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198
include/configs/mx53cx9020.h
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/*
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* Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
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* Patrick Bruenn <p.bruenn@beckhoff.com>
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*
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* Configuration settings for Beckhoff CX9020.
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*
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* Based on Freescale's Linux i.MX mx53loco.h file:
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* Copyright (C) 2010-2011 Freescale Semiconductor.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_MXC_GPIO
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#define CONFIG_REVISION_TAG
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#define CONFIG_MXC_UART_BASE UART2_BASE
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#define CONFIG_FPGA_COUNT 1
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/* MMC Configs */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 2
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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/* bootz: zImage/initrd.img support */
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#define CONFIG_DOS_PARTITION
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/* Eth Configs */
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#define CONFIG_MII
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_ETHPRIME "FEC0"
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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/* USB Configs */
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX5
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_ETHER_MCS7830
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_MXC_USB_PORT 1
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* Command definition */
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */
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#define CONFIG_SYS_TEXT_BASE 0x77800000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_addr=0x71ff0000\0" \
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"rdaddr=0x72000000\0" \
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"console=ttymxc1,115200\0" \
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"uenv=/boot/uEnv.txt\0" \
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"optargs=\0" \
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"cmdline=\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcrootfstype=ext4 rootwait fixrtc\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
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"rootfstype=${mmcrootfstype} " \
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"${cmdline}\0" \
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"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
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"loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \
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"setenv rdsize ${filesize}\0" \
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"loadfdt=echo loading ${fdt_path} ...;" \
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"load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \
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"mmcboot=mmc dev ${mmcdev}; " \
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"if mmc rescan; then " \
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"echo SD/MMC found on device ${mmcdev};" \
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"echo Checking for: ${uenv} ...;" \
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"setenv bootpart ${mmcdev}:${mmcpart};" \
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"if test -e mmc ${bootpart} ${uenv}; then " \
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"load mmc ${bootpart} ${loadaddr} ${uenv};" \
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"env import -t ${loadaddr} ${filesize};" \
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"echo Loaded environment from ${uenv};" \
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"if test -n ${dtb}; then " \
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"setenv fdt_file ${dtb};" \
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"echo Using: dtb=${fdt_file} ...;" \
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"fi;" \
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"echo Checking for uname_r in ${uenv}...;" \
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"if test -n ${uname_r}; then " \
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"echo Running uname_boot ...;" \
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"run uname_boot;" \
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"fi;" \
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"fi;" \
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"fi;\0" \
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"uname_boot="\
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"setenv bootdir /boot; " \
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"setenv bootfile vmlinuz-${uname_r}; " \
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"setenv ccatfile /boot/ccat.rbf; " \
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"echo loading CCAT firmware from ${ccatfile}; " \
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"load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
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"fpga load 0 ${loadaddr} ${filesize}; " \
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"if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
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"echo loading ${bootdir}/${bootfile} ...; " \
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"run loadimage;" \
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"setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
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"if test -e mmc ${bootpart} ${fdt_path}; then " \
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"run loadfdt;" \
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"else " \
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"echo; echo unable to find ${fdt_file} ...;" \
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"echo booting legacy ...;"\
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"run mmcargs;" \
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"echo debug: [${bootargs}] ... ;" \
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"echo debug: [bootz ${loadaddr}] ... ;" \
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"bootz ${loadaddr}; " \
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"fi;" \
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"run mmcargs;" \
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"echo debug: [${bootargs}] ... ;" \
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"echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"run mmcboot;"
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#define CONFIG_ARP_TIMEOUT 200UL
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x70000000
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#define CONFIG_SYS_MEMTEST_END 0x70010000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_CMDLINE_EDITING
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
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#define PHYS_SDRAM_2 CSD1_BASE_ADDR
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#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
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#define PHYS_SDRAM_SIZE (gd->ram_size)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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/* Framebuffer and LCD */
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#define CONFIG_PREBOOT
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 200000000
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#endif /* __CONFIG_H */
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219
include/dt-bindings/clock/imx5-clock.h
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219
include/dt-bindings/clock/imx5-clock.h
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/*
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* Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX5_H
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#define __DT_BINDINGS_CLOCK_IMX5_H
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#define IMX5_CLK_DUMMY 0
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#define IMX5_CLK_CKIL 1
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#define IMX5_CLK_OSC 2
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#define IMX5_CLK_CKIH1 3
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#define IMX5_CLK_CKIH2 4
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#define IMX5_CLK_AHB 5
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#define IMX5_CLK_IPG 6
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#define IMX5_CLK_AXI_A 7
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#define IMX5_CLK_AXI_B 8
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#define IMX5_CLK_UART_PRED 9
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#define IMX5_CLK_UART_ROOT 10
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#define IMX5_CLK_ESDHC_A_PRED 11
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#define IMX5_CLK_ESDHC_B_PRED 12
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#define IMX5_CLK_ESDHC_C_SEL 13
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#define IMX5_CLK_ESDHC_D_SEL 14
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#define IMX5_CLK_EMI_SEL 15
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#define IMX5_CLK_EMI_SLOW_PODF 16
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#define IMX5_CLK_NFC_PODF 17
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#define IMX5_CLK_ECSPI_PRED 18
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#define IMX5_CLK_ECSPI_PODF 19
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#define IMX5_CLK_USBOH3_PRED 20
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#define IMX5_CLK_USBOH3_PODF 21
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#define IMX5_CLK_USB_PHY_PRED 22
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#define IMX5_CLK_USB_PHY_PODF 23
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#define IMX5_CLK_CPU_PODF 24
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#define IMX5_CLK_DI_PRED 25
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#define IMX5_CLK_TVE_SEL 27
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#define IMX5_CLK_UART1_IPG_GATE 28
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#define IMX5_CLK_UART1_PER_GATE 29
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#define IMX5_CLK_UART2_IPG_GATE 30
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#define IMX5_CLK_UART2_PER_GATE 31
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#define IMX5_CLK_UART3_IPG_GATE 32
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#define IMX5_CLK_UART3_PER_GATE 33
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#define IMX5_CLK_I2C1_GATE 34
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#define IMX5_CLK_I2C2_GATE 35
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#define IMX5_CLK_GPT_IPG_GATE 36
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#define IMX5_CLK_PWM1_IPG_GATE 37
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#define IMX5_CLK_PWM1_HF_GATE 38
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#define IMX5_CLK_PWM2_IPG_GATE 39
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#define IMX5_CLK_PWM2_HF_GATE 40
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#define IMX5_CLK_GPT_HF_GATE 41
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#define IMX5_CLK_FEC_GATE 42
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#define IMX5_CLK_USBOH3_PER_GATE 43
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#define IMX5_CLK_ESDHC1_IPG_GATE 44
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#define IMX5_CLK_ESDHC2_IPG_GATE 45
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#define IMX5_CLK_ESDHC3_IPG_GATE 46
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#define IMX5_CLK_ESDHC4_IPG_GATE 47
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#define IMX5_CLK_SSI1_IPG_GATE 48
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#define IMX5_CLK_SSI2_IPG_GATE 49
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#define IMX5_CLK_SSI3_IPG_GATE 50
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#define IMX5_CLK_ECSPI1_IPG_GATE 51
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#define IMX5_CLK_ECSPI1_PER_GATE 52
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#define IMX5_CLK_ECSPI2_IPG_GATE 53
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#define IMX5_CLK_ECSPI2_PER_GATE 54
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#define IMX5_CLK_CSPI_IPG_GATE 55
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#define IMX5_CLK_SDMA_GATE 56
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#define IMX5_CLK_EMI_SLOW_GATE 57
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#define IMX5_CLK_IPU_SEL 58
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#define IMX5_CLK_IPU_GATE 59
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#define IMX5_CLK_NFC_GATE 60
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#define IMX5_CLK_IPU_DI1_GATE 61
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#define IMX5_CLK_VPU_SEL 62
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#define IMX5_CLK_VPU_GATE 63
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#define IMX5_CLK_VPU_REFERENCE_GATE 64
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#define IMX5_CLK_UART4_IPG_GATE 65
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#define IMX5_CLK_UART4_PER_GATE 66
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#define IMX5_CLK_UART5_IPG_GATE 67
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#define IMX5_CLK_UART5_PER_GATE 68
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#define IMX5_CLK_TVE_GATE 69
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#define IMX5_CLK_TVE_PRED 70
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#define IMX5_CLK_ESDHC1_PER_GATE 71
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#define IMX5_CLK_ESDHC2_PER_GATE 72
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#define IMX5_CLK_ESDHC3_PER_GATE 73
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#define IMX5_CLK_ESDHC4_PER_GATE 74
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#define IMX5_CLK_USB_PHY_GATE 75
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#define IMX5_CLK_HSI2C_GATE 76
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#define IMX5_CLK_MIPI_HSC1_GATE 77
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#define IMX5_CLK_MIPI_HSC2_GATE 78
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#define IMX5_CLK_MIPI_ESC_GATE 79
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#define IMX5_CLK_MIPI_HSP_GATE 80
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#define IMX5_CLK_LDB_DI1_DIV_3_5 81
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#define IMX5_CLK_LDB_DI1_DIV 82
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#define IMX5_CLK_LDB_DI0_DIV_3_5 83
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#define IMX5_CLK_LDB_DI0_DIV 84
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#define IMX5_CLK_LDB_DI1_GATE 85
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#define IMX5_CLK_CAN2_SERIAL_GATE 86
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#define IMX5_CLK_CAN2_IPG_GATE 87
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#define IMX5_CLK_I2C3_GATE 88
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#define IMX5_CLK_LP_APM 89
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#define IMX5_CLK_PERIPH_APM 90
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#define IMX5_CLK_MAIN_BUS 91
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#define IMX5_CLK_AHB_MAX 92
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#define IMX5_CLK_AIPS_TZ1 93
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#define IMX5_CLK_AIPS_TZ2 94
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#define IMX5_CLK_TMAX1 95
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#define IMX5_CLK_TMAX2 96
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#define IMX5_CLK_TMAX3 97
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#define IMX5_CLK_SPBA 98
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#define IMX5_CLK_UART_SEL 99
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#define IMX5_CLK_ESDHC_A_SEL 100
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#define IMX5_CLK_ESDHC_B_SEL 101
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#define IMX5_CLK_ESDHC_A_PODF 102
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#define IMX5_CLK_ESDHC_B_PODF 103
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#define IMX5_CLK_ECSPI_SEL 104
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#define IMX5_CLK_USBOH3_SEL 105
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#define IMX5_CLK_USB_PHY_SEL 106
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#define IMX5_CLK_IIM_GATE 107
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#define IMX5_CLK_USBOH3_GATE 108
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#define IMX5_CLK_EMI_FAST_GATE 109
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#define IMX5_CLK_IPU_DI0_GATE 110
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#define IMX5_CLK_GPC_DVFS 111
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#define IMX5_CLK_PLL1_SW 112
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#define IMX5_CLK_PLL2_SW 113
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#define IMX5_CLK_PLL3_SW 114
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#define IMX5_CLK_IPU_DI0_SEL 115
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#define IMX5_CLK_IPU_DI1_SEL 116
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#define IMX5_CLK_TVE_EXT_SEL 117
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#define IMX5_CLK_MX51_MIPI 118
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#define IMX5_CLK_PLL4_SW 119
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#define IMX5_CLK_LDB_DI1_SEL 120
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#define IMX5_CLK_DI_PLL4_PODF 121
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#define IMX5_CLK_LDB_DI0_SEL 122
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#define IMX5_CLK_LDB_DI0_GATE 123
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#define IMX5_CLK_USB_PHY1_GATE 124
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#define IMX5_CLK_USB_PHY2_GATE 125
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#define IMX5_CLK_PER_LP_APM 126
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#define IMX5_CLK_PER_PRED1 127
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#define IMX5_CLK_PER_PRED2 128
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#define IMX5_CLK_PER_PODF 129
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#define IMX5_CLK_PER_ROOT 130
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#define IMX5_CLK_SSI_APM 131
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#define IMX5_CLK_SSI1_ROOT_SEL 132
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#define IMX5_CLK_SSI2_ROOT_SEL 133
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#define IMX5_CLK_SSI3_ROOT_SEL 134
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#define IMX5_CLK_SSI_EXT1_SEL 135
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#define IMX5_CLK_SSI_EXT2_SEL 136
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#define IMX5_CLK_SSI_EXT1_COM_SEL 137
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#define IMX5_CLK_SSI_EXT2_COM_SEL 138
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#define IMX5_CLK_SSI1_ROOT_PRED 139
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#define IMX5_CLK_SSI1_ROOT_PODF 140
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#define IMX5_CLK_SSI2_ROOT_PRED 141
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#define IMX5_CLK_SSI2_ROOT_PODF 142
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#define IMX5_CLK_SSI_EXT1_PRED 143
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#define IMX5_CLK_SSI_EXT1_PODF 144
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#define IMX5_CLK_SSI_EXT2_PRED 145
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#define IMX5_CLK_SSI_EXT2_PODF 146
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#define IMX5_CLK_SSI1_ROOT_GATE 147
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#define IMX5_CLK_SSI2_ROOT_GATE 148
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#define IMX5_CLK_SSI3_ROOT_GATE 149
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#define IMX5_CLK_SSI_EXT1_GATE 150
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#define IMX5_CLK_SSI_EXT2_GATE 151
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#define IMX5_CLK_EPIT1_IPG_GATE 152
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#define IMX5_CLK_EPIT1_HF_GATE 153
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#define IMX5_CLK_EPIT2_IPG_GATE 154
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#define IMX5_CLK_EPIT2_HF_GATE 155
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#define IMX5_CLK_CAN_SEL 156
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#define IMX5_CLK_CAN1_SERIAL_GATE 157
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#define IMX5_CLK_CAN1_IPG_GATE 158
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#define IMX5_CLK_OWIRE_GATE 159
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#define IMX5_CLK_GPU3D_SEL 160
|
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#define IMX5_CLK_GPU2D_SEL 161
|
||||
#define IMX5_CLK_GPU3D_GATE 162
|
||||
#define IMX5_CLK_GPU2D_GATE 163
|
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#define IMX5_CLK_GARB_GATE 164
|
||||
#define IMX5_CLK_CKO1_SEL 165
|
||||
#define IMX5_CLK_CKO1_PODF 166
|
||||
#define IMX5_CLK_CKO1 167
|
||||
#define IMX5_CLK_CKO2_SEL 168
|
||||
#define IMX5_CLK_CKO2_PODF 169
|
||||
#define IMX5_CLK_CKO2 170
|
||||
#define IMX5_CLK_SRTC_GATE 171
|
||||
#define IMX5_CLK_PATA_GATE 172
|
||||
#define IMX5_CLK_SATA_GATE 173
|
||||
#define IMX5_CLK_SPDIF_XTAL_SEL 174
|
||||
#define IMX5_CLK_SPDIF0_SEL 175
|
||||
#define IMX5_CLK_SPDIF1_SEL 176
|
||||
#define IMX5_CLK_SPDIF0_PRED 177
|
||||
#define IMX5_CLK_SPDIF0_PODF 178
|
||||
#define IMX5_CLK_SPDIF1_PRED 179
|
||||
#define IMX5_CLK_SPDIF1_PODF 180
|
||||
#define IMX5_CLK_SPDIF0_COM_SEL 181
|
||||
#define IMX5_CLK_SPDIF1_COM_SEL 182
|
||||
#define IMX5_CLK_SPDIF0_GATE 183
|
||||
#define IMX5_CLK_SPDIF1_GATE 184
|
||||
#define IMX5_CLK_SPDIF_IPG_GATE 185
|
||||
#define IMX5_CLK_OCRAM 186
|
||||
#define IMX5_CLK_SAHARA_IPG_GATE 187
|
||||
#define IMX5_CLK_SATA_REF 188
|
||||
#define IMX5_CLK_STEP_SEL 189
|
||||
#define IMX5_CLK_CPU_PODF_SEL 190
|
||||
#define IMX5_CLK_ARM 191
|
||||
#define IMX5_CLK_FIRI_PRED 192
|
||||
#define IMX5_CLK_FIRI_SEL 193
|
||||
#define IMX5_CLK_FIRI_PODF 194
|
||||
#define IMX5_CLK_FIRI_SERIAL_GATE 195
|
||||
#define IMX5_CLK_FIRI_IPG_GATE 196
|
||||
#define IMX5_CLK_CSI0_MCLK1_PRED 197
|
||||
#define IMX5_CLK_CSI0_MCLK1_SEL 198
|
||||
#define IMX5_CLK_CSI0_MCLK1_PODF 199
|
||||
#define IMX5_CLK_CSI0_MCLK1_GATE 200
|
||||
#define IMX5_CLK_IEEE1588_PRED 201
|
||||
#define IMX5_CLK_IEEE1588_SEL 202
|
||||
#define IMX5_CLK_IEEE1588_PODF 203
|
||||
#define IMX5_CLK_IEEE1588_GATE 204
|
||||
#define IMX5_CLK_END 205
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
|
||||
Reference in New Issue
Block a user