arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC
Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
This commit is contained in:
Patrick Bruenn
committed by
Stefano Babic
Stefano Babic
parent
8e1d92fdbc
commit
98d62e618b
@@ -18,11 +18,19 @@ config TARGET_USBARMORY
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bool "Support USB armory"
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select CPU_V7
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config TARGET_MX53CX9020
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bool "Support CX9020"
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select CPU_V7
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select MX53
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select DM
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select DM_SERIAL
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endchoice
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config SYS_SOC
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default "mx5"
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source "board/beckhoff/mx53cx9020/Kconfig"
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source "board/inversepath/usbarmory/Kconfig"
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endif
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@@ -293,6 +293,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
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pcm052.dtb \
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bk4r1.dtb
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dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
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dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6sll-evk.dtb \
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imx6dl-icore.dtb \
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190
arch/arm/dts/imx53-cx9020.dts
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190
arch/arm/dts/imx53-cx9020.dts
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@@ -0,0 +1,190 @@
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/*
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* Copyright 2016 Beckhoff Automation
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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/dts-v1/;
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#include "imx53.dtsi"
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#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
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#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
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#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
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#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
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/ {
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model = "Beckhoff CX9020-0100 i.MX53";
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compatible = "fsl,imx53-qsb", "fsl,imx53";
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chosen {
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stdout-path = &uart2;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx53-qsb {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
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MX53_PAD_GPIO_8__GPIO1_8 0x80000000
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MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
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MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
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MX53_PAD_GPIO_1__GPIO1_1 0x80000000
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MX53_PAD_GPIO_4__GPIO1_4 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
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MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
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MX53_PAD_GPIO_16__GPIO7_11 0x80000000
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MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
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MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000
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MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000
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MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000
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MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000
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MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000
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MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000
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MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000
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MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000
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MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000
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MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000
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MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000
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MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000
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MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000
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MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000
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MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000
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MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000
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MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4
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MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4
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MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4
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MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4
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MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4
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MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4
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MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4
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MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4
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MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4
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MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4
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MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4
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MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4
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MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4
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MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4
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MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4
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MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4
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MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
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MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
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MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
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MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
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MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
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MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
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MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
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MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
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MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4
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MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4
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MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4
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MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4
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MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4
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MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4
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MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4
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MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4
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MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001
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MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001
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MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001
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MX53_PAD_EIM_D23__GPIO3_23 0x80000000
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MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
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MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
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MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
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MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
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MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
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MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
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MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
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MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
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MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
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MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
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MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
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MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
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MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
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MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
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MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
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MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
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MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
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MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
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MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
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MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
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MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
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MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5
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MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
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MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
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MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
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MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
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MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
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MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
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MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
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MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
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MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
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MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
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MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
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MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
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MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
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MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
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MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
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MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
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MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
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MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
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MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
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MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
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MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
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MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
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MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
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MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
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MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4
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MX53_PAD_EIM_D28__UART2_RTS 0x1e4
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MX53_PAD_EIM_D29__UART2_CTS 0x1e4
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>;
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};
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};
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};
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&uart2 {
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pinctrl-names = "default";
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uart-has-rtscts;
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fsl,dte-mode;
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 0>;
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status = "okay";
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};
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1189
arch/arm/dts/imx53-pinfunc.h
Normal file
1189
arch/arm/dts/imx53-pinfunc.h
Normal file
File diff suppressed because it is too large
Load Diff
110
arch/arm/dts/imx53.dtsi
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110
arch/arm/dts/imx53.dtsi
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@@ -0,0 +1,110 @@
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/*
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* Copyright 2016 Beckhoff Automation
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx53-pinfunc.h"
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#include <dt-bindings/clock/imx5-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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serial1 = &uart2;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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aips@50000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x10000000>;
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ranges;
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iomuxc: iomuxc@53fa8000 {
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compatible = "fsl,imx53-iomuxc";
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reg = <0x53fa8000 0x4000>;
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};
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gpr: iomuxc-gpr@53fa8000 {
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compatible = "fsl,imx53-iomuxc-gpr", "syscon";
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reg = <0x53fa8000 0xc>;
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};
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uart2: serial@53fc0000 {
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compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
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reg = <0x53fc0000 0x4000>;
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interrupts = <32>;
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clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
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<&clks IMX5_CLK_UART2_PER_GATE>;
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clock-names = "ipg", "per";
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dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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clks: ccm@53fd4000{
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compatible = "fsl,imx53-ccm";
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reg = <0x53fd4000 0x4000>;
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interrupts = <0 71 0x04 0 72 0x04>;
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#clock-cells = <1>;
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};
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gpio7: gpio@53fe4000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53fe4000 0x4000>;
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interrupts = <107 108>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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aips@60000000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x60000000 0x10000000>;
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ranges;
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sdma: sdma@63fb0000 {
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compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
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reg = <0x63fb0000 0x4000>;
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interrupts = <6>;
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clocks = <&clks IMX5_CLK_SDMA_GATE>,
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<&clks IMX5_CLK_SDMA_GATE>;
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clock-names = "ipg", "ahb";
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#dma-cells = <3>;
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
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};
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fec: ethernet@63fec000 {
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compatible = "fsl,imx53-fec", "fsl,imx25-fec";
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reg = <0x63fec000 0x4000>;
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interrupts = <87>;
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clocks = <&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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};
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};
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};
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