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ARM: DRA7xx: clocks: Update PLL values

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Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
This commit is contained in:
Lokesh Vutla
2013-05-30 03:19:38 +00:00
committed by Tom Rini
parent 7f36c88f64
commit 97405d843e
7 changed files with 73 additions and 46 deletions
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2
include/configs/dra7xx_evm.h
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@@ -39,4 +39,6 @@
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 UART1_BASE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_OMAP_ABE_SYSCK
#endif /* __CONFIG_DRA7XX_EVM_H */