From 4e521e143082db6821bd3ee36f5cb990d8105253 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Fri, 12 Mar 2021 17:51:10 +0800 Subject: [PATCH 01/11] arm: socfpga: smc: Remove unused SMC function ID Remove unused SMC function ID 61 and 62. Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- include/linux/intel-smc.h | 52 --------------------------------------- 1 file changed, 52 deletions(-) diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index cacb410691..68d62be417 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -518,56 +518,4 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_MBOX_SEND_CMD \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) -/* - * Request INTEL_SIP_SMC_HPS_SET_PHYINTF - * - * Select EMACx PHY interface - * - * Call register usage: - * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF - * a1 EMAC number: - * 0 - EMAC0 - * 1 - EMAC1 - * 2 - EMAC2 - * a2 Type of PHY interface: - * 0 - GMII_MII - * 1 - RGMII - * 2 - RMII - * 3 - RESET - * a3-7 not used - * - * Return status - * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR - */ -#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61 -#define INTEL_SIP_SMC_HPS_SET_PHYINTF \ - INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF) - -/* - * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK - * - * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC - * - * Call register usage: - * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK - * a1 Select which phase shift of the clock for cclk_in_drv (drvsel): - * 0 - 0 degree - * 1 - 45 degrees - * 2 - 90 degrees - * 3 - 135 degrees - * 4 - 180 degrees - * 5 - 225 degrees - * 6 - 270 degrees - * 7 - 315 degrees - * a2 Select which phase shift of the clock for cclk_in_sample (smplsel): - * (Same as above) - * a3-7 not used - * - * Return status - * a0 INTEL_SIP_SMC_STATUS_OK - */ -#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62 -#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \ - INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK) - #endif From f86ed75059966e9cf1964b95850058e5a63683e4 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Mon, 15 Mar 2021 15:59:16 +0800 Subject: [PATCH 02/11] arm: socfpga: Move Stratix10 and Agilex SPL common code Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/Makefile | 2 ++ arch/arm/mach-socfpga/spl_agilex.c | 16 ---------------- arch/arm/mach-socfpga/spl_s10.c | 17 ----------------- arch/arm/mach-socfpga/spl_soc64.c | 25 +++++++++++++++++++++++++ 4 files changed, 27 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-socfpga/spl_soc64.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 9e63296b38..e4c2da93d5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -70,10 +70,12 @@ endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += firewall.o obj-y += spl_s10.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += firewall.o obj-y += spl_agilex.o +obj-y += spl_soc64.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 71b17ce3a5..ee5a9dc1e2 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -25,22 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_mmc_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif -} -#endif - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 955a1161e8..c20e87cdbe 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -26,23 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) -{ - /* TODO: Get from SDM or handoff */ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_mmc_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif -} -#endif - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c new file mode 100644 index 0000000000..cb98ab39e4 --- /dev/null +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation. All rights reserved + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT) +u32 spl_boot_mode(const u32 boot_device) +{ + if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) + return MMCSD_MODE_FS; + else + return MMCSD_MODE_RAW; +} +#endif From 8f337f37218c49cae518787c0c330ece0c68127a Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 13:11:34 +0800 Subject: [PATCH 03/11] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- .../mach-socfpga/include/mach/handoff_s10.h | 39 ------------------- .../mach-socfpga/include/mach/handoff_soc64.h | 39 +++++++++++++++++++ .../arm/mach-socfpga/wrap_pinmux_config_s10.c | 18 ++++----- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 16 ++++---- include/configs/socfpga_soc64_common.h | 4 +- 6 files changed, 59 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 642dcbb0ac..e060e5754e 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h deleted file mode 100644 index 3e9b606ce2..0000000000 --- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2016-2018 Intel Corporation - * - */ - -#ifndef _HANDOFF_S10_H_ -#define _HANDOFF_S10_H_ - -/* - * Offset for HW handoff from Quartus tools - */ -#define S10_HANDOFF_BASE 0xFFE3F000 -#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10) -#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0) -#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330) -#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0) -#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580) -#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610) -#define S10_HANDOFF_MAGIC_MUX 0x504D5558 -#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354 -#define S10_HANDOFF_MAGIC_FPGA 0x46504741 -#define S10_HANDOFF_MAGIC_DELAY 0x444C4159 -#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53 -#define S10_HANDOFF_MAGIC_MISC 0x4D495343 -#define S10_HANDOFF_OFFSET_LENGTH 0x4 -#define S10_HANDOFF_OFFSET_DATA 0x10 - -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 -#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) -#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) -#else -#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc) -#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600) -#endif - -#define S10_HANDOFF_SIZE 4096 - -#endif /* _HANDOFF_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h new file mode 100644 index 0000000000..804715b13d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#ifndef _HANDOFF_SOC64_H_ +#define _HANDOFF_SOC64_H_ + +/* + * Offset for HW handoff from Quartus tools + */ +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 +#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 +#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 +#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 +#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 +#define SOC64_HANDOFF_OFFSET_LENGTH 0x4 +#define SOC64_HANDOFF_OFFSET_DATA 0x10 + +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#else +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) +#endif + +#define SOC64_HANDOFF_SIZE 4096 + +#endif /* _HANDOFF_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c index 0b497ec30c..d10fb5e454 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c @@ -7,23 +7,23 @@ #include #include #include -#include +#include static void sysmgr_pinmux_handoff_read(void *handoff_address, const u32 **table, unsigned int *table_len) { unsigned int handoff_entry = (swab32(readl(handoff_address + - S10_HANDOFF_OFFSET_LENGTH)) - - S10_HANDOFF_OFFSET_DATA) / + SOC64_HANDOFF_OFFSET_LENGTH)) - + SOC64_HANDOFF_OFFSET_DATA) / sizeof(unsigned int); unsigned int handoff_chunk[handoff_entry], temp, i; - if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) { + if (swab32(readl(SOC64_HANDOFF_MUX)) == SOC64_HANDOFF_MAGIC_MUX) { /* using handoff from Quartus tools if exists */ for (i = 0; i < handoff_entry; i++) { temp = readl(handoff_address + - S10_HANDOFF_OFFSET_DATA + (i * 4)); + SOC64_HANDOFF_OFFSET_DATA + (i * 4)); handoff_chunk[i] = swab32(temp); } *table = handoff_chunk; @@ -33,24 +33,24 @@ static void sysmgr_pinmux_handoff_read(void *handoff_address, void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_MUX, table, table_len); } void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_IOCTL, table, table_len); } void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_FPGA, table, table_len); } void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_DELAY, table, table_len); } diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index 049c5711a8..6a0d6b5ead 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -7,24 +7,24 @@ #include #include #include -#include +#include #include const struct cm_config * const cm_get_default_config(void) { #ifdef CONFIG_SPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) - (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); + (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; u32 i; - u32 handoff_clk = readl(S10_HANDOFF_CLOCK); + u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK); - if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) { - writel(swab32(handoff_clk), S10_HANDOFF_CLOCK); + if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) { + writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK); for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) conversion[i] = swab32(conversion[i]); return cm_handoff_cfg; - } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { + } else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) { return cm_handoff_cfg; } #endif @@ -35,7 +35,7 @@ const unsigned int cm_get_osc_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(HANDOFF_CLOCK_OSC); + u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); writel(clock, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); @@ -52,7 +52,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(HANDOFF_CLOCK_FPGA); + u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); writel(clock, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 1cfa190047..5afdb10454 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -8,7 +8,7 @@ #define __CONFIG_SOCFPGA_SOC64_COMMON_H__ #include -#include +#include #include /* @@ -43,7 +43,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - - S10_HANDOFF_SIZE) + - SOC64_HANDOFF_SIZE) #else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ + 0x100000) From d623e52c9fae29161e5cdcefaf19a8c38f4b0aa9 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 13:11:35 +0800 Subject: [PATCH 04/11] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Rename to common file name to used by all SOC64 devices. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/Makefile | 4 ++-- .../{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} (100%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e4c2da93d5..eca6fd173f 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -38,7 +38,7 @@ obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o -obj-y += wrap_pll_config_s10.o +obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -53,7 +53,7 @@ obj-y += system_manager_s10.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_pinmux_config_s10.o -obj-y += wrap_pll_config_s10.o +obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c similarity index 100% rename from arch/arm/mach-socfpga/wrap_pll_config_s10.c rename to arch/arm/mach-socfpga/wrap_pll_config_soc64.c From bab26535ccd917ef2217a40ec31755910e11a63f Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 13:11:36 +0800 Subject: [PATCH 05/11] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/Makefile | 4 ++-- .../{system_manager_s10.c => system_manager_soc64.c} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} (100%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index eca6fd173f..f9dd166ab3 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -35,7 +35,7 @@ obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o -obj-y += system_manager_s10.o +obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_soc64.o @@ -49,7 +49,7 @@ obj-y += misc_s10.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o -obj-y += system_manager_s10.o +obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_soc64.c similarity index 100% rename from arch/arm/mach-socfpga/system_manager_s10.c rename to arch/arm/mach-socfpga/system_manager_soc64.c From a73514a8d29742c1f844f19226639da572e4cf15 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 13:11:37 +0800 Subject: [PATCH 06/11] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim --- .../mach-socfpga/include/mach/handoff_soc64.h | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 804715b13d..2561255712 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2020 Intel Corporation * */ @@ -10,21 +10,25 @@ /* * Offset for HW handoff from Quartus tools */ -#define SOC64_HANDOFF_BASE 0xFFE3F000 -#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) -#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0) -#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) -#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) -#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) -#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +/* HPS handoff */ #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 + #define SOC64_HANDOFF_OFFSET_LENGTH 0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 +#define SOC64_HANDOFF_SIZE 4096 + +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) @@ -34,6 +38,4 @@ #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif -#define SOC64_HANDOFF_SIZE 4096 - #endif /* _HANDOFF_SOC64_H_ */ From e2ffb1da1ddc442e4f48980e8524dd5b574012a2 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 13:11:38 +0800 Subject: [PATCH 07/11] arm: socfpga: Restructure Stratix10 and Agilex handoff code Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, in preparation to support handoff for Diamond Mesa. Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which contains the generic function to parse the handoff data. Update system_manager_soc64.c to use generic handoff function in wrap_handoff_soc64.c. Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/Makefile | 4 +- .../mach-socfpga/include/mach/handoff_soc64.h | 23 ++++++- .../include/mach/system_manager_soc64.h | 4 -- arch/arm/mach-socfpga/system_manager_soc64.c | 55 ++++++++++------ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 66 +++++++++++++++++++ .../arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 ---------------- 6 files changed, 126 insertions(+), 82 deletions(-) create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index f9dd166ab3..5779c55621 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -37,7 +37,7 @@ obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o -obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif @@ -52,7 +52,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o -obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 2561255712..3750216a9a 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -11,6 +11,7 @@ * Offset for HW handoff from Quartus tools */ /* HPS handoff */ +#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54 #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 @@ -30,7 +31,7 @@ #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) #else @@ -38,4 +39,24 @@ #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif +#define SOC64_HANDOFF_MUX_LEN 96 +#define SOC64_HANDOFF_IOCTL_LEN 96 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#define SOC64_HANDOFF_FPGA_LEN 42 +#else +#define SOC64_HANDOFF_FPGA_LEN 40 +#endif +#define SOC64_HANDOFF_DELAY_LEN 96 + +#ifndef __ASSEMBLY__ +#include +enum endianness { + LITTLE_ENDIAN = 0, + BIG_ENDIAN +}; + +int socfpga_get_handoff_size(void *handoff_address, enum endianness endian); +int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len, + enum endianness big_endian); +#endif #endif /* _HANDOFF_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 4949cae97a..1eb8e7a904 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -10,10 +10,6 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_SOC64_WDDBG 0x08 #define SYSMGR_SOC64_DMA 0x20 diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index c123cc9644..3b5e774e2d 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -4,10 +4,11 @@ * */ -#include +#include +#include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -64,39 +65,55 @@ void populate_sysmgr_fpgaintf_module(void) */ void populate_sysmgr_pinmux(void) { - const u32 *sys_mgr_table_u32; - unsigned int len, i; + u32 len, i; + u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX, BIG_ENDIAN); + u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL, BIG_ENDIAN); + u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA, BIG_ENDIAN); + u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY, BIG_ENDIAN); + + len = (len_mux > len_ioctl) ? len_mux : len_ioctl; + len = (len > len_fpga) ? len : len_fpga; + len = (len > len_delay) ? len : len_delay; + + u32 handoff_table[len]; /* setup the pin sel */ - sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); + len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len, BIG_ENDIAN); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + - (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0); + writel(handoff_table[i + 1], + handoff_table[i] + + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_PINSEL0); } /* setup the pin ctrl */ - sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); + len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len, BIG_ENDIAN); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + - (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0); + writel(handoff_table[i + 1], + handoff_table[i] + + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_IOCTRL0); } /* setup the fpga use */ - sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); + len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len, BIG_ENDIAN); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + + writel(handoff_table[i + 1], + handoff_table[i] + (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA); } /* setup the IO delay */ - sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); + len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len, BIG_ENDIAN); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + - (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0); + writel(handoff_table[i + 1], + handoff_table[i] + + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_IODELAY0); } } diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c new file mode 100644 index 0000000000..a7ad7a18ed --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation + * + */ + +#include +#include +#include +#include +#include "log.h" + +int socfpga_get_handoff_size(void *handoff_address, enum endianness endian) +{ + u32 size; + + size = readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH); + if (endian == BIG_ENDIAN) + size = swab32(size); + + size = (size - SOC64_HANDOFF_OFFSET_DATA) / sizeof(u32); + + debug("%s: handoff address = 0x%p handoff size = 0x%08x\n", __func__, + (u32 *)handoff_address, size); + + return size; +} + +int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len, + enum endianness big_endian) +{ + u32 temp, i; + u32 *table_x32 = table; + + debug("%s: handoff addr = 0x%p ", __func__, (u32 *)handoff_address); + + if (big_endian) { + if (swab32(readl(SOC64_HANDOFF_BASE)) == SOC64_HANDOFF_MAGIC_BOOT) { + debug("Handoff table address = 0x%p ", table_x32); + debug("table length = 0x%x\n", table_len); + debug("%s: handoff data =\n{\n", __func__); + + for (i = 0; i < table_len; i++) { + temp = readl(handoff_address + + SOC64_HANDOFF_OFFSET_DATA + + (i * sizeof(u32))); + *table_x32 = swab32(temp); + + if (!(i % 2)) + debug(" No.%d Addr 0x%08x: ", i, + *table_x32); + else + debug(" 0x%08x\n", *table_x32); + + table_x32++; + } + debug("\n}\n"); + } else { + debug("%s: Cannot find SOC64_HANDOFF_MAGIC_BOOT ", __func__); + debug("at addr 0x%p\n", (u32 *)handoff_address); + return -EPERM; + } + } + + return 0; +} diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c deleted file mode 100644 index d10fb5e454..0000000000 --- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016-2018 Intel Corporation - * - */ - -#include -#include -#include -#include - -static void sysmgr_pinmux_handoff_read(void *handoff_address, - const u32 **table, - unsigned int *table_len) -{ - unsigned int handoff_entry = (swab32(readl(handoff_address + - SOC64_HANDOFF_OFFSET_LENGTH)) - - SOC64_HANDOFF_OFFSET_DATA) / - sizeof(unsigned int); - unsigned int handoff_chunk[handoff_entry], temp, i; - - if (swab32(readl(SOC64_HANDOFF_MUX)) == SOC64_HANDOFF_MAGIC_MUX) { - /* using handoff from Quartus tools if exists */ - for (i = 0; i < handoff_entry; i++) { - temp = readl(handoff_address + - SOC64_HANDOFF_OFFSET_DATA + (i * 4)); - handoff_chunk[i] = swab32(temp); - } - *table = handoff_chunk; - *table_len = ARRAY_SIZE(handoff_chunk); - } -} - -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_MUX, table, - table_len); -} - -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_IOCTL, table, - table_len); -} - -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_FPGA, table, - table_len); -} - -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_DELAY, table, - table_len); -} From 3aef59f28083e2e3bd0c7ad91230f573123ec848 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 17:16:49 +0800 Subject: [PATCH 08/11] arm: socfpga: Move Stratix10 and Agilex clock manager common code Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim Signed-off-by: Tien Fong Chee Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++--- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ .../arm/mach-socfpga/include/mach/clock_manager.h | 1 + .../include/mach/clock_manager_arria10.h | 2 -- .../include/mach/clock_manager_gen5.h | 1 - .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - 7 files changed, 13 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index f0b15f770c..be426a5cfb 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -4,12 +4,13 @@ */ #include +#include +#include +#include +#include #include #include #include -#include -#include -#include DECLARE_GLOBAL_DATA_PTR; @@ -63,6 +64,14 @@ int set_cpu_clk_info(void) return 0; } +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); +} +#endif + #ifndef CONFIG_SPL_BUILD static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 6377f2ce3b..e035c09aae 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void) return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK); } -u32 cm_get_qspi_controller_clk_hz(void) -{ - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); -} - void cm_print_clock_quick_summary(void) { printf("MPU %10d kHz\n", diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index e060e5754e..4b4f0749db 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void) return clock; } -unsigned int cm_get_qspi_controller_clk_hz(void) -{ - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); -} - unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..9cf22375e3 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void); +unsigned int cm_get_qspi_controller_clk_hz(void); #endif #if defined(CONFIG_TARGET_SOCFPGA_GEN5) diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index 11ddee5cb6..798d3741bd 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -70,8 +70,6 @@ int cm_basic_init(const void *blob); unsigned int cm_get_l4_sp_clk_hz(void); unsigned long cm_get_mpu_clk_hz(void); -unsigned int cm_get_qspi_controller_clk_hz(void); - #endif /* __ASSEMBLY__ */ #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h index 5c9abe619b..4cc1268b4c 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h @@ -100,7 +100,6 @@ unsigned long cm_get_mpu_clk_hz(void); unsigned long cm_get_sdram_clk_hz(void); unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); -unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); const unsigned int cm_get_osc_clk_hz(const int osc); const unsigned int cm_get_f2s_per_ref_clk_hz(void); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index cb7923baef..98c3bf1b03 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void); unsigned long cm_get_sdram_clk_hz(void); unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); -unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); struct cm_config { From 404a98b0a49853e02ea342f6873b38702dd122c7 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 17:16:50 +0800 Subject: [PATCH 09/11] arm: socfpga: Changed to store QSPI reference clock in kHz Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/clock_manager.c | 32 +++++++++++++++++-- .../mach-socfpga/include/mach/clock_manager.h | 4 +++ .../include/mach/system_manager_soc64.h | 16 +++++++++- arch/arm/mach-socfpga/mailbox_s10.c | 17 +++++----- 4 files changed, 58 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index be426a5cfb..9e645a4253 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -65,10 +65,38 @@ int set_cpu_clk_info(void) } #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int cm_set_qspi_controller_clk_hz(u32 clk_hz) +{ + u32 reg; + u32 clk_khz; + + /* + * Store QSPI ref clock and set into sysmgr boot register. + * Only clock freq in kHz degree is accepted due to limited bits[27:0] + * is reserved for storing the QSPI clock freq into boot scratch cold0 + * register. + */ + if (clk_hz < 1000) + return -EINVAL; + + clk_khz = clk_hz / 1000; + printf("QSPI: Reference clock at %d kHz\n", clk_khz); + + reg = (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) & + ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK); + + writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + + return 0; +} + unsigned int cm_get_qspi_controller_clk_hz(void) { - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + return (readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD0) & + SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000; } #endif diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 9cf22375e3..2f9b471af3 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -13,6 +13,10 @@ void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void); unsigned int cm_get_qspi_controller_clk_hz(void); + +#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +int cm_set_qspi_controller_clk_hz(u32 clk_hz); +#endif #endif #if defined(CONFIG_TARGET_SOCFPGA_GEN5) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/* + * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 7dcdae8136..101af23855 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -5,14 +5,15 @@ */ #include -#include -#include -#include -#include +#include #include #include +#include +#include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -384,10 +385,10 @@ int mbox_qspi_open(void) if (ret) goto error; - /* We are getting QSPI ref clock and set into sysmgr boot register */ - printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); - writel(resp_buf[0], - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + /* Store QSPI controller ref clock frequency */ + ret = cm_set_qspi_controller_clk_hz(resp_buf[0]); + if (ret) + goto error; return 0; From cdca9860705291de736d40ddc52acba2daaec106 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 23:56:37 +0800 Subject: [PATCH 10/11] arm: socfpga: Enable FIT signature with crc32 for SOC64 devices Add signature with crc32 value for all images in binman node for FIT image in device tree. And, enable FIT signature checking for Stratix10 and Agilex ATF and VAB sdmmc boot. Signed-off-by: Siew Chin Lim --- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 30 ++++++++++++++++++---- configs/socfpga_agilex_atf_defconfig | 4 +++ configs/socfpga_agilex_vab_defconfig | 4 +++ configs/socfpga_stratix10_atf_defconfig | 4 +++ 4 files changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 4b30473743..84b91e8df0 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -29,10 +29,12 @@ arch = "arm64"; compression = "none"; load = <0x00200000>; - uboot_blob: blob-ext { filename = "u-boot-nodtb.bin"; }; + hash { + algo = "crc32"; + }; }; atf { @@ -43,20 +45,24 @@ compression = "none"; load = <0x00001000>; entry = <0x00001000>; - atf_blob: blob-ext { filename = "bl31.bin"; }; + hash { + algo = "crc32"; + }; }; fdt { description = "U-Boot SoC64 flat device-tree"; type = "flat_dt"; compression = "none"; - uboot_fdt_blob: blob-ext { filename = "u-boot.dtb"; }; + hash { + algo = "crc32"; + }; }; }; @@ -67,6 +73,11 @@ firmware = "atf"; loadables = "uboot"; fdt = "fdt"; + signature { + algo = "crc32"; + key-name-hint = "dev"; + sign-images = "atf", "fdt", "uboot"; + }; }; }; }; @@ -87,10 +98,12 @@ compression = "none"; load = <0x4080000>; entry = <0x4080000>; - kernel_blob: blob-ext { filename = "Image"; }; + hash { + algo = "crc32"; + }; }; fdt { @@ -98,10 +111,12 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - kernel_fdt_blob: blob-ext { filename = "linux.dtb"; }; + hash { + algo = "crc32"; + }; }; }; @@ -111,6 +126,11 @@ description = "Intel SoC64 FPGA"; kernel = "kernel"; fdt = "fdt"; + signature { + algo = "crc32"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; }; }; }; diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 7adda02b00..e5b7f4b52a 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -14,6 +14,10 @@ CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index bca663ed61..fac9cf72e5 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -15,6 +15,10 @@ CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 8dbb7424ba..7466025bc0 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -14,6 +14,10 @@ CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set From 96fe4f6485e92ed9da464c96c5f536698c5ee66d Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Thu, 25 Mar 2021 14:07:45 +0800 Subject: [PATCH 11/11] arm: socfpga: smc: Add function to get usercode Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/smc_api.h | 1 + arch/arm/mach-socfpga/smc_api.c | 17 +++++++++++++++++ include/linux/intel-smc.h | 18 ++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/smc_api.h b/arch/arm/mach-socfpga/include/mach/smc_api.h index bbefdd8dd9..6b5b7eadc6 100644 --- a/arch/arm/mach-socfpga/include/mach/smc_api.h +++ b/arch/arm/mach-socfpga/include/mach/smc_api.h @@ -9,5 +9,6 @@ int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len); int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); +int smc_get_usercode(u32 *usercode); #endif /* _SMC_API_H_ */ diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index 085daba162..8ffc7a472b 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -54,3 +54,20 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, return (int)resp[0]; } + +int smc_get_usercode(u32 *usercode) +{ + int ret; + u64 resp; + + if (!usercode) + return -EINVAL; + + ret = invoke_smc(INTEL_SIP_SMC_GET_USERCODE, NULL, 0, + &resp, 1); + + if (ret == INTEL_SIP_SMC_STATUS_OK) + *usercode = (u32)resp; + + return ret; +} diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index 68d62be417..a54eff43ad 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -518,4 +518,22 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) #define INTEL_SIP_SMC_MBOX_SEND_CMD \ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) +/* + * Request INTEL_SIP_SMC_GET_USERCODE + * + * Send mailbox command to get usercode from SDM + * + * Call register usage: + * a0 INTEL_SIP_SMC_GET_USERCODE + * a1-7 not used. + * + * Return status + * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR + * a1 User code + * a2-3 not used. + */ +#define INTEL_SIP_SMC_FUNCID_GET_USERCODE 61 +#define INTEL_SIP_SMC_GET_USERCODE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_GET_USERCODE) + #endif