Merge branch 'master' of git://www.denx.de/git/u-boot
This commit is contained in:
Shinya Kuribayashi
42
include/asm-sh/cpu_sh3.h
Normal file
42
include/asm-sh/cpu_sh3.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_CPU_SH3_H_
|
||||
#define _ASM_CPU_SH3_H_
|
||||
|
||||
/* cache control */
|
||||
#define CCR_CACHE_STOP 0x00000008
|
||||
#define CCR_CACHE_ENABLE 0x00000005
|
||||
#define CCR_CACHE_ICI 0x00000008
|
||||
|
||||
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
|
||||
#define CACHE_OC_WAY_SHIFT 13
|
||||
#define CACHE_OC_NUM_ENTRIES 256
|
||||
#define CACHE_OC_ENTRY_SHIFT 4
|
||||
|
||||
#if defined(CONFIG_CPU_SH7710)
|
||||
#include <asm/cpu_sh7710.h>
|
||||
#elif defined(CONFIG_CPU_SH7720)
|
||||
#include <asm/cpu_sh7720.h>
|
||||
#else
|
||||
#error "Unknown SH3 variant"
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_CPU_SH3_H_ */
|
||||
64
include/asm-sh/cpu_sh7710.h
Normal file
64
include/asm-sh/cpu_sh7710.h
Normal file
@@ -0,0 +1,64 @@
|
||||
#ifndef _ASM_CPU_SH7710_H_
|
||||
#define _ASM_CPU_SH7710_H_
|
||||
|
||||
#define CACHE_OC_NUM_WAYS 4
|
||||
#define CCR_CACHE_INIT 0x0000000D
|
||||
|
||||
/* MMU and Cache control */
|
||||
#define MMUCR 0xFFFFFFE0
|
||||
#define CCR 0xFFFFFFEC
|
||||
|
||||
/* PFC */
|
||||
#define PACR 0xA4050100
|
||||
#define PBCR 0xA4050102
|
||||
#define PCCR 0xA4050104
|
||||
#define PETCR 0xA4050106
|
||||
|
||||
/* Port Data Registers */
|
||||
#define PADR 0xA4050120
|
||||
#define PBDR 0xA4050122
|
||||
#define PCDR 0xA4050124
|
||||
|
||||
/* BSC */
|
||||
#define CMNCR 0xA4FD0000
|
||||
#define CS0BCR 0xA4FD0004
|
||||
#define CS2BCR 0xA4FD0008
|
||||
#define CS3BCR 0xA4FD000C
|
||||
#define CS4BCR 0xA4FD0010
|
||||
#define CS5ABCR 0xA4FD0014
|
||||
#define CS5BBCR 0xA4FD0018
|
||||
#define CS6ABCR 0xA4FD001C
|
||||
#define CS6BBCR 0xA4FD0020
|
||||
#define CS0WCR 0xA4FD0024
|
||||
#define CS2WCR 0xA4FD0028
|
||||
#define CS3WCR 0xA4FD002C
|
||||
#define CS4WCR 0xA4FD0030
|
||||
#define CS5AWCR 0xA4FD0034
|
||||
#define CS5BWCR 0xA4FD0038
|
||||
#define CS6AWCR 0xA4FD003C
|
||||
#define CS6BWCR 0xA4FD0040
|
||||
|
||||
/* SDRAM controller */
|
||||
#define SDCR 0xA4FD0044
|
||||
#define RTCSR 0xA4FD0048
|
||||
#define RTCNT 0xA4FD004C
|
||||
#define RTCOR 0xA4FD0050
|
||||
|
||||
/* SCIF */
|
||||
#define SCSMR_0 0xA4400000
|
||||
#define SCIF0_BASE SCSMR_0
|
||||
#define SCSMR_0 0xA4410000
|
||||
#define SCIF1_BASE SCSMR_1
|
||||
|
||||
/* Timer */
|
||||
#define TSTR0 0xA412FE92
|
||||
#define TSTR TSTR0
|
||||
#define TCNT0 0xa412FE98
|
||||
#define TCR0 0xa412FE9C
|
||||
|
||||
/* On chip oscillator circuits */
|
||||
#define FRQCR 0xA415FF80
|
||||
#define WTCNT 0xA415FF84
|
||||
#define WTCSR 0xA415FF86
|
||||
|
||||
#endif /* _ASM_CPU_SH7710_H_ */
|
||||
207
include/asm-sh/cpu_sh7720.h
Normal file
207
include/asm-sh/cpu_sh7720.h
Normal file
@@ -0,0 +1,207 @@
|
||||
/*
|
||||
* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* SH7720 Internal I/O register
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_CPU_SH7720_H_
|
||||
#define _ASM_CPU_SH7720_H_
|
||||
|
||||
#define CACHE_OC_NUM_WAYS 4
|
||||
#define CCR_CACHE_INIT 0x0000000B
|
||||
|
||||
/* EXP */
|
||||
#define TRA 0xFFFFFFD0
|
||||
#define EXPEVT 0xFFFFFFD4
|
||||
#define INTEVT 0xFFFFFFD8
|
||||
|
||||
/* MMU */
|
||||
#define MMUCR 0xFFFFFFE0
|
||||
#define PTEH 0xFFFFFFF0
|
||||
#define PTEL 0xFFFFFFF4
|
||||
#define TTB 0xFFFFFFF8
|
||||
|
||||
/* CACHE */
|
||||
#define CCR 0xFFFFFFEC
|
||||
|
||||
/* INTC */
|
||||
#define IPRF 0xA4080000
|
||||
#define IPRG 0xA4080002
|
||||
#define IPRH 0xA4080004
|
||||
#define IPRI 0xA4080006
|
||||
#define IPRJ 0xA4080008
|
||||
#define IRR5 0xA4080020
|
||||
#define IRR6 0xA4080022
|
||||
#define IRR7 0xA4080024
|
||||
#define IRR8 0xA4080026
|
||||
#define IRR9 0xA4080028
|
||||
#define IRR0 0xA4140004
|
||||
#define IRR1 0xA4140006
|
||||
#define IRR2 0xA4140008
|
||||
#define IRR3 0xA414000A
|
||||
#define IRR4 0xA414000C
|
||||
#define ICR1 0xA4140010
|
||||
#define ICR2 0xA4140012
|
||||
#define PINTER 0xA4140014
|
||||
#define IPRC 0xA4140016
|
||||
#define IPRD 0xA4140018
|
||||
#define IPRE 0xA414001A
|
||||
#define ICR0 0xA414FEE0
|
||||
#define IPRA 0xA414FEE2
|
||||
#define IPRB 0xA414FEE4
|
||||
|
||||
/* BSC */
|
||||
#define BSC_BASE 0xA4FD0000
|
||||
#define CMNCR (BSC_BASE + 0x00)
|
||||
#define CS0BCR (BSC_BASE + 0x04)
|
||||
#define CS2BCR (BSC_BASE + 0x08)
|
||||
#define CS3BCR (BSC_BASE + 0x0C)
|
||||
#define CS4BCR (BSC_BASE + 0x10)
|
||||
#define CS5ABCR (BSC_BASE + 0x14)
|
||||
#define CS5BBCR (BSC_BASE + 0x18)
|
||||
#define CS6ABCR (BSC_BASE + 0x1C)
|
||||
#define CS6BBCR (BSC_BASE + 0x20)
|
||||
#define CS0WCR (BSC_BASE + 0x24)
|
||||
#define CS2WCR (BSC_BASE + 0x28)
|
||||
#define CS3WCR (BSC_BASE + 0x2C)
|
||||
#define CS4WCR (BSC_BASE + 0x30)
|
||||
#define CS5AWCR (BSC_BASE + 0x34)
|
||||
#define CS5BWCR (BSC_BASE + 0x38)
|
||||
#define CS6AWCR (BSC_BASE + 0x3C)
|
||||
#define CS6BWCR (BSC_BASE + 0x40)
|
||||
#define SDCR (BSC_BASE + 0x44)
|
||||
#define RTCSR (BSC_BASE + 0x48)
|
||||
#define RTCNR (BSC_BASE + 0x4C)
|
||||
#define RTCOR (BSC_BASE + 0x50)
|
||||
#define SDMR2 (BSC_BASE + 0x4000)
|
||||
#define SDMR3 (BSC_BASE + 0x5000)
|
||||
|
||||
/* DMAC */
|
||||
|
||||
/* CPG */
|
||||
#define UCLKCR 0xA40A0008
|
||||
#define FRQCR 0xA415FF80
|
||||
|
||||
/* LOW POWER MODE */
|
||||
|
||||
/* TMU */
|
||||
#define TMU_BASE 0xA412FE90
|
||||
#define TSTR (TMU_BASE + 0x02)
|
||||
#define TCOR0 (TMU_BASE + 0x04)
|
||||
#define TCNT0 (TMU_BASE + 0x08)
|
||||
#define TCR0 (TMU_BASE + 0x0C)
|
||||
#define TCOR1 (TMU_BASE + 0x10)
|
||||
#define TCNT1 (TMU_BASE + 0x14)
|
||||
#define TCR1 (TMU_BASE + 0x18)
|
||||
#define TCOR2 (TMU_BASE + 0x1C)
|
||||
#define TCNT2 (TMU_BASE + 0x20)
|
||||
#define TCR2 (TMU_BASE + 0x24)
|
||||
|
||||
/* TPU */
|
||||
#define TPU_BASE 0xA4480000
|
||||
#define TPU_TSTR (TPU_BASE + 0x00)
|
||||
#define TPU_TCR0 (TPU_BASE + 0x10)
|
||||
#define TPU_TMDR0 (TPU_BASE + 0x14)
|
||||
#define TPU_TIOR0 (TPU_BASE + 0x18)
|
||||
#define TPU_TIER0 (TPU_BASE + 0x1C)
|
||||
#define TPU_TSR0 (TPU_BASE + 0x20)
|
||||
#define TPU_TCNT0 (TPU_BASE + 0x24)
|
||||
#define TPU_TGRA0 (TPU_BASE + 0x28)
|
||||
#define TPU_TGRB0 (TPU_BASE + 0x2C)
|
||||
#define TPU_TGRC0 (TPU_BASE + 0x30)
|
||||
#define TPU_TGRD0 (TPU_BASE + 0x34)
|
||||
#define TPU_TCR1 (TPU_BASE + 0x50)
|
||||
#define TPU_TMDR1 (TPU_BASE + 0x54)
|
||||
#define TPU_TIOR1 (TPU_BASE + 0x58)
|
||||
#define TPU_TIER1 (TPU_BASE + 0x5C)
|
||||
#define TPU_TSR1 (TPU_BASE + 0x60)
|
||||
#define TPU_TCNT1 (TPU_BASE + 0x64)
|
||||
#define TPU_TGRA1 (TPU_BASE + 0x68)
|
||||
#define TPU_TGRB1 (TPU_BASE + 0x6C)
|
||||
#define TPU_TGRC1 (TPU_BASE + 0x70)
|
||||
#define TPU_TGRD1 (TPU_BASE + 0x74)
|
||||
#define TPU_TCR2 (TPU_BASE + 0x90)
|
||||
#define TPU_TMDR2 (TPU_BASE + 0x94)
|
||||
#define TPU_TIOR2 (TPU_BASE + 0x98)
|
||||
#define TPU_TIER2 (TPU_BASE + 0x9C)
|
||||
#define TPU_TSR2 (TPU_BASE + 0xB0)
|
||||
#define TPU_TCNT2 (TPU_BASE + 0xB4)
|
||||
#define TPU_TGRA2 (TPU_BASE + 0xB8)
|
||||
#define TPU_TGRB2 (TPU_BASE + 0xBC)
|
||||
#define TPU_TGRC2 (TPU_BASE + 0xC0)
|
||||
#define TPU_TGRD2 (TPU_BASE + 0xC4)
|
||||
#define TPU_TCR3 (TPU_BASE + 0xD0)
|
||||
#define TPU_TMDR3 (TPU_BASE + 0xD4)
|
||||
#define TPU_TIOR3 (TPU_BASE + 0xD8)
|
||||
#define TPU_TIER3 (TPU_BASE + 0xDC)
|
||||
#define TPU_TSR3 (TPU_BASE + 0xE0)
|
||||
#define TPU_TCNT3 (TPU_BASE + 0xE4)
|
||||
#define TPU_TGRA3 (TPU_BASE + 0xE8)
|
||||
#define TPU_TGRB3 (TPU_BASE + 0xEC)
|
||||
#define TPU_TGRC3 (TPU_BASE + 0xF0)
|
||||
#define TPU_TGRD3 (TPU_BASE + 0xF4)
|
||||
|
||||
/* CMT */
|
||||
|
||||
/* SIOF */
|
||||
|
||||
/* SCIF */
|
||||
#define SCIF0_BASE 0xA4430000
|
||||
|
||||
/* SIM */
|
||||
|
||||
/* IrDA */
|
||||
|
||||
/* IIC */
|
||||
|
||||
/* LCDC */
|
||||
|
||||
/* USBF */
|
||||
|
||||
/* MMCIF */
|
||||
|
||||
/* PFC */
|
||||
#define PFC_BASE 0xA4050100
|
||||
#define PACR (PFC_BASE + 0x00)
|
||||
#define PBCR (PFC_BASE + 0x02)
|
||||
#define PCCR (PFC_BASE + 0x04)
|
||||
#define PDCR (PFC_BASE + 0x06)
|
||||
#define PECR (PFC_BASE + 0x08)
|
||||
#define PFCR (PFC_BASE + 0x0A)
|
||||
#define PGCR (PFC_BASE + 0x0C)
|
||||
#define PHCR (PFC_BASE + 0x0E)
|
||||
#define PJCR (PFC_BASE + 0x10)
|
||||
#define PKCR (PFC_BASE + 0x12)
|
||||
#define PLCR (PFC_BASE + 0x14)
|
||||
#define PMCR (PFC_BASE + 0x16)
|
||||
#define PPCR (PFC_BASE + 0x18)
|
||||
#define PRCR (PFC_BASE + 0x1A)
|
||||
#define PSCR (PFC_BASE + 0x1C)
|
||||
#define PTCR (PFC_BASE + 0x1E)
|
||||
#define PUCR (PFC_BASE + 0x20)
|
||||
#define PVCR (PFC_BASE + 0x22)
|
||||
#define PSELA (PFC_BASE + 0x24)
|
||||
#define PSELB (PFC_BASE + 0x26)
|
||||
#define PSELC (PFC_BASE + 0x28)
|
||||
#define PSELD (PFC_BASE + 0x2A)
|
||||
|
||||
/* I/O Port */
|
||||
|
||||
/* H-UDI */
|
||||
|
||||
#endif /* _ASM_CPU_SH7720_H_ */
|
||||
@@ -227,5 +227,32 @@ out:
|
||||
static inline void sync(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Given a physical address and a length, return a virtual address
|
||||
* that can be used to access the memory range with the caching
|
||||
* properties specified by "flags".
|
||||
*/
|
||||
typedef unsigned long phys_addr_t;
|
||||
|
||||
#define MAP_NOCACHE (0)
|
||||
#define MAP_WRCOMBINE (0)
|
||||
#define MAP_WRBACK (0)
|
||||
#define MAP_WRTHROUGH (0)
|
||||
|
||||
static inline void *
|
||||
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
|
||||
{
|
||||
return (void *)paddr;
|
||||
}
|
||||
|
||||
/*
|
||||
* Take down a mapping set up by map_physmem().
|
||||
*/
|
||||
static inline void unmap_physmem(void *vaddr, unsigned long flags)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_SH_IO_H */
|
||||
|
||||
134
include/configs/ms7720se.h
Normal file
134
include/configs/ms7720se.h
Normal file
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Configuation settings for the Hitachi Solution Engine 7720
|
||||
*
|
||||
* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __MS7720SE_H
|
||||
#define __MS7720SE_H
|
||||
|
||||
#undef DEBUG
|
||||
#define CONFIG_SH 1
|
||||
#define CONFIG_SH3 1
|
||||
#define CONFIG_CPU_SH7720 1
|
||||
#define CONFIG_MS7720SE 1
|
||||
|
||||
#define CONFIG_CMD_FLASH
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_PCMCIA
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CFG_CMD_PCMCIA 0x01
|
||||
#define CFG_CMD_IDE 0x02
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
|
||||
CFG_CMD_IDE|CFG_CMD_PCMCIA) & \
|
||||
~(CFG_CMD_FPGA))
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTARGS "console=ttySC0,115200"
|
||||
#define CONFIG_BOOTFILE /boot/zImage
|
||||
#define CONFIG_LOADADDR 0x8E000000
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* MEMORY */
|
||||
#define MS7720SE_SDRAM_BASE 0x8C000000
|
||||
#define MS7720SE_FLASH_BASE_1 0xA0000000
|
||||
#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
|
||||
#define CFG_PBSIZE 256 /* Buffer size for Console output */
|
||||
#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
|
||||
/* Buffer size for Boot Arguments passed to kernel */
|
||||
#define CFG_BARGSIZE 512
|
||||
/* List of legal baudrate settings for this board */
|
||||
#define CFG_BAUDRATE_TABLE { 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CFG_SCIF_CONSOLE 1
|
||||
#define CONFIG_CONS_SCIF0 1
|
||||
|
||||
#define CFG_MEMTEST_START MS7720SE_SDRAM_BASE
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
|
||||
|
||||
#define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE
|
||||
#define CFG_SDRAM_SIZE (64 * 1024 * 1024)
|
||||
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024)
|
||||
#define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1
|
||||
#define CFG_MONITOR_LEN (128 * 1024)
|
||||
#define CFG_MALLOC_LEN (256 * 1024)
|
||||
#define CFG_GBL_DATA_SIZE 256
|
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
|
||||
/* FLASH */
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#undef CFG_FLASH_QUIET_TEST
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 150
|
||||
#define CFG_MAX_FLASH_BANKS 1
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_FLASH_ERASE_TOUT 120000
|
||||
#define CFG_FLASH_WRITE_TOUT 500
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
|
||||
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
|
||||
|
||||
/* PCMCIA */
|
||||
#define CONFIG_IDE_PCMCIA 1
|
||||
#define CONFIG_MARUBUN_PCCARD 1
|
||||
#define CONFIG_PCMCIA_SLOT_A 1
|
||||
#define CFG_IDE_MAXDEVICE 1
|
||||
#define CFG_MARUBUN_MRSHPC 0xb83fffe0
|
||||
#define CFG_MARUBUN_MW1 0xb8400000
|
||||
#define CFG_MARUBUN_MW2 0xb8500000
|
||||
#define CFG_MARUBUN_IO 0xb8600000
|
||||
|
||||
#define CFG_PIO_MODE 1
|
||||
#define CFG_IDE_MAXBUS 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CFG_ATA_BASE_ADDR CFG_MARUBUN_IO /* base address */
|
||||
#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
|
||||
#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
|
||||
#define CFG_ATA_REG_OFFSET 0 /* reg offset */
|
||||
#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
|
||||
|
||||
#endif /* __MS7720SE_H */
|
||||
@@ -185,7 +185,7 @@
|
||||
|
||||
/* SCFR1 System Clock Frequency Register 1
|
||||
*/
|
||||
#define SCFR1_IPS_DIV 0x2
|
||||
#define SCFR1_IPS_DIV 0x4
|
||||
#define SCFR1_IPS_DIV_MASK 0x03800000
|
||||
#define SCFR1_IPS_DIV_SHIFT 23
|
||||
|
||||
|
||||
Reference in New Issue
Block a user