Merge branch 'master' of git://git.denx.de/u-boot-sh
- RZ/A1 addition. - Old board removal.
This commit is contained in:
Tom Rini
@@ -1,133 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuation settings for the Renesas Solutions ECOVEC board
|
||||
*
|
||||
* Copyright (C) 2009 - 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
*/
|
||||
|
||||
#ifndef __ECOVEC_H
|
||||
#define __ECOVEC_H
|
||||
|
||||
/*
|
||||
* Address Interface BusWidth
|
||||
*-----------------------------------------
|
||||
* 0x0000_0000 U-Boot 16bit
|
||||
* 0x0004_0000 Linux romImage 16bit
|
||||
* 0x0014_0000 MTD for Linux 16bit
|
||||
* 0x0400_0000 Internal I/O 16/32bit
|
||||
* 0x0800_0000 DRAM 32bit
|
||||
* 0x1800_0000 MFI 16bit
|
||||
*/
|
||||
|
||||
#define CONFIG_CPU_SH7724 1
|
||||
|
||||
#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
|
||||
#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED0 100000
|
||||
#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED1 100000
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 41666666
|
||||
|
||||
/* Ether */
|
||||
#define CONFIG_SH_ETHER_USE_PORT (0)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
|
||||
#define CONFIG_PHY_SMSC 1
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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||||
|
||||
/* USB / R8A66597 */
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#define CONFIG_USB_R8A66597_HCD
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#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
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||||
#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
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#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
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#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
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||||
#define CONFIG_SUPERH_ON_CHIP_R8A66597
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/* undef to save memory */
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||||
/* Monitor Command Prompt */
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||||
/* Buffer size for Console output */
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||||
#define CONFIG_SYS_PBSIZE 256
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||||
/* List of legal baudrate settings for this board */
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||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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||||
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||||
/* SCIF */
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#define CONFIG_SCIF 1
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||||
#define CONFIG_CONS_SCIF0 1
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||||
|
||||
/* Suppress display of console information at boot */
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||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE (0x88000000)
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||||
#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
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||||
/* Enable alternate, more extensive, memory test */
|
||||
/* Scratch address used by the alternate memory test */
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
|
||||
/* Enable temporary baudrate change while serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
/* FLASH */
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BASE (0xA0000000)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
/* Timeout for Flash erase operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash write operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
|
||||
/* Timeout for Flash set sector lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
|
||||
/* Timeout for Flash clear lock bit operations (in ms) */
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
|
||||
/*
|
||||
* Use hardware flash sectors protection instead
|
||||
* of U-Boot software protection
|
||||
*/
|
||||
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
|
||||
/* Monitor size */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
/* Size of DRAM reserved for malloc() use */
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* Board Clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 41666666
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
|
||||
#endif /* __ECOVEC_H */
|
||||
53
include/configs/grpeach.h
Normal file
53
include/configs/grpeach.h
Normal file
@@ -0,0 +1,53 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration settings for the Renesas GRPEACH board
|
||||
*
|
||||
* Copyright (C) 2017-2019 Renesas Electronics
|
||||
*/
|
||||
|
||||
#ifndef __GRPEACH_H
|
||||
#define __GRPEACH_H
|
||||
|
||||
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
|
||||
/* Serial Console */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Miscellaneous */
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
|
||||
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x20000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
|
||||
#define CONFIG_SYS_LOAD_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_OFFSET 0xc0000
|
||||
|
||||
/* Malloc */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
|
||||
/* Kernel Boot */
|
||||
#define CONFIG_BOOTARGS "ignore_loglevel"
|
||||
|
||||
/* Network interface */
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
#endif /* __GRPEACH_H */
|
||||
@@ -1,128 +0,0 @@
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||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuation settings for the Renesas Technology R0P7785LC0011RL board
|
||||
*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*/
|
||||
|
||||
#ifndef __SH7785LCR_H
|
||||
#define __SH7785LCR_H
|
||||
|
||||
#define CONFIG_CPU_SH7785 1
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootdevice=0:1\0" \
|
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"usbload=usb reset;usbboot;usb stop;bootm\0"
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* MEMORY */
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
/* 0x40000000 - 0x47FFFFFF does not use */
|
||||
#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
|
||||
#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
|
||||
#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
|
||||
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
|
||||
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
|
||||
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
|
||||
#define SH7785LCR_USB_BASE (0xa6000000)
|
||||
#else
|
||||
#define SH7785LCR_SDRAM_BASE (0x08000000)
|
||||
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
|
||||
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
|
||||
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
|
||||
#define SH7785LCR_USB_BASE (0xb4000000)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_CONS_SCIF1 1
|
||||
#define CONFIG_SCIF_EXT_CLOCK 1
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
(SH7785LCR_SDRAM_SIZE) - \
|
||||
4 * 1024 * 1024)
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
|
||||
(0 * SH7785LCR_FLASH_BANK_SIZE) }
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
|
||||
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
/* R8A66597 */
|
||||
#define CONFIG_USB_R8A66597_HCD
|
||||
#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
|
||||
#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
|
||||
#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
|
||||
#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
|
||||
|
||||
/* PCI Controller */
|
||||
#define CONFIG_SH4_PCI
|
||||
#define CONFIG_SH7780_PCI
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define CONFIG_SH7780_PCI_LSR 0x1ff00001
|
||||
#define CONFIG_SH7780_PCI_LAR 0x5f000000
|
||||
#define CONFIG_SH7780_PCI_BAR 0x5f000000
|
||||
#else
|
||||
#define CONFIG_SH7780_PCI_LSR 0x07f00001
|
||||
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
|
||||
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
|
||||
#endif
|
||||
#define CONFIG_PCI_SCAN_SHOW 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
|
||||
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
|
||||
#else
|
||||
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
|
||||
#endif
|
||||
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* Board Clock */
|
||||
/* The SCIF used external clock. system clock only used timer. */
|
||||
#define CONFIG_SYS_CLK_FREQ 50000000
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
|
||||
#endif /* __SH7785LCR_H */
|
||||
112
include/dt-bindings/clock/r7s72100-clock.h
Normal file
112
include/dt-bindings/clock/r7s72100-clock.h
Normal file
@@ -0,0 +1,112 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
|
||||
#define __DT_BINDINGS_CLOCK_R7S72100_H__
|
||||
|
||||
#define R7S72100_CLK_PLL 0
|
||||
#define R7S72100_CLK_I 1
|
||||
#define R7S72100_CLK_G 2
|
||||
|
||||
/* MSTP2 */
|
||||
#define R7S72100_CLK_CORESIGHT 0
|
||||
|
||||
/* MSTP3 */
|
||||
#define R7S72100_CLK_IEBUS 7
|
||||
#define R7S72100_CLK_IRDA 6
|
||||
#define R7S72100_CLK_LIN0 5
|
||||
#define R7S72100_CLK_LIN1 4
|
||||
#define R7S72100_CLK_MTU2 3
|
||||
#define R7S72100_CLK_CAN 2
|
||||
#define R7S72100_CLK_ADCPWR 1
|
||||
#define R7S72100_CLK_PWM 0
|
||||
|
||||
/* MSTP4 */
|
||||
#define R7S72100_CLK_SCIF0 7
|
||||
#define R7S72100_CLK_SCIF1 6
|
||||
#define R7S72100_CLK_SCIF2 5
|
||||
#define R7S72100_CLK_SCIF3 4
|
||||
#define R7S72100_CLK_SCIF4 3
|
||||
#define R7S72100_CLK_SCIF5 2
|
||||
#define R7S72100_CLK_SCIF6 1
|
||||
#define R7S72100_CLK_SCIF7 0
|
||||
|
||||
/* MSTP5 */
|
||||
#define R7S72100_CLK_SCI0 7
|
||||
#define R7S72100_CLK_SCI1 6
|
||||
#define R7S72100_CLK_SG0 5
|
||||
#define R7S72100_CLK_SG1 4
|
||||
#define R7S72100_CLK_SG2 3
|
||||
#define R7S72100_CLK_SG3 2
|
||||
#define R7S72100_CLK_OSTM0 1
|
||||
#define R7S72100_CLK_OSTM1 0
|
||||
|
||||
/* MSTP6 */
|
||||
#define R7S72100_CLK_ADC 7
|
||||
#define R7S72100_CLK_CEU 6
|
||||
#define R7S72100_CLK_DOC0 5
|
||||
#define R7S72100_CLK_DOC1 4
|
||||
#define R7S72100_CLK_DRC0 3
|
||||
#define R7S72100_CLK_DRC1 2
|
||||
#define R7S72100_CLK_JCU 1
|
||||
#define R7S72100_CLK_RTC 0
|
||||
|
||||
/* MSTP7 */
|
||||
#define R7S72100_CLK_VDEC0 7
|
||||
#define R7S72100_CLK_VDEC1 6
|
||||
#define R7S72100_CLK_ETHER 4
|
||||
#define R7S72100_CLK_NAND 3
|
||||
#define R7S72100_CLK_USB0 1
|
||||
#define R7S72100_CLK_USB1 0
|
||||
|
||||
/* MSTP8 */
|
||||
#define R7S72100_CLK_IMR0 7
|
||||
#define R7S72100_CLK_IMR1 6
|
||||
#define R7S72100_CLK_IMRDISP 5
|
||||
#define R7S72100_CLK_MMCIF 4
|
||||
#define R7S72100_CLK_MLB 3
|
||||
#define R7S72100_CLK_ETHAVB 2
|
||||
#define R7S72100_CLK_SCUX 1
|
||||
|
||||
/* MSTP9 */
|
||||
#define R7S72100_CLK_I2C0 7
|
||||
#define R7S72100_CLK_I2C1 6
|
||||
#define R7S72100_CLK_I2C2 5
|
||||
#define R7S72100_CLK_I2C3 4
|
||||
#define R7S72100_CLK_SPIBSC0 3
|
||||
#define R7S72100_CLK_SPIBSC1 2
|
||||
#define R7S72100_CLK_VDC50 1 /* and LVDS */
|
||||
#define R7S72100_CLK_VDC51 0
|
||||
|
||||
/* MSTP10 */
|
||||
#define R7S72100_CLK_SPI0 7
|
||||
#define R7S72100_CLK_SPI1 6
|
||||
#define R7S72100_CLK_SPI2 5
|
||||
#define R7S72100_CLK_SPI3 4
|
||||
#define R7S72100_CLK_SPI4 3
|
||||
#define R7S72100_CLK_CDROM 2
|
||||
#define R7S72100_CLK_SPDIF 1
|
||||
#define R7S72100_CLK_RGPVG2 0
|
||||
|
||||
/* MSTP11 */
|
||||
#define R7S72100_CLK_SSI0 5
|
||||
#define R7S72100_CLK_SSI1 4
|
||||
#define R7S72100_CLK_SSI2 3
|
||||
#define R7S72100_CLK_SSI3 2
|
||||
#define R7S72100_CLK_SSI4 1
|
||||
#define R7S72100_CLK_SSI5 0
|
||||
|
||||
/* MSTP12 */
|
||||
#define R7S72100_CLK_SDHI00 3
|
||||
#define R7S72100_CLK_SDHI01 2
|
||||
#define R7S72100_CLK_SDHI10 1
|
||||
#define R7S72100_CLK_SDHI11 0
|
||||
|
||||
/* MSTP13 */
|
||||
#define R7S72100_CLK_PIX1 2
|
||||
#define R7S72100_CLK_PIX0 1
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
|
||||
18
include/dt-bindings/pinctrl/r7s72100-pinctrl.h
Normal file
18
include/dt-bindings/pinctrl/r7s72100-pinctrl.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Defines macros and constants for Renesas RZ/A1 pin controller pin
|
||||
* muxing functions.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
|
||||
#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
|
||||
|
||||
#define RZA1_PINS_PER_PORT 16
|
||||
|
||||
/*
|
||||
* Create the pin index from its bank and position numbers and store in
|
||||
* the upper 16 bits the alternate function identifier
|
||||
*/
|
||||
#define RZA1_PINMUX(b, p, f) \
|
||||
((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16))
|
||||
|
||||
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
|
||||
Reference in New Issue
Block a user