eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-sh

Browse Source 
- RZ/A1 addition.
- Old board removal.
This commit is contained in:
Tom Rini
2019-05-07 09:38:00 -04:00
parent 6984044d05 ba932bc846
commit 8d7f06bbbe
58 changed files with 1860 additions and 2164 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpio/Kconfig
View File

@@ -169,6 +169,12 @@ config RCAR_GPIO
help
This driver supports the GPIO banks on Renesas RCar SoCs.
config RZA1_GPIO
bool "Renesas RZ/A1 GPIO driver"
depends on DM_GPIO && RZA1
help
This driver supports the GPIO banks on Renesas RZ/A1 R7S72100 SoCs.
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
depends on DM_GPIO

1
drivers/gpio/Makefile
View File

@@ -27,6 +27,7 @@ obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_PCA9698) += pca9698.o
obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o
obj-$(CONFIG_S5P) += s5p_gpio.o
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o

134
drivers/gpio/gpio-rza1.c Normal file
View File

@@ -0,0 +1,134 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#define P(bank) (0x0000 + (bank) * 4)
#define PSR(bank) (0x0100 + (bank) * 4)
#define PPR(bank) (0x0200 + (bank) * 4)
#define PM(bank) (0x0300 + (bank) * 4)
#define PMC(bank) (0x0400 + (bank) * 4)
#define PFC(bank) (0x0500 + (bank) * 4)
#define PFCE(bank) (0x0600 + (bank) * 4)
#define PNOT(bank) (0x0700 + (bank) * 4)
#define PMSR(bank) (0x0800 + (bank) * 4)
#define PMCSR(bank) (0x0900 + (bank) * 4)
#define PFCAE(bank) (0x0A00 + (bank) * 4)
#define PIBC(bank) (0x4000 + (bank) * 4)
#define PBDC(bank) (0x4100 + (bank) * 4)
#define PIPC(bank) (0x4200 + (bank) * 4)
#define RZA1_MAX_GPIO_PER_BANK 16
DECLARE_GLOBAL_DATA_PTR;
struct r7s72100_gpio_priv {
void __iomem *regs;
int bank;
};
static int r7s72100_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
return !!(readw(priv->regs + PPR(priv->bank)) & BIT(offset));
}
static int r7s72100_gpio_set_value(struct udevice *dev, unsigned line,
int value)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
writel(BIT(line + 16) | (value ? BIT(line) : 0),
priv->regs + PSR(priv->bank));
return 0;
}
static void r7s72100_gpio_set_direction(struct udevice *dev, unsigned line,
bool output)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
writel(BIT(line + 16), priv->regs + PMCSR(priv->bank));
writel(BIT(line + 16) | (output ? 0 : BIT(line)),
priv->regs + PMSR(priv->bank));
clrsetbits_le16(priv->regs + PIBC(priv->bank), BIT(line),
output ? 0 : BIT(line));
}
static int r7s72100_gpio_direction_input(struct udevice *dev, unsigned offset)
{
r7s72100_gpio_set_direction(dev, offset, false);
return 0;
}
static int r7s72100_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
/* write GPIO value to output before selecting output mode of pin */
r7s72100_gpio_set_value(dev, offset, value);
r7s72100_gpio_set_direction(dev, offset, true);
return 0;
}
static int r7s72100_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
if (readw(priv->regs + PM(priv->bank)) & BIT(offset))
return GPIOF_INPUT;
else
return GPIOF_OUTPUT;
}
static const struct dm_gpio_ops r7s72100_gpio_ops = {
.direction_input = r7s72100_gpio_direction_input,
.direction_output = r7s72100_gpio_direction_output,
.get_value = r7s72100_gpio_get_value,
.set_value = r7s72100_gpio_set_value,
.get_function = r7s72100_gpio_get_function,
};
static int r7s72100_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct r7s72100_gpio_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
int node = dev_of_offset(dev);
int ret;
fdt_addr_t addr_base;
uc_priv->bank_name = dev->name;
dev = dev_get_parent(dev);
addr_base = devfdt_get_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (void __iomem *)addr_base;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
NULL, 3, 0, &args);
priv->bank = ret == 0 ? (args.args[1] / RZA1_MAX_GPIO_PER_BANK) : -1;
uc_priv->gpio_count = ret == 0 ? args.args[2] : RZA1_MAX_GPIO_PER_BANK;
return 0;
}
U_BOOT_DRIVER(r7s72100_gpio) = {
.name = "r7s72100-gpio",
.id = UCLASS_GPIO,
.ops = &r7s72100_gpio_ops,
.priv_auto_alloc_size = sizeof(struct r7s72100_gpio_priv),
.probe = r7s72100_gpio_probe,
};

11
drivers/net/sh_eth.c
View File

@@ -425,7 +425,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
#elif defined(CONFIG_RCAR_GEN2)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
@@ -806,9 +806,11 @@ static int sh_ether_probe(struct udevice *udev)
priv->iobase = pdata->iobase;
#if CONFIG_IS_ENABLED(CLK)
ret = clk_get_by_index(udev, 0, &priv->clk);
if (ret < 0)
return ret;
#endif
ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
if (!ret) {
@@ -843,9 +845,11 @@ static int sh_ether_probe(struct udevice *udev)
eth->port_info[eth->port].iobase =
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
if (ret)
goto err_mdio_register;
#endif
ret = sh_eth_phy_config(udev);
if (ret) {
@@ -856,7 +860,9 @@ static int sh_ether_probe(struct udevice *udev)
return 0;
err_phy_config:
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
#endif
err_mdio_register:
mdio_free(mdiodev);
return ret;
@@ -868,7 +874,9 @@ static int sh_ether_remove(struct udevice *udev)
struct sh_eth_dev *eth = &priv->shdev;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
#endif
free(port_info->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
@@ -917,6 +925,7 @@ int sh_ether_ofdata_to_platdata(struct udevice *dev)
}
static const struct udevice_id sh_ether_ids[] = {
{ .compatible = "renesas,ether-r7s72100" },
{ .compatible = "renesas,ether-r8a7790" },
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },

59
drivers/net/sh_eth.h
View File

@@ -228,6 +228,60 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMII_MII] = 0x0790,
};
static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
[EDSR] = 0x0000,
[EDMR] = 0x0400,
[EDTRR] = 0x0408,
[EDRRR] = 0x0410,
[EESR] = 0x0428,
[EESIPR] = 0x0430,
[TDLAR] = 0x0010,
[TDFAR] = 0x0014,
[TDFXR] = 0x0018,
[TDFFR] = 0x001c,
[RDLAR] = 0x0030,
[RDFAR] = 0x0034,
[RDFXR] = 0x0038,
[RDFFR] = 0x003c,
[TRSCER] = 0x0438,
[RMFCR] = 0x0440,
[TFTR] = 0x0448,
[FDR] = 0x0450,
[RMCR] = 0x0458,
[RPADIR] = 0x0460,
[FCFTR] = 0x0468,
[CSMR] = 0x04E4,
[ECMR] = 0x0500,
[ECSR] = 0x0510,
[ECSIPR] = 0x0518,
[PIR] = 0x0520,
[PSR] = 0x0528,
[PIPR] = 0x052c,
[RFLR] = 0x0508,
[APR] = 0x0554,
[MPR] = 0x0558,
[PFTCR] = 0x055c,
[PFRCR] = 0x0560,
[TPAUSER] = 0x0564,
[GECMR] = 0x05b0,
[BCULR] = 0x05b4,
[MAHR] = 0x05c0,
[MALR] = 0x05c8,
[TROCR] = 0x0700,
[CDCR] = 0x0708,
[LCCR] = 0x0710,
[CEFCR] = 0x0740,
[FRECR] = 0x0748,
[TSFRCR] = 0x0750,
[TLFRCR] = 0x0758,
[RFCR] = 0x0760,
[CERCR] = 0x0768,
[CEECR] = 0x0770,
[MAFCR] = 0x0778,
[RMII_MII] = 0x0790,
};
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
@@ -295,9 +349,6 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xfef00000
#endif
#elif defined(CONFIG_CPU_SH7724)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xA4600000
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
@@ -606,6 +657,8 @@ static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
#elif defined(SH_ETH_TYPE_RZ)
const u16 *reg_offset = sh_eth_offset_rz;
#else
#error
#endif

12
drivers/pinctrl/renesas/Kconfig
View File

@@ -3,6 +3,7 @@ if ARCH_RMOBILE
config PINCTRL_PFC
bool "Renesas pin control drivers"
depends on DM && ARCH_RMOBILE
default n if CPU_RZA1
help
Enable support for clock present on Renesas RCar SoCs.
@@ -116,4 +117,15 @@ config PINCTRL_PFC_R8A77995
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R7S72100
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
default y if CPU_RZA1
help
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
endif

1
drivers/pinctrl/renesas/Makefile
View File

@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o

146
drivers/pinctrl/renesas/pfc-r7s72100.c Normal file
View File

@@ -0,0 +1,146 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* R7S72100 processor support
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <linux/io.h>
#include <linux/err.h>
#define P(bank) (0x0000 + (bank) * 4)
#define PSR(bank) (0x0100 + (bank) * 4)
#define PPR(bank) (0x0200 + (bank) * 4)
#define PM(bank) (0x0300 + (bank) * 4)
#define PMC(bank) (0x0400 + (bank) * 4)
#define PFC(bank) (0x0500 + (bank) * 4)
#define PFCE(bank) (0x0600 + (bank) * 4)
#define PNOT(bank) (0x0700 + (bank) * 4)
#define PMSR(bank) (0x0800 + (bank) * 4)
#define PMCSR(bank) (0x0900 + (bank) * 4)
#define PFCAE(bank) (0x0A00 + (bank) * 4)
#define PIBC(bank) (0x4000 + (bank) * 4)
#define PBDC(bank) (0x4100 + (bank) * 4)
#define PIPC(bank) (0x4200 + (bank) * 4)
#define RZA1_PINS_PER_PORT 16
DECLARE_GLOBAL_DATA_PTR;
struct r7s72100_pfc_platdata {
void __iomem *base;
};
static void r7s72100_pfc_set_function(struct udevice *dev, u16 bank, u16 line,
u16 func, u16 inbuf, u16 bidir)
{
struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
clrsetbits_le16(plat->base + PFCAE(bank), BIT(line),
(func & BIT(2)) ? BIT(line) : 0);
clrsetbits_le16(plat->base + PFCE(bank), BIT(line),
(func & BIT(1)) ? BIT(line) : 0);
clrsetbits_le16(plat->base + PFC(bank), BIT(line),
(func & BIT(0)) ? BIT(line) : 0);
clrsetbits_le16(plat->base + PIBC(bank), BIT(line),
inbuf ? BIT(line) : 0);
clrsetbits_le16(plat->base + PBDC(bank), BIT(line),
bidir ? BIT(line) : 0);
setbits_le32(plat->base + PMCSR(bank), BIT(line + 16) | BIT(line));
setbits_le16(plat->base + PIPC(bank), BIT(line));
}
static int r7s72100_pfc_set_state(struct udevice *dev, struct udevice *config)
{
const void *blob = gd->fdt_blob;
int node = dev_of_offset(config);
u32 cells[32];
u16 bank, line, func;
int i, count, bidir;
count = fdtdec_get_int_array_count(blob, node, "pinmux",
cells, ARRAY_SIZE(cells));
if (count < 0) {
printf("%s: bad pinmux array %d\n", __func__, count);
return -EINVAL;
}
if (count > ARRAY_SIZE(cells)) {
printf("%s: unsupported pinmux array count %d\n",
__func__, count);
return -EINVAL;
}
for (i = 0 ; i < count; i++) {
func = (cells[i] >> 16) & 0xf;
if (func == 0 || func > 8) {
printf("Invalid cell %i in node %s!\n",
count, ofnode_get_name(dev_ofnode(config)));
continue;
}
func = (func - 1) & 0x7;
bank = (cells[i] / RZA1_PINS_PER_PORT) & 0xff;
line = cells[i] % RZA1_PINS_PER_PORT;
bidir = 0;
if (bank == 3 && line == 3 && func == 1)
bidir = 1;
r7s72100_pfc_set_function(dev, bank, line, func, 0, bidir);
}
return 0;
}
const struct pinctrl_ops r7s72100_pfc_ops = {
.set_state = r7s72100_pfc_set_state,
};
static int r7s72100_pfc_probe(struct udevice *dev)
{
struct r7s72100_pfc_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr_base;
ofnode node;
addr_base = devfdt_get_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = (void __iomem *)addr_base;
dev_for_each_subnode(node, dev) {
struct udevice *cdev;
if (!ofnode_read_bool(node, "gpio-controller"))
continue;
device_bind_driver_to_node(dev, "r7s72100-gpio",
ofnode_get_name(node),
node, &cdev);
}
return 0;
}
static const struct udevice_id r7s72100_pfc_match[] = {
{ .compatible = "renesas,r7s72100-ports" },
{}
};
U_BOOT_DRIVER(r7s72100_pfc) = {
.name = "r7s72100_pfc",
.id = UCLASS_PINCTRL,
.of_match = r7s72100_pfc_match,
.probe = r7s72100_pfc_probe,
.platdata_auto_alloc_size = sizeof(struct r7s72100_pfc_platdata),
.ops = &r7s72100_pfc_ops,
};

4
drivers/serial/serial_sh.c
View File

@@ -21,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
static int scif_rxfill(struct uart_port *port)
{
@@ -63,6 +62,9 @@ static void sh_serial_init_generic(struct uart_port *port)
sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(port, SCFCR);
sci_out(port, SCFCR, 0);
#if defined(CONFIG_RZA1)
sci_out(port, SCSPTR, 0x0003);
#endif
}
static void

24
drivers/serial/serial_sh.h
View File

@@ -107,11 +107,6 @@ struct uart_port {
# define SCSPTR5 0xa4050128
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7724)
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7734)
# define SCSPTR0 0xFFE40020
# define SCSPTR1 0xFFE41020
@@ -175,8 +170,7 @@ struct uart_port {
# define SCSCR_INIT(port) 0x3a
#endif
#elif defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
#elif defined(CONFIG_CPU_SH7786)
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
@@ -201,7 +195,7 @@ struct uart_port {
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
# endif
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7269)
#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
@@ -211,6 +205,7 @@ struct uart_port {
# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_CPU_SH7619)
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
@@ -252,12 +247,9 @@ struct uart_port {
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786) || \
defined(CONFIG_CPU_SHX3)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
#elif defined(CONFIG_CPU_SH7724)
#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
#else
#define SCI_CTRL_FLAGS_REIE 0
#endif
@@ -494,7 +486,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name)
#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
#elif defined(CONFIG_CPU_SH7723)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
@@ -549,8 +541,7 @@ SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
SCIF_FNS(SCLSR, 0x00, 0)
SCIF_FNS(DL, 0x00, 0) /* dummy */
#elif defined(CONFIG_CPU_SH7723) ||\
defined(CONFIG_CPU_SH7724)
#elif defined(CONFIG_CPU_SH7723)
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
@@ -594,7 +585,6 @@ SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
@@ -734,7 +724,6 @@ static inline int sci_rxd_in(struct uart_port *port)
*/
#if (defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)) && \
!defined(CONFIG_SH_SH2007)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
@@ -747,8 +736,7 @@ static inline int sci_rxd_in(struct uart_port *port)
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(CONFIG_CPU_SH7723) ||\
defined(CONFIG_CPU_SH7724)
#elif defined(CONFIG_CPU_SH7723)
static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
{
if (port->type == PORT_SCIF)

2
drivers/spi/Kconfig
View File

@@ -173,7 +173,7 @@ config PL022_SPI
config RENESAS_RPC_SPI
bool "Renesas RPC SPI driver"
depends on RCAR_GEN3
depends on RCAR_GEN3 || RZA1
imply SPI_FLASH_BAR
help
Enable the Renesas RPC SPI driver, used to access SPI NOR flash

12
drivers/spi/renesas_rpc_spi.c
View File

@@ -409,27 +409,30 @@ static int rpc_spi_probe(struct udevice *dev)
priv->regs = plat->regs;
priv->extr = plat->extr;
#if CONFIG_IS_ENABLED(CLK)
clk_enable(&priv->clk);
#endif
return 0;
}
static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
{
struct rpc_spi_platdata *plat = dev_get_platdata(bus);
struct rpc_spi_priv *priv = dev_get_priv(bus);
int ret;
plat->regs = dev_read_addr_index(bus, 0);
plat->extr = dev_read_addr_index(bus, 1);
#if CONFIG_IS_ENABLED(CLK)
struct rpc_spi_priv *priv = dev_get_priv(bus);
int ret;
ret = clk_get_by_index(bus, 0, &priv->clk);
if (ret < 0) {
printf("%s: Could not get clock for %s: %d\n",
__func__, bus->name, ret);
return ret;
}
#endif
plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
@@ -448,6 +451,7 @@ static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,rpc-r8a77965" },
{ .compatible = "renesas,rpc-r8a77970" },
{ .compatible = "renesas,rpc-r8a77995" },
{ .compatible = "renesas,rpc-r7s72100" },
{ }
};

7
drivers/timer/Kconfig
View File

@@ -110,6 +110,13 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
config RENESAS_OSTM_TIMER
bool "Renesas RZ/A1 R7S72100 OSTM Timer"
depends on TIMER
help
Enables support for the Renesas OSTM Timer driver.
This timer is present on Renesas RZ/A1 R7S72100 SoCs.
config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer"
depends on X86_TSC_TIMER

1
drivers/timer/Makefile
View File

@@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o

92
drivers/timer/ostm_timer.c Normal file
View File

@@ -0,0 +1,92 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Renesas RZ/A1 R7S72100 OSTM Timer driver
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <timer.h>
#define OSTM_CMP 0x00
#define OSTM_CNT 0x04
#define OSTM_TE 0x10
#define OSTM_TS 0x14
#define OSTM_TT 0x18
#define OSTM_CTL 0x20
#define OSTM_CTL_D BIT(1)
DECLARE_GLOBAL_DATA_PTR;
struct ostm_priv {
fdt_addr_t regs;
};
static int ostm_get_count(struct udevice *dev, u64 *count)
{
struct ostm_priv *priv = dev_get_priv(dev);
*count = timer_conv_64(readl(priv->regs + OSTM_CNT));
return 0;
}
static int ostm_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ostm_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
uc_priv->clock_rate = clk_get_rate(&clk);
clk_free(&clk);
#else
uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
#endif
readb(priv->regs + OSTM_CTL);
writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
setbits_8(priv->regs + OSTM_TT, BIT(0));
writel(0xffffffff, priv->regs + OSTM_CMP);
setbits_8(priv->regs + OSTM_TS, BIT(0));
return 0;
}
static int ostm_ofdata_to_platdata(struct udevice *dev)
{
struct ostm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr(dev);
return 0;
}
static const struct timer_ops ostm_ops = {
.get_count = ostm_get_count,
};
static const struct udevice_id ostm_ids[] = {
{ .compatible = "renesas,ostm" },
{}
};
U_BOOT_DRIVER(ostm_timer) = {
.name = "ostm-timer",
.id = UCLASS_TIMER,
.ops = &ostm_ops,
.probe = ostm_probe,
.of_match = ostm_ids,
.ofdata_to_platdata = ostm_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct ostm_priv),
};