Convert CONFIG_MXC_GPIO to Kconfig

This converts the following to Kconfig:
   CONFIG_MXC_GPIO

Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
2018-02-04 09:32:43 -06:00
committed by Tom Rini
parent f1754f0810
commit 8bbff6a70e
41 changed files with 20 additions and 55 deletions

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@@ -33,7 +33,6 @@
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_OCOTP

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@@ -101,7 +101,6 @@
#define CONFIG_DFU_MMC
/* Miscellaneous commands */
#define CONFIG_MXC_GPIO
/* Framebuffer and LCD */
#define CONFIG_VIDEO_IPUV3

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@@ -169,11 +169,6 @@
#define CONFIG_CONS_INDEX 1
#define CONFIG_MXC_UART_BASE UART1_BASE
/*
* GPIO
*/
#define CONFIG_MXC_GPIO
/*
* NOR
*/

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@@ -89,7 +89,6 @@
#define CONFIG_DFU_MMC
/* Miscellaneous commands */
#define CONFIG_MXC_GPIO
/* Framebuffer and LCD */
#define CONFIG_VIDEO_IPUV3

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@@ -64,9 +64,6 @@
#define CONFIG_MXC_OCOTP
#endif
/* GPIO */
#define CONFIG_MXC_GPIO
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC

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@@ -48,7 +48,6 @@
#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */
#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
/*
* UART (console)

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@@ -50,7 +50,6 @@
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_OCOTP

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@@ -131,11 +131,6 @@
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
/*
* GPIO
*/
#define CONFIG_MXC_GPIO
/*
* U-Boot general configuration
*/

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@@ -147,8 +147,6 @@
/* EET platform additions */
#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET
#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI

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@@ -8,8 +8,6 @@
#ifndef __M53EVK_CONFIG_H__
#define __M53EVK_CONFIG_H__
#define CONFIG_MXC_GPIO
#include <asm/arch/imx-regs.h>
#define CONFIG_REVISION_TAG

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@@ -12,7 +12,6 @@
/* High Level Configuration Options */
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_TIMER_RATE 32768

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@@ -38,7 +38,6 @@
#define CONFIG_MXC_SPI 1
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_MXC_GPIO
/* PMIC Controller */
#define CONFIG_POWER

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@@ -46,7 +46,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI

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@@ -42,7 +42,6 @@
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
/*
* PMIC Configs

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@@ -36,7 +36,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_MXC_GPIO
/*
* SPI Configs

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@@ -23,8 +23,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI

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@@ -24,7 +24,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
#define CONFIG_MXC_UART_BASE UART2_BASE

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@@ -23,8 +23,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE

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@@ -23,7 +23,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
#define CONFIG_MXC_UART

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@@ -29,7 +29,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
#define CONFIG_MXC_UART

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@@ -23,8 +23,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE

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@@ -69,9 +69,6 @@
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_MAXARGS 32
/* GPIO */
#define CONFIG_MXC_GPIO
/* MMC */
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_ESDHC

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@@ -27,8 +27,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE

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@@ -45,9 +45,6 @@
#ifndef CONFIG_SYS_DCACHE_OFF
#endif
/* GPIO */
#define CONFIG_MXC_GPIO
/* UART */
#define CONFIG_MXC_UART

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@@ -43,7 +43,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_MXC_GPIO
/*
* SPI Configs

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@@ -12,7 +12,6 @@
#define __CONFIG_H
#define CONFIG_SYS_FSL_CLK
#define CONFIG_MXC_GPIO
#include <asm/arch/imx-regs.h>

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@@ -44,7 +44,6 @@
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
/* PMIC Controller */
#define CONFIG_POWER
@@ -76,8 +75,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_MXC_GPIO
#define CONFIG_NET_RETRY_COUNT 100

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@@ -37,11 +37,6 @@
* Hardware drivers
*/
/*
* GPIO
*/
#define CONFIG_MXC_GPIO
/*
* Serial
*/