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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Browse Source 
fsl-qoriq: Fixes and updates on fsl-layerscape
mpc85xx: fixes and code cleanup
This commit is contained in:
Tom Rini
2022-04-27 09:19:41 -04:00
parent 24df831cd4 182d45ddff
commit 8b2b125e95
85 changed files with 610 additions and 421 deletions
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4
include/configs/P1010RDB.h
View File

@@ -81,6 +81,10 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
#else
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_TPL_PAD_TO 0x20000

3
include/configs/T102xRDB.h
View File

@@ -36,6 +36,9 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

3
include/configs/T104xRDB.h
View File

@@ -40,6 +40,9 @@
#endif
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

3
include/configs/T208xQDS.h
View File

@@ -44,6 +44,9 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

3
include/configs/T208xRDB.h
View File

@@ -39,6 +39,9 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif
#ifdef CONFIG_SPIFLASH

1
include/configs/ls1012a2g5rdb.h
View File

@@ -19,7 +19,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x800000\0" \
"scriptaddr=0x80000000\0" \

2
include/configs/ls1012afrdm.h
View File

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#ifndef __LS1012ARDB_H__
@@ -21,7 +22,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"fdt_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"fdtheader_addr_r=0x80100000\0" \

1
include/configs/ls1012afrwy.h
View File

@@ -35,7 +35,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernel_size_sd=0x16000\0" \
"kernelhdr_size_sd=0x10\0" \

1
include/configs/ls1012aqds.h
View File

@@ -89,7 +89,6 @@
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x600000\0" \
"scriptaddr=0x80000000\0" \

1
include/configs/ls1012ardb.h
View File

@@ -44,7 +44,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x600000\0" \
"scriptaddr=0x80000000\0" \

1
include/configs/ls1021atsn.h
View File

@@ -114,7 +114,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"kernelheader_addr=0x60800000\0" \
"scriptaddr=0x80000000\0" \

4
include/configs/ls1021atwr.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#ifndef __CONFIG_H
@@ -209,7 +209,6 @@
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
"cma=64M@0x0-0xb0000000\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x65000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
@@ -266,7 +265,6 @@
"bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
"cma=64M@0x0-0xb0000000\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"kernelheader_addr=0x60800000\0" \
"scriptaddr=0x80000000\0" \

3
include/configs/ls1028aqds.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#ifndef __LS1028A_QDS_H
@@ -68,7 +68,6 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

3
include/configs/ls1028ardb.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#ifndef __LS1028A_RDB_H
@@ -64,7 +64,6 @@
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"bootm_size=0x10000000\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

1
include/configs/ls1043a_common.h
View File

@@ -173,7 +173,6 @@
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

1
include/configs/ls1046a_common.h
View File

@@ -165,7 +165,6 @@
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"bootm_size=0x10000000\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \

2
include/configs/ls1088ardb.h
View File

@@ -271,7 +271,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x1000000\0" \
"kernel_addr_sd=0x8000\0" \
"kernelhdr_addr_sd=0x3000\0" \
@@ -340,7 +339,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x1000000\0" \
"kernel_addr_sd=0x8000\0" \
"kernelhdr_addr_sd=0x3000\0" \

2
include/configs/ls2080ardb.h
View File

@@ -323,7 +323,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x581000000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x800000\0" \
@@ -386,7 +385,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x581000000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x600000\0" \

1
include/configs/lx2160a_common.h
View File

@@ -164,7 +164,6 @@
"ramdisk_size=0x2000000\0" \
"fdt_high=0xa0000000\0" \
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_start=0x1000000\0" \
"kernelheader_start=0x600000\0" \
"scriptaddr=0x80000000\0" \

48
include/configs/p1_p2_rdb_pc.h
View File

@@ -21,6 +21,9 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
@@ -46,6 +49,9 @@
#define __SW_BOOT_SD 0x24
#define __SW_BOOT_NAND 0x44
#define __SW_BOOT_PCIE 0x74
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -57,9 +63,13 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28
#define __SW_BOOT_SD 0x68 /* or 0x18 */
#define __SW_BOOT_SD 0x68
#define __SW_BOOT_SD2 0x18
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
@@ -111,6 +121,10 @@
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
#else
#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#endif
#endif /* not CONFIG_TPL_BUILD */
#define CONFIG_SPL_PAD_TO 0x20000
@@ -320,7 +334,7 @@
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000"
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
@@ -339,6 +353,10 @@
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
#ifndef __VSCFW_ADDR
#define __VSCFW_ADDR ""
#endif
/*
* Config the L2 Cache as L2 SRAM
*/
@@ -526,28 +544,28 @@
#ifdef __SW_BOOT_NOR
#define __NOR_RST_CMD \
norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_SPI
#define __SPI_RST_CMD \
spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_SD
#define __SD_RST_CMD \
sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_NAND
#define __NAND_RST_CMD \
nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#ifdef __SW_BOOT_PCIE
#define __PCIE_RST_CMD \
pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
i2c mw 18 3 __SW_BOOT_MASK 1; reset
pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \
i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -574,9 +592,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
"nandbootaddr=100000\0" \
"nandfdtaddr=80000\0" \
"ramdisk_size=120000\0" \
"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
__stringify(__VSCFW_ADDR)"\0" \
__VSCFW_ADDR \
"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \
__stringify(__NOR_RST_CMD)"\0" \
__stringify(__SPI_RST_CMD)"\0" \
__stringify(__SD_RST_CMD)"\0" \

1
include/fsl_esdhc.h
View File

@@ -76,6 +76,7 @@
/* eSDHC control register */
#define ESDHCCTL 0x0002e40c
#define ESDHCCTL_SNOOP (0x00000040)
#define ESDHCCTL_PCS (0x00080000)
#define ESDHCCTL_FAF (0x00040000)