Merge branch 'master' of git://git.denx.de/u-boot-imx
This commit is contained in:
Wolfgang Denk
@@ -68,10 +68,13 @@
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS0 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@@ -89,6 +92,7 @@
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_NAND
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#define CONFIG_BOOTDELAY 3
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@@ -174,4 +178,13 @@
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_JFFS2_DEV "nor0"
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/*
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* NAND flash
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*/
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#define CONFIG_NAND_MXC
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#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_MXC_NAND_HWECC
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#endif /* __CONFIG_H */
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@@ -65,10 +65,12 @@
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS0 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@@ -69,12 +69,13 @@
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 2
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783 1
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/* MC13783 connected to CSPI2 and SS2 */
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#define CONFIG_MC13783_SPI_BUS 1
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#define CONFIG_MC13783_SPI_CS 2
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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@@ -54,12 +54,27 @@
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/* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define BOARD_LATE_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_SYS_MX51_UART1
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/*
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* SPI Configs
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* */
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#define CONFIG_CMD_SPI
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#define CONFIG_MXC_SPI
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 0
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 2500000
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#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH)
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/*
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* MMC Configs
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* */
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@@ -54,6 +54,17 @@
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#define CONFIG_MX31_GPIO
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#define CONFIG_MXC_SPI
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13783
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#define CONFIG_FSL_PMIC
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 100000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
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/* FPGA */
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#define CONFIG_QONG_FPGA 1
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#define CONFIG_FPGA_BASE (CS1_BASE)
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@@ -73,7 +84,7 @@
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_CMD_BMP
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#define CONFIG_BMP_16BPP
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#define CONFIG_DISPLAY_VBEST_VGG322403
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#define CONFIG_DISPLAY_COM57H5M10XRC
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/*
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* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
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@@ -98,6 +109,9 @@
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_DATE
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#define BOARD_LATE_INIT
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/*
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* You can compile in a MAC address and your custom net settings by using
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128
include/fsl_pmic.h
Normal file
128
include/fsl_pmic.h
Normal file
@@ -0,0 +1,128 @@
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/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_PMIC_H__
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#define __FSL_PMIC_H__
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/*
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* The registers of different PMIC has the same meaning
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* but the bit positions of the fields can differ or
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* some fields has a meaning only on some devices.
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* You have to check with the internal SPI bitmap
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* (see Freescale Documentation) to set the registers
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* for the device you are using
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*/
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enum {
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REG_INT_STATUS0 = 0,
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REG_INT_MASK0,
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REG_INT_SENSE0,
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REG_INT_STATUS1,
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REG_INT_MASK1,
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REG_INT_SENSE1,
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REG_PU_MODE_S,
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REG_IDENTIFICATION,
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REG_UNUSED0,
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REG_ACC0,
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REG_ACC1, /*10 */
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REG_UNUSED1,
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REG_UNUSED2,
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REG_POWER_CTL0,
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REG_POWER_CTL1,
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REG_POWER_CTL2,
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REG_REGEN_ASSIGN,
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REG_UNUSED3,
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REG_MEM_A,
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REG_MEM_B,
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REG_RTC_TIME, /*20 */
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REG_RTC_ALARM,
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REG_RTC_DAY,
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REG_RTC_DAY_ALARM,
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REG_SW_0,
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REG_SW_1,
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REG_SW_2,
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REG_SW_3,
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REG_SW_4,
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REG_SW_5,
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REG_SETTING_0, /*30 */
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REG_SETTING_1,
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REG_MODE_0,
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REG_MODE_1,
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REG_POWER_MISC,
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REG_UNUSED4,
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REG_UNUSED5,
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REG_UNUSED6,
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REG_UNUSED7,
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REG_UNUSED8,
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REG_UNUSED9, /*40 */
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REG_UNUSED10,
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REG_UNUSED11,
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REG_ADC0,
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REG_ADC1,
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REG_ADC2,
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REG_ADC3,
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REG_ADC4,
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REG_CHARGE,
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REG_USB0,
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REG_USB1, /*50 */
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REG_LED_CTL0,
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REG_LED_CTL1,
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REG_LED_CTL2,
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REG_LED_CTL3,
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REG_UNUSED12,
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REG_UNUSED13,
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REG_TRIM0,
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REG_TRIM1,
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REG_TEST0,
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REG_TEST1, /*60 */
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REG_TEST2,
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REG_TEST3,
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REG_TEST4,
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};
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/* REG_POWER_MISC */
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#define GPO1EN (1 << 6)
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#define GPO1STBY (1 << 7)
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#define GPO2EN (1 << 8)
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#define GPO2STBY (1 << 9)
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#define GPO3EN (1 << 10)
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#define GPO3STBY (1 << 11)
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#define GPO4EN (1 << 12)
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#define GPO4STBY (1 << 13)
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#define PWGT1SPIEN (1 << 15)
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#define PWGT2SPIEN (1 << 16)
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#define PWUP (1 << 21)
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/* Power Control 0 */
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#define COINCHEN (1 << 23)
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#define BATTDETEN (1 << 19)
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/* Interrupt status 1 */
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#define RTCRSTI (1 << 7)
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void pmic_show_pmic_info(void);
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void pmic_reg_write(u32 reg, u32 value);
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u32 pmic_reg_read(u32 reg);
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#endif
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160
include/mc13892.h
Normal file
160
include/mc13892.h
Normal file
@@ -0,0 +1,160 @@
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/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MC13892_H__
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#define __MC13892_H__
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/* REG_CHARGE */
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#define VCHRG0 0
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#define VCHRG1 (1 << 1)
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#define VCHRG2 (1 << 2)
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#define ICHRG0 (1 << 3)
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#define ICHRG1 (1 << 4)
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#define ICHRG2 (1 << 5)
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#define ICHRG3 (1 << 6)
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#define ICHRGTR0 (1 << 7)
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#define ICHRGTR1 (1 << 8)
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#define ICHRGTR2 (1 << 9)
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#define FETOVRD (1 << 10)
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#define FETCTRL (1 << 11)
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#define RVRSMODE (1 << 13)
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#define OVCTRL0 (1 << 15)
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#define OVCTRL1 (1 << 16)
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#define UCHEN (1 << 17)
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#define CHRGLEDEN (1 << 18)
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#define CHRGRAWPDEN (1 << 19)
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#define CHGRESTART (1 << 20)
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#define CHGAUTOB (1 << 21)
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#define CYCLB (1 << 22)
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#define CHGAUTOVIB (1 << 23)
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/* REG_SETTING_0/1 */
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#define VO_1_20V 0
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#define VO_1_30V 1
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#define VO_1_50V 2
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#define VO_1_80V 3
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#define VO_1_10V 4
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#define VO_2_00V 5
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#define VO_2_77V 6
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#define VO_2_40V 7
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#define VIOL 2
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#define VDIG 4
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#define VGEN 6
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/* SWxMode for Normal/Standby Mode */
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#define SWMODE_OFF_OFF 0
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#define SWMODE_PWM_OFF 1
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#define SWMODE_PWMPS_OFF 2
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#define SWMODE_PFM_OFF 3
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#define SWMODE_AUTO_OFF 4
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#define SWMODE_PWM_PWM 5
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#define SWMODE_PWM_AUTO 6
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#define SWMODE_AUTO_AUTO 8
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#define SWMODE_PWM_PWMPS 9
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#define SWMODE_PWMS_PWMPS 10
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#define SWMODE_PWMS_AUTO 11
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#define SWMODE_AUTO_PFM 12
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#define SWMODE_PWM_PFM 13
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#define SWMODE_PWMS_PFM 14
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#define SWMODE_PFM_PFM 15
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#define SWMODE_MASK 0x0F
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#define SWMODE1_SHIFT 0
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#define SWMODE2_SHIFT 10
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#define SWMODE3_SHIFT 0
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#define SWMODE4_SHIFT 8
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/* Fields in REG_SETTING_1 */
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#define VVIDEO_2_7 (0 << 2)
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#define VVIDEO_2_775 (1 << 2)
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#define VVIDEO_2_5 (2 << 2)
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#define VVIDEO_2_6 (3 << 2)
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#define VVIDEO_MASK (3 << 2)
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#define VAUDIO_2_3 (0 << 4)
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#define VAUDIO_2_5 (1 << 4)
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#define VAUDIO_2_775 (2 << 4)
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#define VAUDIO_3_0 (3 << 4)
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#define VAUDIO_MASK (3 << 4)
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#define VSD_1_8 (0 << 6)
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#define VSD_2_0 (1 << 6)
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#define VSD_2_6 (2 << 6)
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#define VSD_2_7 (3 << 6)
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#define VSD_2_8 (4 << 6)
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#define VSD_2_9 (5 << 6)
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#define VSD_3_0 (6 << 6)
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#define VSD_3_15 (7 << 6)
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#define VSD_MASK (7 << 6)
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#define VGEN1_1_2 0
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#define VGEN1_1_5 1
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#define VGEN1_2_775 2
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#define VGEN1_3_15 3
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#define VGEN1_MASK 3
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#define VGEN2_1_2 (0 << 6)
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#define VGEN2_1_5 (1 << 6)
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#define VGEN2_1_6 (2 << 6)
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#define VGEN2_1_8 (3 << 6)
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#define VGEN2_2_7 (4 << 6)
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#define VGEN2_2_8 (5 << 6)
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#define VGEN2_3_0 (6 << 6)
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#define VGEN2_3_15 (7 << 6)
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#define VGEN2_MASK (7 << 6)
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/* Fields in REG_SETTING_1 */
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#define VGEN3_1_8 (0 << 14)
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#define VGEN3_2_9 (1 << 14)
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#define VGEN3_MASK (1 << 14)
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#define VDIG_1_05 (0 << 4)
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#define VDIG_1_25 (1 << 4)
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#define VDIG_1_65 (2 << 4)
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#define VDIG_1_8 (3 << 4)
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#define VDIG_MASK (3 << 4)
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#define VCAM_2_5 (0 << 16)
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#define VCAM_2_6 (1 << 16)
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#define VCAM_2_75 (2 << 16)
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#define VCAM_3_0 (3 << 16)
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#define VCAM_MASK (3 << 16)
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/* Reg Mode 1 */
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#define VGEN3EN (1 << 0)
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#define VGEN3STBY (1 << 1)
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#define VGEN3MODE (1 << 2)
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#define VGEN3CONFIG (1 << 3)
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#define VCAMEN (1 << 6)
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#define VCAMSTBY (1 << 7)
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#define VCAMMODE (1 << 8)
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#define VCAMCONFIG (1 << 9)
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#define VVIDEOEN (1 << 12)
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#define VIDEOSTBY (1 << 13)
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#define VVIDEOMODE (1 << 14)
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#define VAUDIOEN (1 << 15)
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#define VAUDIOSTBY (1 << 16)
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#define VSDEN (1 << 18)
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#define VSDSTBY (1 << 19)
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#define VSDMODE (1 << 20)
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||||
#endif
|
||||
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