Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
@@ -78,6 +78,7 @@
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#ifdef CONFIG_MPC8349ITX
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#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
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#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
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#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
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#endif
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#define CONFIG_PCI
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@@ -141,7 +142,16 @@
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#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* SATA
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*/
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#ifdef CONFIG_SATA_SIL3114
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#define CONFIG_SYS_SATA_MAX_DEVICE 4
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#define CONFIG_LIBATA
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#define CONFIG_LBA48
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#endif
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@@ -449,9 +459,18 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SDRAM
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#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_FAT
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#endif
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#ifdef CONFIG_COMPACT_FLASH
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#endif
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#ifdef CONFIG_SATA_SIL3114
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#define CONFIG_CMD_SATA
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#define CONFIG_CMD_EXT2
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#endif
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#ifdef CONFIG_PCI
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@@ -49,6 +49,7 @@
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#else
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#define CONFIG_83XX_GENERIC_PCI 1
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#define CONFIG_83XX_GENERIC_PCIE 1
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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@@ -375,6 +376,26 @@
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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@@ -890,6 +890,8 @@
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#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
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#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
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#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
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#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
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#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
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/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
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*/
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@@ -535,6 +535,8 @@ extern int pci_hose_config_device(struct pci_controller *hose,
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pci_addr_t mem,
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unsigned long command);
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int pci_last_busno(void);
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#ifdef CONFIG_MPC824X
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extern void pci_mpc824x_init (struct pci_controller *hose);
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#endif
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