Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
@@ -90,7 +90,7 @@ static void show_eeprom(void)
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/* EEPROM tag ID, either CCID or NXID */
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#ifdef CONFIG_SYS_I2C_EEPROM_NXID
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printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
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be32_to_cpu(e.version));
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e.version);
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#else
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printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
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#endif
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@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
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#ifdef CONFIG_SYS_I2C_EEPROM_NXID
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printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
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be32_to_cpu(e.version));
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e.version);
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#else
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printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
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#endif
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@@ -17,6 +17,9 @@
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#include "../common/qixis.h"
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#include "ls1021aqds_qixis.h"
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#ifdef CONFIG_U_QE
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#include "../../../drivers/qe/qe.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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@@ -137,9 +140,8 @@ int board_early_init_f(void)
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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#ifdef CONFIG_TSEC_ENET
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out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
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out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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#endif
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#ifdef CONFIG_FSL_IFC
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@@ -230,6 +232,13 @@ int board_init(void)
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/* Set CCI-400 control override register to
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* enable barrier transaction */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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/*
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* Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
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* All transactions are treated as non-shareable
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*/
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out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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@@ -237,6 +246,11 @@ int board_init(void)
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fsl_serdes_init();
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config_serdes_mux();
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#endif
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#ifdef CONFIG_U_QE
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u_qe_init();
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#endif
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return 0;
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}
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@@ -17,6 +17,10 @@
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <fsl_sec.h>
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#ifdef CONFIG_U_QE
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#include "../../../drivers/qe/qe.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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@@ -251,11 +255,8 @@ int board_early_init_f(void)
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_TSEC_ENET
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out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
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out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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udelay(10);
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out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
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#endif
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#ifdef CONFIG_FSL_IFC
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@@ -263,9 +264,7 @@ int board_early_init_f(void)
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#endif
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#ifdef CONFIG_FSL_DCU_FB
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out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
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out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
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out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
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#endif
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return 0;
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@@ -273,11 +272,25 @@ int board_early_init_f(void)
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
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* All transactions are treated as non-shareable
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*/
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out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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config_serdes_mux();
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#endif
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#ifdef CONFIG_U_QE
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u_qe_init();
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#endif
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return 0;
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}
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