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* Patches by Yuli Barcohen, 13 Jul 2003:

Browse Source 
- Correct flash and JFFS2 support for MPC8260ADS
  - fix PVR values and clock generation for PowerQUICC II family
    (8270/8275/8280)

* Patch by Bernhard Kuhn, 08 Jul 2003:
  - add support for M68K targets

* Patch by Ken Chou, 3 Jul:
  - Fix PCI config table for A3000
  - Fix iobase for natsemi.c
    (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)

* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
This commit is contained in:
wdenk
2003-07-14 22:13:32 +00:00
parent 5702923e23
commit 8564acf936
40 changed files with 818 additions and 445 deletions
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6
post/memory.c
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@@ -146,7 +146,7 @@
* regions of RAM around each 1Mb boundary. For example, for 64Mb
* RAM the following areas are verified: 0x00000000-0x00000800,
* 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
* 0x04000000. If the test is run in power-fail mode, it verifies
* 0x04000000. If the test is run in slow-test mode, it verifies
* the whole RAM.
*/
@@ -460,9 +460,9 @@ int memory_post_test (int flags)
256 << 20 : bd->bi_memsize) - (1 << 20);
if (flags & POST_POWERFAIL) {
if (flags & POST_SLOWTEST) {
ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
} else { /* POST_POWERNORMAL */
} else { /* POST_NORMAL */
unsigned long i;