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MPC512x: use I/O accessors instead of pointer accesses

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This commit changes the MPC512x code to use I/O accessor calls (i.e.
out_*() and in_*()) instead of using deprecated pointer accesses.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
This commit is contained in:
Wolfgang Denk
2009-05-16 10:47:43 +02:00
parent 19dc7e1792
commit 843efb1192
9 changed files with 323 additions and 263 deletions
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26
cpu/mpc512x/cpu_init.c
View File

@@ -1,6 +1,6 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2007 DENX Software Engineering
* Copyright (C) 2007-2009 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -26,6 +26,8 @@
#include <common.h>
#include <mpc512x.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,30 +48,34 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
out_be32(&im->arbiter.acr,
(im->arbiter.acr & ~ACR_PIPE_DEP) |
(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
);
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
out_be32(im->arbiter.acr,
(im->arbiter.acr & ~(ACR_RPTCNT)) |
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
);
#endif
/* RSR - Reset Status Register - clear all status */
gd->reset_status = im->reset.rsr;
im->reset.rsr = ~(RSR_RES);
out_be32(&im->reset.rsr, ~RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
ips_div = im->clk.scfr[0];
ips_div = in_be32(&im->clk.scfr[0]);
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
im->clk.scfr[0] = ips_div;
out_be32(&im->clk.scfr[0], ips_div);
/*
* Enable Time Base/Decrementer
@@ -78,7 +84,7 @@ void cpu_init_f (volatile immap_t * im)
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
im->sysconf.spcr |= SPCR_TBEN;
setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
}
int cpu_init_r (void)

56
cpu/mpc512x/i2c.c
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2003 - 2007
* (C) Copyright 2003 - 2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -24,6 +24,7 @@
*/
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -32,8 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
#include <mpc512x.h>
#include <i2c.h>
#define immr ((immap_t *)CONFIG_SYS_IMMR)
/* by default set I2C bus 0 active */
static unsigned int bus_num = 0;
@@ -56,29 +55,24 @@ static int mpc_get_fdr(int);
static int mpc_reg_in (volatile u32 *reg)
{
int ret = *reg >> 24;
__asm__ __volatile__ ("eieio");
int ret = in_be32(reg) >> 24;
return ret;
}
static void mpc_reg_out (volatile u32 *reg, int val, int mask)
{
int tmp;
if (!mask) {
*reg = val << 24;
out_be32(reg, val << 24);
} else {
tmp = mpc_reg_in (reg);
*reg = ((tmp & ~mask) | (val & mask)) << 24;
clrsetbits_be32(reg, mask << 24, (val & mask) << 24);
}
__asm__ __volatile__ ("eieio");
return;
}
static int wait_for_bb (void)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int timeout = I2C_TIMEOUT;
int status;
@@ -101,7 +95,8 @@ static int wait_for_bb (void)
static int wait_for_pin (int *status)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int timeout = I2C_TIMEOUT;
*status = mpc_reg_in (&regs->msr);
@@ -122,7 +117,8 @@ static int wait_for_pin (int *status)
static int do_address (uchar chip, char rdwr_flag)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int status;
chip <<= 1;
@@ -147,7 +143,8 @@ static int do_address (uchar chip, char rdwr_flag)
static int send_bytes (uchar chip, char *buf, int len)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int wrcount;
int status;
@@ -170,7 +167,8 @@ static int send_bytes (uchar chip, char *buf, int len)
static int receive_bytes (uchar chip, char *buf, int len)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int dummy = 1;
int rdcount = 0;
int status;
@@ -208,9 +206,12 @@ static int receive_bytes (uchar chip, char *buf, int len)
void i2c_init (int speed, int saddr)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
int i;
for(i = 0; i < I2C_BUS_CNT; i++){
i2c512x_dev_t *regs = &immr->i2c.dev[i];
for (i = 0; i < I2C_BUS_CNT; i++){
volatile i2c512x_dev_t *regs = &im->i2c.dev[i];
mpc_reg_out (&regs->mcr, 0, 0);
/* Set clock */
@@ -223,10 +224,10 @@ void i2c_init (int speed, int saddr)
}
/* Disable interrupts */
immr->i2c.icr = 0;
out_be32(&im->i2c.icr, 0);
/* Turn off filters */
immr->i2c.mifr = 0;
return;
out_be32(&im->i2c.mifr, 0);
}
static int mpc_get_fdr (int speed)
@@ -281,7 +282,8 @@ static int mpc_get_fdr (int speed)
int i2c_probe (uchar chip)
{
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int i;
for (i = 0; i < I2C_RETRIES; i++) {
@@ -302,8 +304,9 @@ int i2c_probe (uchar chip)
int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
char xaddr[4];
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int ret = -1;
xaddr[0] = (addr >> 24) & 0xFF;
@@ -346,8 +349,9 @@ Done:
int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
char xaddr[4];
i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int ret = -1;
xaddr[0] = (addr >> 24) & 0xFF;

52
cpu/mpc512x/ide.c
View File

@@ -23,47 +23,46 @@
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_IDE_RESET)
void ide_set_reset (int idereset)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
debug ("ide_set_reset(%d)\n", idereset);
if (idereset) {
out_be32(&im->pata.pata_ata_control, 0);
} else {
out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
}
udelay(100);
}
void init_ide_reset (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
debug ("init_ide_reset\n");
/*
* Clear the reset bit to reset the interface
* cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
*/
immr->pata.pata_ata_control = 0;
udelay(100);
ide_set_reset(1);
/* Assert the reset bit to enable the interface */
immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
udelay(100);
}
ide_set_reset(0);
void ide_set_reset (int idereset)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
debug ("ide_set_reset(%d)\n", idereset);
if (idereset) {
immr->pata.pata_ata_control = 0;
udelay(100);
} else {
immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
udelay(100);
}
}
#define CALC_TIMING(t) (t + period - 1) / period
int ide_preinit (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
long t;
const struct {
short t0;
@@ -92,13 +91,13 @@ int ide_preinit (void)
u8 field3;
u8 field4;
}bytes;
}cfg;
} cfg;
debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
(u32)&immr->pata);
(u32)&im->pata);
/* Set the reset bit to 1 to enable the interface */
immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
ide_set_reset(0);
/* Init timings : we use PIO mode 0 timings */
t = 1000000000 / gd->ips_clk; /* period in ns */
@@ -107,19 +106,20 @@ int ide_preinit (void)
cfg.bytes.field3 = (pio_specs.t1 + t) / t;
cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
immr->pata.pata_time1 = cfg.config;
out_be32(&im->pata.pata_time1, cfg.config);
cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
cfg.bytes.field3 = 1;
cfg.bytes.field4 = (pio_specs.t4 + t) / t;
immr->pata.pata_time2 = cfg.config;
out_be32(&im->pata.pata_time2, cfg.config);
cfg.config = immr->pata.pata_time3;
cfg.config = in_be32(&im->pata.pata_time3);
cfg.bytes.field1 = (pio_specs.t9 + t) / t;
immr->pata.pata_time3 = cfg.config;
out_be32(&im->pata.pata_time3, cfg.config);
debug ("PATA preinit complete.\n");
return 0;

6
cpu/mpc512x/iopin.c
View File

@@ -23,7 +23,7 @@
#include <common.h>
#include <linux/types.h>
#include <asm/immap_512x.h>
#include <asm/io.h>
void iopin_initialize(iopin_t *ioregs_init, int len)
{
@@ -40,9 +40,9 @@ void iopin_initialize(iopin_t *ioregs_init, int len)
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
reg[j] |= ioregs_init[i].val;
setbits_be32(reg + j, ioregs_init[i].val);
else
reg[j] = ioregs_init[i].val;
out_be32 (reg + j, ioregs_init[i].val);
}
}
return;

71
cpu/mpc512x/pci.c
View File

@@ -1,5 +1,6 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
* Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,6 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/global_data.h>
#include <pci.h>
@@ -46,7 +48,7 @@ static struct pci_controller pci_hose;
void
pci_init_board(void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile law512x_t *pci_law;
volatile pot512x_t *pci_pot;
volatile pcictrl512x_t *pci_ctrl;
@@ -58,24 +60,29 @@ pci_init_board(void)
struct pci_controller *hose;
/* Set PCI divider for 33MHz */
reg32 = immr->clk.scfr[0];
reg32 = im->clk.scfr[0];
reg32 &= ~(SCFR1_PCI_DIV_MASK);
reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
immr->clk.scfr[0] = reg32;
im->clk.scfr[0] = reg32;
pci_law = immr->sysconf.pcilaw;
pci_pot = immr->ios.pot;
pci_ctrl = &immr->pci_ctrl;
pci_conf = &immr->pci_conf;
clrsetbits_be32(&im->clk.scfr[0],
SCFR1_PCI_DIV_MASK,
SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
);
pci_law = im->sysconf.pcilaw;
pci_pot = im->ios.pot;
pci_ctrl = &im->pci_ctrl;
pci_conf = &im->pci_conf;
hose = &pci_hose;
/*
* Release PCI RST Output signal
*/
pci_ctrl->gcr = 0;
out_be32(&pci_ctrl->gcr, 0);
udelay(2000);
pci_ctrl->gcr = 1;
out_be32(&pci_ctrl->gcr, 1);
/* We need to wait at least a 1sec based on PCI specs */
for (i = 0; i < 1000; i++)
@@ -84,30 +91,39 @@ pci_init_board(void)
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
/*
* Configure PCI Outbound Translation Windows
*/
/* PCI mem space - prefetch */
pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
out_be32(&pci_pot[0].potar,
(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
out_be32(&pci_pot[0].pobar,
(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
out_be32(&pci_pot[0].pocmr,
POCMR_EN | POCMR_PRE | POCMR_CM_256M);
/* PCI IO space */
pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
out_be32(&pci_pot[1].potar,
(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
out_be32(&pci_pot[1].pobar,
(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
out_be32(&pci_pot[1].pocmr,
POCMR_EN | POCMR_IO | POCMR_CM_16M);
/* PCI mmio - non-prefetch mem space */
pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
out_be32(&pci_pot[2].potar,
(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
out_be32(&pci_pot[2].pobar,
(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
out_be32(&pci_pot[2].pocmr,
POCMR_EN | POCMR_CM_256M);
/*
* Configure PCI Inbound Translation Windows
@@ -115,11 +131,12 @@ pci_init_board(void)
/* we need RAM mapped to PCI space for the devices to
* access main memory */
pci_ctrl[0].pitar1 = 0x0;
pci_ctrl[0].pibar1 = 0x0;
pci_ctrl[0].piebar1 = 0x0;
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
out_be32(&pci_ctrl[0].pitar1, 0x0);
out_be32(&pci_ctrl[0].pibar1, 0x0);
out_be32(&pci_ctrl[0].piebar1, 0x0);
out_be32(&pci_ctrl[0].piwar1,
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
hose->first_busno = 0;
hose->last_busno = 0xff;

64
cpu/mpc512x/serial.c
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2000 - 2007
* (C) Copyright 2000 - 2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -30,6 +30,8 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,21 +42,21 @@ static void fifo_init (volatile psc512x_t *psc)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
/* reset Rx & Tx fifo slice */
psc->rfcmd = PSC_FIFO_RESET_SLICE;
psc->tfcmd = PSC_FIFO_RESET_SLICE;
out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
/* disable Tx & Rx FIFO interrupts */
psc->rfintmask = 0;
psc->tfintmask = 0;
out_be32(&psc->rfintmask, 0);
out_be32(&psc->tfintmask, 0);
psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
/* enable Tx & Rx FIFO slice */
psc->rfcmd = PSC_FIFO_ENABLE_SLICE;
psc->tfcmd = PSC_FIFO_ENABLE_SLICE;
out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE;
out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
__asm__ volatile ("sync");
}
@@ -68,38 +70,38 @@ int serial_init(void)
fifo_init (psc);
/* set MR register to point to MR1 */
psc->command = PSC_SEL_MODE_REG_1;
out_8(&psc->command, PSC_SEL_MODE_REG_1);
/* disable Tx/Rx */
psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE;
out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
/* choose the prescaler by 16 for the Tx/Rx clock generation */
psc->psc_clock_select = 0xdd00;
out_be16(&psc->psc_clock_select, 0xdd00);
/* switch to UART mode */
psc->sicr = 0;
out_be32(&psc->sicr, 0);
/* mode register points to mr1 */
/* configure parity, bit length and so on in mode register 1*/
psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
/* now, mode register points to mr2 */
psc->mode = PSC_MODE_1_STOPBIT;
out_8(&psc->mode, PSC_MODE_1_STOPBIT);
/* calculate dividor for setting PSC CTUR and CTLR registers */
baseclk = (gd->ips_clk + 8) / 16;
div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
psc->ctur = (div >> 8) & 0xff;
out_8(&psc->ctur, (div >> 8) & 0xff);
/* set baudrate */
psc->ctlr = div & 0xff;
out_8(&psc->ctlr, div & 0xff);
/* disable all interrupts */
psc->psc_imr = 0;
out_be16(&psc->psc_imr, 0);
/* reset and enable Rx/Tx */
psc->command = PSC_RST_RX;
psc->command = PSC_RST_TX;
psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
out_8(&psc->command, PSC_RST_RX);
out_8(&psc->command, PSC_RST_TX);
out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
return 0;
}
@@ -113,7 +115,7 @@ void serial_putc (const char c)
serial_putc ('\r');
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
;
psc->tfdata_8 = c;
@@ -125,7 +127,7 @@ void serial_putc_raw (const char c)
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
;
psc->tfdata_8 = c;
@@ -145,7 +147,7 @@ int serial_getc (void)
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for a character to arrive. */
while (psc->rfstat & PSC_FIFO_EMPTY)
while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
;
return psc->rfdata_8;
@@ -156,7 +158,7 @@ int serial_tstc (void)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
return !(psc->rfstat & PSC_FIFO_EMPTY);
return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
}
void serial_setbrg (void)
@@ -168,8 +170,8 @@ void serial_setbrg (void)
baseclk = (gd->csb_clk + 8) / 16;
div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
psc->ctur = (div >> 8) & 0xFF;
psc->ctlr = div & 0xff; /* set baudrate */
out_8(&psc->ctur, (div >> 8) & 0xFF);
out_8(&psc->ctlr, div & 0xff); /* set baudrate */
}
void serial_setrts(int s)
@@ -179,11 +181,11 @@ void serial_setrts(int s)
if (s) {
/* Assert RTS (become LOW) */
psc->op1 = 0x1;
out_8(&psc->op1, 0x1);
}
else {
/* Negate RTS (become HIGH) */
psc->op0 = 0x1;
out_8(&psc->op0, 0x1);
}
}
@@ -192,6 +194,6 @@ int serial_getcts(void)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
return (psc->ip & 0x1) ? 0 : 1;
return (in_8(&psc->ip) & 0x1) ? 0 : 1;
}
#endif /* CONFIG_PSC_CONSOLE */

23
cpu/mpc512x/speed.c
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2000-2007
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
@@ -28,6 +28,7 @@
#include <common.h>
#include <mpc512x.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -75,29 +76,37 @@ int get_clocks (void)
u32 csb_clk;
u32 ips_clk;
u32 pci_clk;
u32 reg;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
reg = in_be32(&im->sysconf.immrbar);
if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
reg = in_be32(&im->clk.spmr);
spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
spll = ref_clk * spmf_mult[spmf];
sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
reg = in_be32(&im->clk.scfr[1]);
sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
csb_clk = sys_clk / 2;
cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
reg = in_be32(&im->clk.spmr);
cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
reg = in_be32(&im->clk.scfr[0]);
ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) {
ips_clk = csb_clk / ips_div;
} else {
/* in case we cannot get a sane IPS divisor, fail gracefully */
ips_clk = 0;
}
pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
reg = in_be32(&im->clk.scfr[0]);
pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
if (pci_div != 0) {
pci_clk = csb_clk / pci_div;
} else {