From bfe682e9ddbd8d13903f5e51452d8bff07706f85 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:52 +0200 Subject: [PATCH 1/8] apalis/colibri_t30: add comment about tristate and input vs. output pinmuxing Add pinmuxing comment stating that TRISTATE means the output driver is tri-stated and INPUT means the input driver is enabled vs. OUTPUT where it is disabled. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 2 ++ board/toradex/colibri_t30/pinmux-config-colibri_t30.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index 49c2df7ab2..8d6696aaad 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -11,7 +11,9 @@ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ +/* TRISTATE here means output driver is tri-stated */ \ .tristate = PMUX_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_DEFAULT, \ .od = PMUX_PIN_OD_DEFAULT, \ diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index bdbbf5e49a..6181b506a4 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -11,7 +11,9 @@ .pingrp = PMUX_PINGRP_##_pingrp, \ .func = PMUX_FUNC_##_mux, \ .pull = PMUX_PULL_##_pull, \ +/* TRISTATE here means output driver is tri-stated */ \ .tristate = PMUX_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ .io = PMUX_PIN_##_io, \ .lock = PMUX_PIN_LOCK_DEFAULT, \ .od = PMUX_PIN_OD_DEFAULT, \ From a6094e1b0a8e1707ad43c5911b8cf902d98951a4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:53 +0200 Subject: [PATCH 2/8] colibri_t30: fix spi1 and uart2/3 resp. uartb/c pinmuxing Fix SPI1 and UART2/3 resp. UARTB/C pinmuxing. Note: The former was illegally muxing multiple SoC balls onto the same internal SoC signal which caused rather strange behaviour regarding the RS232 serial transceiver ForceOFF# pins as available on Iris. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- .../colibri_t30/pinmux-config-colibri_t30.h | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index 6181b506a4..c583583b3f 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -181,13 +181,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD_PW6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RXD_PW7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N_PA1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), @@ -270,10 +271,10 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI_PX4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK_PX5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N_PX6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO_PX7, RSVD4, NORMAL, NORMAL, INPUT), /* LAN_RESET */ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT), From 4ba4bd0f87b48d34b5ca68968037fc3aa7658cb7 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:54 +0200 Subject: [PATCH 3/8] apalis/colibri_t30: avoid uart input from floating pins Avoid UART input from floating RX pins on UARTB and UARTC (Colibri T30) and UARTB, UARTC and UARTD (Apalis T30). Note: Floating pins may cause spurious break conditions potentially interrupting U-Boot's autoboot. Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 9 ++++++--- board/toradex/colibri_t30/pinmux-config-colibri_t30.h | 7 ++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h index 8d6696aaad..3a2cf4606e 100644 --- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h +++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h @@ -120,7 +120,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), + /* UARTD RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), @@ -189,12 +190,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + /* UARTB RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), + /* UARTC RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h index c583583b3f..5ac1a6da97 100644 --- a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h +++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h @@ -180,7 +180,8 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), - DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), + /* UARTC RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, UP, NORMAL, INPUT), DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART2_RTS_N_PJ6, GMI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(UART2_CTS_N_PJ5, GMI, NORMAL, NORMAL, INPUT), @@ -207,11 +208,11 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = { DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT), + /* UARTB RX, make sure we don't get input form a floating Pin */ + DEFAULT_PINMUX(GMI_A17_PB0, UARTD, UP, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT), - /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT), DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT), From 8e487f38cc6408d0045194eec2271695da31b321 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:55 +0200 Subject: [PATCH 4/8] apalis/colibri_t30: add note about colibri vs. nvidia uart mapping The following mapping is applicable for Apalis T30: Apalis UART1: NVIDIA UARTA Apalis UART2: NVIDIA UARTD Apalis UART3: NVIDIA UARTB Apalis UART4: NVIDIA UARTC The following mapping is applicable for Colibri T30: Colibri UART-A: NVIDIA UARTA Colibri UART-B: NVIDIA UARTD Colibri UART-C: NVIDIA UARTB Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- include/configs/apalis_t30.h | 9 ++++++++- include/configs/colibri_t30.h | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index bf0aefda2a..f0c003d2fe 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -12,7 +12,14 @@ #include "tegra30-common.h" -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index fa0fa93b03..94802a66f7 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -14,7 +14,13 @@ /* High-level configuration options */ -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE From 1b56cd868e3c691625aa9bce2f475fcd4cf0405a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:56 +0200 Subject: [PATCH 5/8] colibri_t30: disable rs232 serial transceiver forceoff pins Use gpio_early_init_uart() function to disable RS232 serial transceiver ForceOFF# pins on Iris. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- board/toradex/colibri_t30/colibri_t30.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index c5562f6d57..20cbb75a36 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -57,6 +57,17 @@ void pinmux_init(void) ARRAY_SIZE(colibri_t30_padctrl)); } +/* + * Disable RS232 serial transceiver ForceOFF# pins on Iris + */ +void gpio_early_init_uart(void) +{ + gpio_request(TEGRA_GPIO(X, 6), "Force OFF# X13"); + gpio_direction_output(TEGRA_GPIO(X, 6), 1); + gpio_request(TEGRA_GPIO(X, 7), "Force OFF# X14"); + gpio_direction_output(TEGRA_GPIO(X, 7), 1); +} + /* * Enable AX88772B USB to LAN controller */ From 632fb978a513e22e4cbc8410156a185716216649 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 2 Apr 2020 00:28:54 +0100 Subject: [PATCH 6/8] arm: tegra: define fdtfile option for distro boot For booting via UEFI we need to define the fdtfile option so bootefi has the option to load a fdtfile from disk. For arm64 the kernel dtb is located in a vendor directory so we define that as nvidia for that architecture. Signed-off-by: Peter Robinson Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 6 ++++++ include/configs/tegra114-common.h | 1 + include/configs/tegra124-common.h | 1 + include/configs/tegra186-common.h | 1 + include/configs/tegra20-common.h | 1 + include/configs/tegra210-common.h | 1 + include/configs/tegra30-common.h | 1 + 7 files changed, 12 insertions(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2b968917d3..432eceaf35 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -49,6 +49,12 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#ifdef CONFIG_ARM64 +#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index d3a7045697..9d751b6740 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -50,6 +50,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 522993b958..0eb8f92809 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -52,6 +52,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index b4936cc731..5c3ad35c76 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -49,6 +49,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 1e31d82574..fdd8996955 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -51,6 +51,7 @@ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x03000000\0" \ "ramdisk_addr_r=0x03100000\0" diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1b8e94b60c..2226effe16 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,6 +46,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83200000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 54bc6756ab..6c5dc24b26 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -47,6 +47,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" From fe669925cb4276b881a0b444e660378293585093 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 2 Apr 2020 00:28:55 +0100 Subject: [PATCH 7/8] arm: tegra: add options for BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 Upstream linux DT naming doesn't align with the U-Boot DT, which may not always be the case so this allows using BOOTENV_EFI_SET_FDTFILE_FALLBACK where it might be appropriate for some boards. Signed-off-by: Peter Robinson Signed-off-by: Tom Warren --- include/config_distro_bootcmd.h | 2 ++ include/configs/tegra186-common.h | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index ff29ef5a90..82a3a365c5 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -118,8 +118,10 @@ "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ "fi; " #else +#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK #define BOOTENV_EFI_SET_FDTFILE_FALLBACK #endif +#endif #define BOOTENV_SHARED_EFI \ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index 5c3ad35c76..d5f21e0907 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -20,6 +20,12 @@ /* Generic Interrupt Controller */ #define CONFIG_GICV2 +#undef FDTFILE +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ + "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ + "fi; " + /* * Memory layout for where various images get loaded by boot scripts: * @@ -49,7 +55,6 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" From 4f5128ff899d0cb13a7b010f6dbffd0aba71bb25 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 18 Jun 2020 09:41:34 +0200 Subject: [PATCH 8/8] configs: cei-tk1-som: remove CONFIG_ARMV7_PSCI in include file Activate ARCH_SUPPORT_PSCI as other TEGRA124 target and remove CONFIG_ARMV7_PSCI and CONFIG_ARMV7_PSCI_NR_CPUS in configs file as they are migrated in Kconfig. Select CONFIG_ARMV7_PSCI_0_1 (the first PSCI version), because CONFIG_ARMV7_PSCI_0_2 and CONFIG_ARMV7_PSCI_1_0 are not activated in this product. Hi, This patch depend on the previous serie [1]. I don't test this patch on real hardware but after this patch the size of the binary don't change. In .config we have: CONFIG_ARCH_SUPPORT_PSCI=y CONFIG_ARMV7_PSCI=y # CONFIG_ARMV7_PSCI_1_0 is not set # CONFIG_ARMV7_PSCI_0_2 is not set CONFIG_ARMV7_PSCI_0_1=y CONFIG_ARMV7_PSCI_NR_CPUS=4 In u-boot.cfg, this patch only add the 2 lines #define CONFIG_ARCH_SUPPORT_PSCI 1 #define CONFIG_ARMV7_PSCI_0_1 1 [1] "Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig" http://patchwork.ozlabs.org/project/uboot/list/?series=184029 Regards Patrick END Signed-off-by: Patrick Delaunay Reviewed-by: Peter Chubb Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra124/Kconfig | 1 + configs/cei-tk1-som_defconfig | 1 + include/configs/cei-tk1-som.h | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 6fa31ea0a1..fb016aa46c 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -19,6 +19,7 @@ config TARGET_JETSON_TK1 config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" + select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT select CPU_V7_HAS_NONSEC if !SPL_BUILD select CPU_V7_HAS_VIRT if !SPL_BUILD diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index a1b494ec0f..987e3ac8e9 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_ARMV7_PSCI_0_1=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index dd3bdacc2c..2c406d3186 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -28,8 +28,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000