From 82fadccccfd80c6162639180af85c600b6e41d9e Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Fri, 8 Feb 2019 08:59:24 +0000 Subject: [PATCH 1/6] drivers: net: ldpaa_eth: check if the dpmac is enabled some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha --- drivers/net/ldpaa_eth/lx2160a.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index 7dd46c04f6..1fbeb0d14b 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -91,7 +91,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; - if (!ec) + if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV)) wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); #endif @@ -100,7 +100,7 @@ void fsl_rgmii_init(void) & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; - if (!ec) + if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV)) wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); #endif } From 2e9f1bf5888b0df65a691bd10702f33193e9a666 Mon Sep 17 00:00:00 2001 From: Ioana Ciocoi Radulescu Date: Tue, 26 Feb 2019 15:50:07 +0000 Subject: [PATCH 2/6] driver: net: fsl-mc: Fix DPC MAC address fixup If node /board_info/ports does not exist in the DPC file, function mc_fixup_dpc() will skip not only MAC address fixup, but also the cache flush at the end. This may cause the other fixup changes (e.g. ICID related ones) to be ignored by MC. Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL") Signed-off-by: Ioana Radulescu Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha --- drivers/net/fsl-mc/mc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index a51b8a4625..e6cf7f3362 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -421,9 +421,11 @@ static int mc_fixup_dpc(u64 dpc_addr) /* fixup MAC addresses for dpmac ports */ nodeoffset = fdt_path_offset(blob, "/board_info/ports"); if (nodeoffset < 0) - return 0; + goto out; err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC); + +out: flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); return err; From 43ad41e6aecdfd4df71698bec8a69caa23c30232 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Wed, 27 Feb 2019 14:41:02 +0530 Subject: [PATCH 3/6] mc : Reduce MC memory size to 128M ls2088, ls1088 : minimum MC Memory size is 128 MB lx2 : minimum MC memory size is 256 MB Signed-off-by: Meenakshi Aggarwal Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha --- drivers/net/fsl-mc/mc.c | 22 ++++++++++++++++++---- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index e6cf7f3362..cc59b21f9f 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -28,6 +28,7 @@ #define MC_MEM_SIZE_ENV_VAR "mcmemsize" #define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout" #define MC_BOOT_ENV_VAR "mcinitcmd" +#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024) DECLARE_GLOBAL_DATA_PTR; static int mc_memset_resv_ram; @@ -682,13 +683,20 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t mc_ram_size = mc_get_dram_block_size(); mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT; - if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) { + + if (mc_ram_num_256mb_blocks >= 0xff) { error = -EINVAL; printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n", mc_ram_size); goto out; } + /* + * To support 128 MB DDR Size for MC + */ + if (mc_ram_num_256mb_blocks == 0) + mc_ram_num_256mb_blocks = 0xFF; + /* * Management Complex cores should be held at reset out of POR. * U-Boot should be the first software to touch MC. To be safe, @@ -729,8 +737,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Tell MC what is the address range of the DRAM block assigned to it: */ - reg_mcfbalr = (u32)mc_ram_addr | - (mc_ram_num_256mb_blocks - 1); + if (mc_ram_num_256mb_blocks < 0xFF) { + reg_mcfbalr = (u32)mc_ram_addr | + (mc_ram_num_256mb_blocks - 1); + } else { + reg_mcfbalr = (u32)mc_ram_addr | + (mc_ram_num_256mb_blocks); + } + out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr); out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)(mc_ram_addr >> 32)); @@ -880,7 +894,7 @@ unsigned long mc_get_dram_block_size(void) "\' environment variable: %lu\n", dram_block_size); - dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE; } } diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index a80ce92881..50c18f1542 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -147,7 +147,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Command line configuration */ #define CONFIG_CMD_CACHE diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 60a0b42503..454c9e94b6 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -152,7 +152,7 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Command line configuration */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 4b5608b5a3..637619cb55 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -100,7 +100,7 @@ * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #endif /* I2C bus multiplexer */ From d296842c2d6c5245068fcd56fa09b315245c8a8a Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Thu, 28 Feb 2019 08:12:55 +0000 Subject: [PATCH 4/6] board: fsl: lx2160aqds: modify the phy fixup code Now that we are representing the MDIO mux in LX2160AQDS board in producer/consumer terms, the consumer nodes' has been changed. Therefore, modify the device tree fixups according to change in device tree. Signed-off-by: Pankaj Bansal Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha --- board/freescale/lx2160a/eth_lx2160aqds.c | 38 +++++++++++++++++++----- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 1e98d0c1f9..f6e22d7337 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -628,8 +628,9 @@ int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) { char mdio_ioslot_str[] = "mdio@00"; - char mdio_mux_str[] = "mdio-mux-0"; struct lx2160a_qds_mdio *priv; + u64 reg; + u32 phandle; int offset, mux_val; /*Test if the MDIO bus is real mdio bus or muxing front end ?*/ @@ -643,15 +644,32 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) debug("real_bus_num = %d, ioslot = %d\n", priv->realbusnum, priv->ioslot); - sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum); - offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str); + if (priv->realbusnum == EMI1) + reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + else + reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + + offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); if (offset < 0) { - printf("%s node not found under node %s in device tree\n", - mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL)); + printf("mdio@%llx node not found in device tree\n", reg); + return offset; + } + + phandle = fdt_get_phandle(fdt, offset); + phandle = cpu_to_fdt32(phandle); + offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus", + &phandle, 4); + if (offset < 0) { + printf("mdio-mux-%d node not found in device tree\n", + priv->realbusnum == EMI1 ? 1 : 2); return offset; } mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + if (priv->realbusnum == EMI1) + mux_val >>= BRDCFG4_EMI1SEL_SHIFT; + else + mux_val >>= BRDCFG4_EMI2SEL_SHIFT; sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val); offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str); @@ -675,7 +693,9 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset, *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name); if (*subnodeoffset <= 0) { - printf("Could not add subnode %s\n", phy_node_name); + printf("Could not add subnode %s inside node %s err = %s\n", + phy_node_name, fdt_get_name(fdt, offset, NULL), + fdt_strerror(*subnodeoffset)); return *subnodeoffset; } @@ -779,7 +799,6 @@ int fdt_fixup_board_phy(void *fdt) } if (dpmac_id == NUM_WRIOP_PORTS) continue; - ret = fdt_create_phy_node(fdt, offset, i, &subnodeoffset, phy_dev, phandle); @@ -792,6 +811,11 @@ int fdt_fixup_board_phy(void *fdt) fdt_del_node(fdt, subnodeoffset); break; } + /* calculate offset again as new node addition may have + * changed offset; + */ + offset = fdt_get_ioslot_offset(fdt, mii_dev, + fpga_offset); phandle++; } From ba7eadd8e107202ab90d0b2937044b6dcba4b7ae Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Thu, 28 Feb 2019 09:06:40 +0000 Subject: [PATCH 5/6] drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset Fix EC1 and EC2 read from correct offset 26, instead of 25 Signed-off-by: Pramod Kumar Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha --- drivers/net/ldpaa_eth/ls1088a.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 43210532ba..c3260d318c 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -93,7 +93,7 @@ void fsl_rgmii_init(void) u32 ec; #ifdef CONFIG_SYS_FSL_EC1 - ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR]) & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK; ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT; @@ -102,7 +102,7 @@ void fsl_rgmii_init(void) #endif #ifdef CONFIG_SYS_FSL_EC2 - ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR]) & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK; ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT; From 158097052a6a528408e05d2345ff2ccdbb46036e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 6 Mar 2019 14:49:14 +0800 Subject: [PATCH 6/6] armv7: ls102xa: Add workaround for DDR erratum A-008850 Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu Signed-off-by: Alison Wang Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv7/ls102xa/Kconfig | 6 +++ arch/arm/cpu/armv7/ls102xa/soc.c | 44 ++++++++++++++++--- .../include/asm/arch-ls102xa/ls102xa_soc.h | 2 + board/freescale/ls1021aiot/ls1021aiot.c | 2 + board/freescale/ls1021aqds/ddr.c | 2 + board/freescale/ls1021aqds/ddr.h | 3 ++ board/freescale/ls1021aqds/ls1021aqds.c | 30 ------------- board/freescale/ls1021atwr/ls1021atwr.c | 2 + include/configs/ls1021aiot.h | 2 + include/configs/ls1021atwr.h | 2 + 10 files changed, 58 insertions(+), 37 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 5d6a711c14..94fa68250d 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -4,6 +4,7 @@ config ARCH_LS1021A select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 @@ -63,6 +64,11 @@ config SYS_CCI400_OFFSET Offset for CCI400 base. CCI400 base addr = CCSRBAR + CCI400_OFFSET +config SYS_FSL_ERRATUM_A008850 + bool + help + Workaround for DDR erratum A008850 + config SYS_FSL_ERRATUM_A008997 bool help diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 448d951c36..a779d33739 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -11,6 +11,7 @@ #include #include #include +#include struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), @@ -103,6 +104,41 @@ static void erratum_a009007(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ } +static void erratum_a008850_early(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + +void erratum_a008850_post(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = in_be32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + out_be32(&ddr->eor, tmp); +#endif +} + void s_init(void) { } @@ -163,13 +199,6 @@ int arch_soc_init(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); } /* Enable all the snoop signal for various masters */ @@ -191,6 +220,7 @@ int arch_soc_init(void) out_be32(&scfg->eddrtqcfg, 0x63b20042); /* Erratum */ + erratum_a008850_early(); erratum_a009008(); erratum_a009798(); erratum_a008997(); diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h index 05e8b49c2d..1fde8bce5d 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -10,6 +10,8 @@ unsigned int get_soc_major_rev(void); int arch_soc_init(void); int ls102xa_smmu_stream_id_init(void); +void erratum_a008850_post(void); + #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 void erratum_a010315(void); #endif diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index fb05b55b5c..70992a5ce4 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -97,6 +97,8 @@ int dram_init(void) ddrmc_init(); #endif + erratum_a008850_post(); + gd->ram_size = DDR_SIZE; return 0; } diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 98faf9389e..d3e2e53321 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -179,6 +179,8 @@ int fsl_initdram(void) fsl_dp_resume(); #endif + erratum_a008850_post(); + gd->ram_size = dram_size; return 0; diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index ff1fe8e2ec..58a8838436 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -5,6 +5,9 @@ #ifndef __DDR_H__ #define __DDR_H__ + +void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index c08be1ee46..2ca2bd9909 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -200,10 +200,6 @@ int board_early_init_f(void) #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - unsigned int major; - #ifdef CONFIG_NAND_BOOT struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; u32 porsr1, pinctl; @@ -240,10 +236,6 @@ void board_init_f(ulong dummy) i2c_init_all(); #endif - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); - timer_init(); dram_init(); @@ -420,22 +412,12 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - unsigned int major; - #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 erratum_a009942_check_cpo(); #endif - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* Set CCI-400 control override register to - * enable barrier transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - } select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -456,18 +438,6 @@ int board_init(void) #if defined(CONFIG_DEEP_SLEEP) void board_sleep_prepare(void) { - struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - unsigned int major; - - major = get_soc_major_rev(); - if (major == SOC_MAJOR_VER_1_0) { - /* Set CCI-400 control override register to - * enable barrier transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - } - - #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index beb82cebb6..01ba1bc962 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -222,6 +222,8 @@ int dram_init(void) ddrmc_init(); #endif + erratum_a008850_post(); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 6be8df109b..4af3988886 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -85,6 +85,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + /* * Serial Port */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 4b6760b600..da55bf2f43 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -104,6 +104,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ !defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FMAN_FW_IN_NOR