From b9a0cc8752d4afb7ff6dd25393b66b0b55e848b9 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:13 +0100 Subject: [PATCH 01/31] ARM: dts: stm32: Use lower-case hex for address for stm32mp15-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15-u-boot.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index db23d80eef..e23d6c7d7e 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -50,8 +50,8 @@ compatible = "st,stm32mp1-ddr"; - reg = <0x5A003000 0x550 - 0x5A004000 0x234>; + reg = <0x5a003000 0x550 + 0x5a004000 0x234>; clocks = <&rcc AXIDCG>, <&rcc DDRC1>, @@ -237,7 +237,7 @@ u-boot-stm32 { filename = "u-boot.stm32"; mkimage { - args = "-T stm32image -a 0xC0100000 -e 0xC0100000"; + args = "-T stm32image -a 0xc0100000 -e 0xc0100000"; u-boot { }; }; @@ -250,7 +250,7 @@ spl-stm32 { filename = "u-boot-spl.stm32"; mkimage { - args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500"; + args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500"; u-boot-spl { }; }; From f1a3eb59c886af1ae79045658db0215c533fbb85 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:14 +0100 Subject: [PATCH 02/31] ARM: dts: stm32: Use lower-case hex for address for stm32f769-disco-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 7dfe430a40..5589b41652 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -53,9 +53,9 @@ soc { dsi: dsi@40016c00 { compatible = "st,stm32-dsi"; - reg = <0x40016C00 0x800>; + reg = <0x40016c00 0x800>; resets = <&rcc STM32F7_APB2_RESET(DSI)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, + clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, <&clk_hse>; clock-names = "pclk", "px_clk", "ref"; @@ -227,7 +227,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>; flash0: mx66l51235l@0 { #address-cells = <1>; #size-cells = <1>; From 4aace3da3c72ab8913ab6d7cdb552e356fdc1fc3 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:15 +0100 Subject: [PATCH 03/31] ARM: dts: stm32: Use lower-case hex for address for stm32746-disco-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 4f34fc9a8c..f88466fa60 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -228,7 +228,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>; qflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; From e447a18095ad049c10983b366756da24f3a8ef2a Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:16 +0100 Subject: [PATCH 04/31] ARM: dts: stm32: Use lower-case hex for address for stm32f7-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32f7-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 46bd1102df..c1b2ac25c3 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -7,7 +7,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; @@ -46,7 +46,7 @@ compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <92>; spi-max-frequency = <108000000>; From e114ddc3851775ebad13b74124af446497d9b6da Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:17 +0100 Subject: [PATCH 05/31] ARM: dts: stm32: Use lower-case hex for address for stm32f469-disco-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 9eda8f535b..cd173623ef 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -34,7 +34,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; st,syscfg = <&syscfg>; pinctrl-0 = <&fmc_pins_d32>; @@ -70,7 +70,7 @@ compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <91>; spi-max-frequency = <108000000>; @@ -236,7 +236,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>; flash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; From fbe6b99d96de7fd1908118a5e198b3e6f42df2a4 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:18 +0100 Subject: [PATCH 06/31] ARM: dts: stm32: Use lower-case hex for address for stm32f429-disco-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32f429-disco-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index 297cc56144..c993f86be8 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -33,7 +33,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; From a2f823e49e100774697a37c814a58c7e7a4fc983 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:19 +0100 Subject: [PATCH 07/31] ARM: dts: stm32: Use lower-case hex for address for stm32f746g-eval-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32746g-eval-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi index f2195a6c51..8550ef7863 100644 --- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -177,7 +177,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>; qflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; From 0c6079c2a9661a8b2651c6c31c1c840205c5826c Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Nov 2021 11:39:20 +0100 Subject: [PATCH 08/31] ARM: dts: stm32: Use lower-case hex for address for stm32429i-eval-u-boot.dtsi Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32429i-eval-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi index 09d9d9ab9b..fcab9ae977 100644 --- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -33,7 +33,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; st,syscfg = <&syscfg>; pinctrl-0 = <&fmc_pins_d32>; From 4c5956086afc1c841d20de639d4cc9a7cfd6b8de Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 10 Nov 2021 18:14:10 +0100 Subject: [PATCH 09/31] pinctrl: stmfx: define LOG_CATEGORY Define LOG_CATEGORY to allow filtering with log command. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/pinctrl/pinctrl-stmfx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index fe7a59d431..509e2a80e9 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -5,8 +5,12 @@ * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander * based on Linux driver : pinctrl/pinctrl-stmfx.c */ + +#define LOG_CATEGORY UCLASS_PINCTRL + #include #include +#include #include #include #include From 15e20e4bdf3a247962c2274070e0b28ab6f1e2f5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:24:44 +0100 Subject: [PATCH 10/31] ARM: stm32: Increase USB power-good delay on DHSOM The USB hub on STM32MP1 DHCOM boards needs to wait a bit longer until the USB Vbus is stable. Increase the USB power-good delay to 1 s. This adds default-undefined STM32MP_BOARD_EXTRA_ENV variable into stm32mp15_common.h to reduce duplication in board-specific config files adding custom environment. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/configs/stm32mp15_common.h | 7 ++++++- include/configs/stm32mp15_dh_dhsom.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 4e2cabff2e..dab679f71e 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -142,6 +142,10 @@ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" +#ifndef STM32MP_BOARD_EXTRA_ENV +#define STM32MP_BOARD_EXTRA_ENV +#endif + #include /* @@ -169,7 +173,8 @@ STM32MP_BOOTCMD \ STM32MP_PARTS_DEFAULT \ BOOTENV \ - STM32MP_EXTRA + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV #endif /* ifndef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index c559cd72da..bac9e8388a 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_DH_DHSOM_H__ #define __CONFIG_STM32MP15_DH_DHSOM_H__ +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" + #include #define CONFIG_SPL_TARGET "u-boot.itb" From 1aba8e51d85293360150028297c5c2b479c86078 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:25:13 +0100 Subject: [PATCH 11/31] ARM: stm32: Add update_sf script to install U-Boot into SF on DHSOM Add script to read U-Boot from SD card and write it to matching locations in the SPI NOR, thus making the SPI NOR bootable. The script erases the entire SPI NOR, including U-Boot environment, to make sure the installation is clean. To retain environment from current running U-Boot, run 'saveenv' after running the 'update_sf' script. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/configs/stm32mp15_dh_dhsom.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index bac9e8388a..b68e153f10 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -9,7 +9,17 @@ #define __CONFIG_STM32MP15_DH_DHSOM_H__ #define STM32MP_BOARD_EXTRA_ENV \ - "usb_pgood_delay=1000\0" + "usb_pgood_delay=1000\0" \ + "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ + "setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \ + "load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \ + "env set filesize1 ${filesize} && " \ + "load mmc 0:4 ${loadaddr} /boot/u-boot.itb && " \ + "sf probe && sf erase 0 0x200000 && " \ + "sf update ${loadaddr1} 0 ${filesize1} && " \ + "sf update ${loadaddr1} 0x40000 ${filesize1} && " \ + "sf update ${loadaddr} 0x80000 ${filesize} && " \ + "env set filesize1 && env set loadaddr1\0" #include From 5e3e882cf2ef50fbad63493c7ade15b91e2ebc2c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:26:05 +0100 Subject: [PATCH 12/31] ARM: stm32: Increase PHY auto-negotiation timeout to 20s on DHSOM The Micrel PHYs on known DHSOM based boards take a while to come out of reset, increase the auto-negotiation timeout to prevent it from timing out in case the ethernet is used right after the board was reset. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/configs/stm32mp15_dh_dhsom.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index b68e153f10..c79f0272cb 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_DH_DHSOM_H__ #define __CONFIG_STM32MP15_DH_DHSOM_H__ +/* PHY needs a longer autoneg timeout */ +#define PHY_ANEG_TIMEOUT 20000 + #define STM32MP_BOARD_EXTRA_ENV \ "usb_pgood_delay=1000\0" \ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ From 525dd34535005ecde1cde7235c4d1d7329617248 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:26:39 +0100 Subject: [PATCH 13/31] ARM: stm32: Fix SoM and board coding strap GPIO handling on DHSOM The variables retaining the strap values have to be initialized, always, make it so. Moreover, free the requested GPIO list at the end to avoid wasting memory. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/dhelectronics/dh_stm32mp1/board.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index a8402e2457..f44afb01e2 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -212,34 +212,40 @@ static void board_get_coding_straps(void) ofnode node; int i, ret; + brdcode = 0; + ddr3code = 0; + somcode = 0; + node = ofnode_path("/config"); if (!ofnode_valid(node)) { printf("%s: no /config node?\n", __func__); return; } - brdcode = 0; - ddr3code = 0; - somcode = 0; - ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios", gpio, ARRAY_SIZE(gpio), GPIOD_IS_IN); for (i = 0; i < ret; i++) somcode |= !!dm_gpio_get_value(&(gpio[i])) << i; + gpio_free_list_nodev(gpio, ret); + ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios", gpio, ARRAY_SIZE(gpio), GPIOD_IS_IN); for (i = 0; i < ret; i++) ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i; + gpio_free_list_nodev(gpio, ret); + ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios", gpio, ARRAY_SIZE(gpio), GPIOD_IS_IN); for (i = 0; i < ret; i++) brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i; + gpio_free_list_nodev(gpio, ret); + printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n", somcode, ddr3code, brdcode); } From 312011e8e7ba1a5cf2234dae73daa8304f5993dd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:27:37 +0100 Subject: [PATCH 14/31] ARM: dts: stm32: Add custom PHY reset bindings on AV96 The ethernet PHY must be reset on AV96, however DWMAC currently does not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC PHY reset property is going away on next DT sync. Add PHY specific reset bindings to trigger the PHY reset and fix sporadic ethernet malfunctions, until the next DT sync. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 8b275e4950..4b1dbf0838 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -19,6 +19,17 @@ }; }; + +ðernet0 { + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <1000>; + }; + }; +}; + &sdmmc1 { u-boot,dm-spl; }; From 7d35a499bdaa0f8433640452f2db0ba59d86052b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:28:03 +0100 Subject: [PATCH 15/31] ARM: stm32: Enable KSZ90x1 PHY driver on DHCOR Enable KSZ9x01 PHY driver in DHCOR common configuration, since the AV96 board has this PHY populated on the PCB. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15_dhcor_basic_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index aa000effc4..2356de76ba 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -108,6 +108,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_DWC_ETH_QOS=y CONFIG_PHY=y From 8e5266eefdd0fcc139113214a75f287168c006ec Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:29:43 +0100 Subject: [PATCH 16/31] mmc: stm32_sdmmc2: Add support for probing bus voltage level translator Add support for testing whether bus voltage level translator is present and operational. This is useful on systems where the bus voltage level translator is optional, as the translator can be auto-detected by the driver and the feedback clock functionality can be disabled if it is not present. The translator test sets CMD high to avoid interfering with a card, and then verifies whether signal set on CK is detected on CKIN. If the signal is detected, translator is present, otherwise the CKIN feedback clock are disabled. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Yann Gautier --- drivers/mmc/stm32_sdmmc2.c | 63 +++++++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index a3cdf7bcd9..44bfc911af 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -645,6 +646,66 @@ static const struct dm_mmc_ops stm32_sdmmc2_ops = { .host_power_cycle = stm32_sdmmc2_host_power_cycle, }; +static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) +{ + struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct gpio_desc cmd_gpio; + struct gpio_desc ck_gpio; + struct gpio_desc ckin_gpio; + int clk_hi, clk_lo, ret; + + /* + * Assume the level translator is present if st,use-ckin is set. + * This is to cater for DTs which do not implement this test. + */ + priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; + + ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) + goto exit_cmd; + + ret = gpio_request_by_name(dev, "st,ck-gpios", 0, &ck_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) + goto exit_ck; + + ret = gpio_request_by_name(dev, "st,ckin-gpios", 0, &ckin_gpio, + GPIOD_IS_IN); + if (ret) + goto exit_ckin; + + /* All GPIOs are valid, test whether level translator works */ + + /* Sample CKIN */ + clk_hi = !!dm_gpio_get_value(&ckin_gpio); + + /* Set CK low */ + dm_gpio_set_value(&ck_gpio, 0); + + /* Sample CKIN */ + clk_lo = !!dm_gpio_get_value(&ckin_gpio); + + /* Tristate all */ + dm_gpio_set_dir_flags(&cmd_gpio, GPIOD_IS_IN); + dm_gpio_set_dir_flags(&ck_gpio, GPIOD_IS_IN); + + /* Level translator is present if CK signal is propagated to CKIN */ + if (!clk_hi || clk_lo) + priv->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN; + + dm_gpio_free(dev, &ckin_gpio); + +exit_ckin: + dm_gpio_free(dev, &ck_gpio); +exit_ck: + dm_gpio_free(dev, &cmd_gpio); +exit_cmd: + pinctrl_select_state(dev, "default"); + + return 0; +} + static int stm32_sdmmc2_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -662,7 +723,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) if (dev_read_bool(dev, "st,sig-dir")) priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; if (dev_read_bool(dev, "st,use-ckin")) - priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; + stm32_sdmmc2_probe_level_translator(dev); ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) From 77d043cac66965d48381cfec8f227799202a0a30 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:29:44 +0100 Subject: [PATCH 17/31] ARM: dts: stm32: Auto-detect DHSOM with uSD level translator The uSD level translator on DHSOM and Avenger96 are optional, however it is possible to auto-detect it. This is done by setting SD CMD line high, and then testing whether signal level on CK line matches the signal level on CKIN line. If so, the uSD level translator is present, otherwise it is not populated. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 4 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 71b0486f02..5b2b09bcfb 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -216,6 +216,10 @@ &sdmmc1 { u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; }; &sdmmc1_b4_pins_a { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 4b1dbf0838..c96eba99c5 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -32,6 +32,10 @@ &sdmmc1 { u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; }; &sdmmc1_b4_pins_a { From 4831ba2903d886d233400423c2a425fde170b367 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 15:32:28 +0100 Subject: [PATCH 18/31] stm32mp1: ram: add read valid training support Add the read data eye training = training for optimal read valid placement (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3. This training is supported on the PUBL integrated in the STM32MP15x DDR subsystem and it is not required for DDR3. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 8 ++++++-- drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 0457166b12..1f8422518b 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -826,8 +826,12 @@ start: */ /* 10. configure PUBL PIR register to specify which training step to run */ - /* warning : RVTRN is not supported by this PUBL */ - stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); + /* RVTRN is excuted only on LPDDR2/LPDDR3 */ + if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) + pir = DDRPHYC_PIR_QSTRN; + else + pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN; + stm32mp1_ddrphy_init(priv->phy, pir); /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ ddrphy_idone_wait(priv->phy); diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index 3c8885a965..ada3087328 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -309,6 +309,7 @@ struct stm32mp1_ddrphy { #define DDRPHYC_PIR_DRAMRST BIT(5) #define DDRPHYC_PIR_DRAMINIT BIT(6) #define DDRPHYC_PIR_QSTRN BIT(7) +#define DDRPHYC_PIR_RVTRN BIT(8) #define DDRPHYC_PIR_ICPC BIT(16) #define DDRPHYC_PIR_ZCALBYP BIT(30) #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) From 9819fe345cc9de8ab1ca8c53999b5d460a8d0e7d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 15:32:29 +0100 Subject: [PATCH 19/31] stm32mp1: ram: remove the support of calibration result The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15-ddr.dtsi | 30 --------- .../dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 12 ---- .../dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 12 ---- .../stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 12 ---- .../stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 12 ---- .../stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 12 ---- .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 12 ---- .../memory-controllers/st,stm32mp1-ddr.txt | 32 --------- drivers/ram/stm32mp1/stm32mp1_ddr.c | 65 +++++++------------ drivers/ram/stm32mp1/stm32mp1_ddr.h | 17 ----- drivers/ram/stm32mp1/stm32mp1_interactive.c | 15 +---- drivers/ram/stm32mp1/stm32mp1_ram.c | 22 +------ 12 files changed, 27 insertions(+), 226 deletions(-) diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 2a139c54e9..0aac9131a6 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -116,24 +116,6 @@ DDR_MR3 >; -#ifdef DDR_PHY_CAL_SKIP - st,phy-cal = < - DDR_DX0DLLCR - DDR_DX0DQTR - DDR_DX0DQSTR - DDR_DX1DLLCR - DDR_DX1DQTR - DDR_DX1DQSTR - DDR_DX2DLLCR - DDR_DX2DQTR - DDR_DX2DQSTR - DDR_DX3DLLCR - DDR_DX3DQTR - DDR_DX3DQSTR - >; - -#endif - status = "okay"; }; }; @@ -224,18 +206,6 @@ #undef DDR_ODTCR #undef DDR_ZQ0CR1 #undef DDR_DX0GCR -#undef DDR_DX0DLLCR -#undef DDR_DX0DQTR -#undef DDR_DX0DQSTR #undef DDR_DX1GCR -#undef DDR_DX1DLLCR -#undef DDR_DX1DQTR -#undef DDR_DX1DQSTR #undef DDR_DX2GCR -#undef DDR_DX2DLLCR -#undef DDR_DX2DQTR -#undef DDR_DX2DQSTR #undef DDR_DX3GCR -#undef DDR_DX3DLLCR -#undef DDR_DX3DQTR -#undef DDR_DX3DQSTR diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index 978331b279..e60d0ae606 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE80 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE80 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index 426be21f42..1a6fa80edf 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi index b3eb280f96..0a277cd675 100644 --- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi @@ -101,20 +101,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi index ed3a5248f8..92774fffb9 100644 --- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi @@ -101,20 +101,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi index d5813d64b0..e53ab18a69 100644 --- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi @@ -101,20 +101,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi index 24c81269b0..ff582ac6af 100644 --- a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt index ac6a7df432..926e3e83b3 100644 --- a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -128,23 +128,6 @@ phyc attributes: MR2 MR3 -- st,phy-cal : phy cal depending of calibration or tuning of DDR - This parameter is optional; when it is absent the built-in PHY - calibration is done. - for STM32MP15x: 12 values are requested in this order - DX0DLLCR - DX0DQTR - DX0DQSTR - DX1DLLCR - DX1DQTR - DX1DQSTR - DX2DLLCR - DX2DQTR - DX2DQSTR - DX3DLLCR - DX3DQTR - DX3DQSTR - Example: / { @@ -280,21 +263,6 @@ Example: 0x00000000 /*MR3*/ >; - st,phy-cal = < - 0x40000000 /*DX0DLLCR*/ - 0xFFFFFFFF /*DX0DQTR*/ - 0x3DB02000 /*DX0DQSTR*/ - 0x40000000 /*DX1DLLCR*/ - 0xFFFFFFFF /*DX1DQTR*/ - 0x3DB02000 /*DX1DQSTR*/ - 0x40000000 /*DX2DLLCR*/ - 0xFFFFFFFF /*DX2DQTR*/ - 0x3DB02000 /*DX2DQSTR*/ - 0x40000000 /*DX3DLLCR*/ - 0xFFFFFFFF /*DX3DQTR*/ - 0x3DB02000 /*DX3DQSTR*/ - >; - status = "okay"; }; }; diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 1f8422518b..9d086601a4 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -68,7 +68,6 @@ struct reg_desc { #define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */ #define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */ -#define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */ #define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg) static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = { @@ -178,22 +177,6 @@ static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = { DDRPHY_REG_TIMING(mr3), }; -#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) -static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = { - DDRPHY_REG_CAL(dx0dllcr), - DDRPHY_REG_CAL(dx0dqtr), - DDRPHY_REG_CAL(dx0dqstr), - DDRPHY_REG_CAL(dx1dllcr), - DDRPHY_REG_CAL(dx1dqtr), - DDRPHY_REG_CAL(dx1dqstr), - DDRPHY_REG_CAL(dx2dllcr), - DDRPHY_REG_CAL(dx2dqtr), - DDRPHY_REG_CAL(dx2dqstr), - DDRPHY_REG_CAL(dx3dllcr), - DDRPHY_REG_CAL(dx3dqtr), - DDRPHY_REG_CAL(dx3dqstr), -}; - /************************************************************** * DYNAMIC REGISTERS: only used for debug purpose (read/modify) **************************************************************/ @@ -218,12 +201,24 @@ static const struct reg_desc ddrphy_dyn[] = { DDRPHY_REG_DYN(zq0sr1), DDRPHY_REG_DYN(dx0gsr0), DDRPHY_REG_DYN(dx0gsr1), + DDRPHY_REG_DYN(dx0dllcr), + DDRPHY_REG_DYN(dx0dqtr), + DDRPHY_REG_DYN(dx0dqstr), DDRPHY_REG_DYN(dx1gsr0), DDRPHY_REG_DYN(dx1gsr1), + DDRPHY_REG_DYN(dx1dllcr), + DDRPHY_REG_DYN(dx1dqtr), + DDRPHY_REG_DYN(dx1dqstr), DDRPHY_REG_DYN(dx2gsr0), DDRPHY_REG_DYN(dx2gsr1), + DDRPHY_REG_DYN(dx2dllcr), + DDRPHY_REG_DYN(dx2dqtr), + DDRPHY_REG_DYN(dx2dqstr), DDRPHY_REG_DYN(dx3gsr0), DDRPHY_REG_DYN(dx3gsr1), + DDRPHY_REG_DYN(dx3dllcr), + DDRPHY_REG_DYN(dx3dqtr), + DDRPHY_REG_DYN(dx3dqstr), }; #define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn) @@ -240,7 +235,6 @@ enum reg_type { REG_MAP, REGPHY_REG, REGPHY_TIMING, - REGPHY_CAL, #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE /* dynamic registers => managed in driver or not changed, * can be dumped in interactive mode @@ -264,8 +258,6 @@ struct ddr_reg_info { enum base_type base; }; -#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) - const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = { [REG_REG] = { "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE}, @@ -279,8 +271,6 @@ const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = { "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE}, [REGPHY_TIMING] = { "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE}, -[REGPHY_CAL] = { - "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE}, #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE [REG_DYN] = { "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE}, @@ -456,9 +446,6 @@ static u32 get_par_addr(const struct stm32mp1_ddr_config *config, case REGPHY_TIMING: par_addr = (u32)&config->p_timing; break; - case REGPHY_CAL: - par_addr = (u32)&config->p_cal; - break; case REG_DYN: case REGPHY_DYN: case REG_TYPE_NB: @@ -774,8 +761,6 @@ start: */ set_reg(priv, REGPHY_REG, &config->p_reg); set_reg(priv, REGPHY_TIMING, &config->p_timing); - if (config->p_cal_present) - set_reg(priv, REGPHY_CAL, &config->p_cal); if (INTERACTIVE(STEP_PHY_INIT)) goto start; @@ -810,36 +795,32 @@ start: wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); - if (config->p_cal_present) { - log_debug("DDR DQS training skipped.\n"); - } else { - log_debug("DDR DQS training : "); + log_debug("DDR DQS training : "); /* 8. Disable Auto refresh and power down by setting * - RFSHCTL3.dis_au_refresh = 1 * - PWRCTL.powerdown_en = 0 * - DFIMISC.dfiinit_complete_en = 0 */ - stm32mp1_refresh_disable(priv->ctl); + stm32mp1_refresh_disable(priv->ctl); /* 9. Program PUBL PGCR to enable refresh during training and rank to train * not done => keep the programed value in PGCR */ /* 10. configure PUBL PIR register to specify which training step to run */ - /* RVTRN is excuted only on LPDDR2/LPDDR3 */ - if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) - pir = DDRPHYC_PIR_QSTRN; - else - pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN; - stm32mp1_ddrphy_init(priv->phy, pir); + /* RVTRN is excuted only on LPDDR2/LPDDR3 */ + if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) + pir = DDRPHYC_PIR_QSTRN; + else + pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN; + stm32mp1_ddrphy_init(priv->phy, pir); /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ - ddrphy_idone_wait(priv->phy); + ddrphy_idone_wait(priv->phy); /* 12. set back registers in step 8 to the orginal values if desidered */ - stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, - config->c_reg.pwrctl); - } /* if (config->p_cal_present) */ + stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, + config->c_reg.pwrctl); /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h index 4998f04439..3bfcb85a8f 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h @@ -140,21 +140,6 @@ struct stm32mp1_ddrphy_timing { u32 mr3; }; -struct stm32mp1_ddrphy_cal { - u32 dx0dllcr; - u32 dx0dqtr; - u32 dx0dqstr; - u32 dx1dllcr; - u32 dx1dqtr; - u32 dx1dqstr; - u32 dx2dllcr; - u32 dx2dqtr; - u32 dx2dqstr; - u32 dx3dllcr; - u32 dx3dqtr; - u32 dx3dqstr; -}; - struct stm32mp1_ddr_info { const char *name; u32 speed; /* in kHZ */ @@ -169,8 +154,6 @@ struct stm32mp1_ddr_config { struct stm32mp1_ddrctrl_perf c_perf; struct stm32mp1_ddrphy_reg p_reg; struct stm32mp1_ddrphy_timing p_timing; - struct stm32mp1_ddrphy_cal p_cal; - bool p_cal_present; }; int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed); diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index 8c2310ac90..a667d49cff 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -111,7 +111,7 @@ static void stm32mp1_do_usage(void) "help displays help\n" "info displays DDR information\n" "info changes DDR information\n" - " with = step, name, size, speed or cal\n" + " with = step, name, size or speed\n" "freq displays the DDR PHY frequency in kHz\n" "freq changes the DDR PHY frequency\n" "param [type|reg] prints input parameters\n" @@ -132,7 +132,7 @@ static void stm32mp1_do_usage(void) "\nwith for [type|reg]:\n" " all registers if absent\n" " = ctl, phy\n" - " or one category (static, timing, map, perf, cal, dyn)\n" + " or one category (static, timing, map, perf, dyn)\n" " = name of the register\n" }; @@ -165,7 +165,6 @@ static void stm32mp1_do_info(struct ddr_info *priv, printf("name = %s\n", config->info.name); printf("size = 0x%x\n", config->info.size); printf("speed = %d kHz\n", config->info.speed); - printf("cal = %d\n", config->p_cal_present); return; } @@ -214,16 +213,6 @@ static void stm32mp1_do_info(struct ddr_info *priv, } return; } - if (!strcmp(argv[1], "cal")) { - if (strict_strtoul(argv[2], 10, &value) < 0 || - (value != 0 && value != 1)) { - printf("invalid value %s\n", argv[2]); - } else { - config->p_cal_present = value; - printf("cal = %d\n", config->p_cal_present); - } - return; - } printf("argument %s invalid\n", argv[1]); } diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 98fa1f4f11..3b65269b98 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -95,26 +95,22 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) { .name = x, \ .offset = offsetof(struct stm32mp1_ddr_config, y), \ .size = sizeof(config.y) / sizeof(u32), \ - .present = z, \ } #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL) #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL) -#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present) const struct { const char *name; /* name in DT */ const u32 offset; /* offset in config struct */ const u32 size; /* size of parameters */ - bool * const present; /* presence indication for opt */ } param[] = { CTL_PARAM(reg), CTL_PARAM(timing), CTL_PARAM(map), CTL_PARAM(perf), PHY_PARAM(reg), - PHY_PARAM(timing), - PHY_PARAM_OPT(cal) + PHY_PARAM(timing) }; config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0); @@ -133,25 +129,11 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) param[idx].size); dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); - if (ret && - (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) { + if (ret) { dev_err(dev, "Cannot read %s, error=%d\n", param[idx].name, ret); return -EINVAL; } - if (param[idx].present) { - /* save presence of optional parameters */ - *param[idx].present = true; - if (ret == -FDT_ERR_NOTFOUND) { - *param[idx].present = false; -#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE - /* reset values if used later */ - memset((void *)((u32)&config + - param[idx].offset), - 0, param[idx].size * sizeof(u32)); -#endif - } - } } ret = clk_get_by_name(dev, "axidcg", &axidcg); From b3c29dc9e5f0ed2bef4f20927a8c9bba4342a1cb Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 15:32:30 +0100 Subject: [PATCH 20/31] stm32mp1: ram: remove tuning support Remove the DDR interactive command tuning, as the support of a predefined DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A and the result of this tuning will be never used. Moreover this SW tuning procedure can failed on some hardware configuration (to many BIST errors and no convergence); it will be no more supported in the next delivery of the DDR utilities included in the CubeMX tool of STMicroelectronics. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/ram/stm32mp1/Makefile | 1 - drivers/ram/stm32mp1/stm32mp1_ddr.c | 8 +- drivers/ram/stm32mp1/stm32mp1_ddr.h | 5 - drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 64 +- drivers/ram/stm32mp1/stm32mp1_interactive.c | 22 +- drivers/ram/stm32mp1/stm32mp1_tests.h | 3 - drivers/ram/stm32mp1/stm32mp1_tuning.c | 1540 ------------------- 7 files changed, 7 insertions(+), 1636 deletions(-) delete mode 100644 drivers/ram/stm32mp1/stm32mp1_tuning.c diff --git a/drivers/ram/stm32mp1/Makefile b/drivers/ram/stm32mp1/Makefile index e1e9135603..71ded6bed4 100644 --- a/drivers/ram/stm32mp1/Makefile +++ b/drivers/ram/stm32mp1/Makefile @@ -8,7 +8,6 @@ obj-y += stm32mp1_ddr.o obj-$(CONFIG_STM32MP1_DDR_INTERACTIVE) += stm32mp1_interactive.o obj-$(CONFIG_STM32MP1_DDR_TESTS) += stm32mp1_tests.o -obj-$(CONFIG_STM32MP1_DDR_TUNING) += stm32mp1_tuning.o ifneq ($(DDR_INTERACTIVE),) CFLAGS_stm32mp1_interactive.o += -DCONFIG_STM32MP1_DDR_INTERACTIVE_FORCE=y diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 9d086601a4..4d78aa5cb1 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -557,7 +557,7 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) (u32)&phy->pgsr, pgsr, ret); } -void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) +static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) { pir |= DDRPHYC_PIR_INIT; writel(pir, &phy->pir); @@ -626,7 +626,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode) log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat); } -void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) +static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) { start_sw_done(ctl); /* quasi-dynamic register update*/ @@ -637,8 +637,8 @@ void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) wait_sw_done_ack(ctl); } -void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, - u32 rfshctl3, u32 pwrctl) +static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + u32 rfshctl3, u32 pwrctl) { start_sw_done(ctl); if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH)) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.h b/drivers/ram/stm32mp1/stm32mp1_ddr.h index 3bfcb85a8f..861efff92b 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.h @@ -157,11 +157,6 @@ struct stm32mp1_ddr_config { }; int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed); -void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir); -void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl); -void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, - u32 rfshctl3, - u32 pwrctl); void stm32mp1_ddr_init( struct ddr_info *priv, diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index ada3087328..be89d81018 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -6,8 +6,9 @@ #ifndef _RAM_STM32MP1_DDR_REGS_H #define _RAM_STM32MP1_DDR_REGS_H -/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ #include + +/* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ struct stm32mp1_ddrctl { u32 mstr ; /* 0x0 Master*/ u32 stat; /* 0x4 Operating Mode Status*/ @@ -275,25 +276,6 @@ struct stm32mp1_ddrphy { #define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) -#define DDRCTRL_DBG1_DIS_HIF BIT(1) - -#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) -#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) -#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) -#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) -#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) -#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ - (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ - DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) -#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ - (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ - DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ - DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) - -#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) - -#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) - #define DDRCTRL_SWCTL_SW_DONE BIT(0) #define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) @@ -312,11 +294,6 @@ struct stm32mp1_ddrphy { #define DDRPHYC_PIR_RVTRN BIT(8) #define DDRPHYC_PIR_ICPC BIT(16) #define DDRPHYC_PIR_ZCALBYP BIT(30) -#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) - -#define DDRPHYC_PGCR_DFTCMP BIT(2) -#define DDRPHYC_PGCR_PDDISDX BIT(24) -#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25) #define DDRPHYC_PGSR_IDONE BIT(0) #define DDRPHYC_PGSR_DTERR BIT(5) @@ -325,43 +302,6 @@ struct stm32mp1_ddrphy { #define DDRPHYC_PGSR_RVERR BIT(8) #define DDRPHYC_PGSR_RVEIRR BIT(9) -#define DDRPHYC_DLLGCR_BPS200 BIT(23) - -#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) - -#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0) -#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0 -#define DDRPHYC_ZQ0CRN_ZDEN BIT(28) - -#define DDRPHYC_DXNGCR_DXEN BIT(0) - -#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30) -#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) -#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14) -#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14 - -#define DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit) (4 * (bit)) -#define DDRPHYC_DXNDQTR_DQDLY_MASK GENMASK(3, 0) -#define DDRPHYC_DXNDQTR_DQDLY_LOW_MASK GENMASK(1, 0) -#define DDRPHYC_DXNDQTR_DQDLY_HIGH_MASK GENMASK(3, 2) - -#define DDRPHYC_DXNDQSTR_DQSDLY_MASK GENMASK(22, 20) -#define DDRPHYC_DXNDQSTR_DQSDLY_SHIFT 20 -#define DDRPHYC_DXNDQSTR_DQSNDLY_MASK GENMASK(25, 23) -#define DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT 23 -#define DDRPHYC_DXNDQSTR_R0DGSL_MASK GENMASK(2, 0) -#define DDRPHYC_DXNDQSTR_R0DGSL_SHIFT 0 -#define DDRPHYC_DXNDQSTR_R0DGPS_MASK GENMASK(13, 12) -#define DDRPHYC_DXNDQSTR_R0DGPS_SHIFT 12 - -#define DDRPHYC_BISTRR_BDXSEL_MASK GENMASK(22, 19) -#define DDRPHYC_BISTRR_BDXSEL_SHIFT 19 - -#define DDRPHYC_BISTGSR_BDDONE BIT(0) -#define DDRPHYC_BISTGSR_BDXERR BIT(2) - -#define DDRPHYC_BISTWCSR_DXWCNT_SHIFT 16 - /* PWR registers */ #define PWR_CR3 0x00C #define PWR_CR3_DDRSRDIS BIT(11) diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index a667d49cff..f0fe7e61e3 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -32,7 +32,6 @@ enum ddr_command { DDR_CMD_NEXT, DDR_CMD_GO, DDR_CMD_TEST, - DDR_CMD_TUNING, DDR_CMD_UNKNOWN, }; @@ -59,9 +58,6 @@ enum ddr_command stm32mp1_get_command(char *cmd, int argc) [DDR_CMD_GO] = "go", #ifdef CONFIG_STM32MP1_DDR_TESTS [DDR_CMD_TEST] = "test", -#endif -#ifdef CONFIG_STM32MP1_DDR_TUNING - [DDR_CMD_TUNING] = "tuning", #endif }; /* min and max number of argument */ @@ -78,9 +74,6 @@ enum ddr_command stm32mp1_get_command(char *cmd, int argc) [DDR_CMD_GO] = { 0, 0 }, #ifdef CONFIG_STM32MP1_DDR_TESTS [DDR_CMD_TEST] = { 0, 255 }, -#endif -#ifdef CONFIG_STM32MP1_DDR_TUNING - [DDR_CMD_TUNING] = { 0, 255 }, #endif }; int i; @@ -125,9 +118,6 @@ static void stm32mp1_do_usage(void) "reset reboots machine\n" #ifdef CONFIG_STM32MP1_DDR_TESTS "test [help] | [...] lists (with help) or executes test \n" -#endif -#ifdef CONFIG_STM32MP1_DDR_TUNING - "tuning [help] | [...] lists (with help) or execute tuning \n" #endif "\nwith for [type|reg]:\n" " all registers if absent\n" @@ -311,7 +301,7 @@ end: return step; } -#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING) +#if defined(CONFIG_STM32MP1_DDR_TESTS) static const char * const s_result[] = { [TEST_PASSED] = "Pass", [TEST_FAILED] = "Failed", @@ -468,16 +458,6 @@ bool stm32mp1_ddr_interactive(void *priv, stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb); break; #endif - -#ifdef CONFIG_STM32MP1_DDR_TUNING - case DDR_CMD_TUNING: - if (!stm32mp1_check_step(step, STEP_DDR_READY)) - continue; - stm32mp1_ddr_subcmd(priv, argc, argv, - tuning, tuning_nb); - break; -#endif - default: break; } diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.h b/drivers/ram/stm32mp1/stm32mp1_tests.h index 55f5d6d93b..8436780790 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.h +++ b/drivers/ram/stm32mp1/stm32mp1_tests.h @@ -28,7 +28,4 @@ struct test_desc { extern const struct test_desc test[]; extern const int test_nb; -extern const struct test_desc tuning[]; -extern const int tuning_nb; - #endif diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c deleted file mode 100644 index c8cd7c3cea..0000000000 --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c +++ /dev/null @@ -1,1540 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2019, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY UCLASS_RAM - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stm32mp1_ddr_regs.h" -#include "stm32mp1_ddr.h" -#include "stm32mp1_tests.h" - -#define MAX_DQS_PHASE_IDX _144deg -#define MAX_DQS_UNIT_IDX 7 -#define MAX_GSL_IDX 5 -#define MAX_GPS_IDX 3 - -/* Number of bytes used in this SW. ( min 1--> max 4). */ -#define NUM_BYTES 4 - -enum dqs_phase_enum { - _36deg = 0, - _54deg = 1, - _72deg = 2, - _90deg = 3, - _108deg = 4, - _126deg = 5, - _144deg = 6 -}; - -/* BIST Result struct */ -struct BIST_result { - /* Overall test result: - * 0 Fail (any bit failed) , - * 1 Success (All bits success) - */ - bool test_result; - /* 1: true, all fail / 0: False, not all bits fail */ - bool all_bits_fail; - bool bit_i_test_result[8]; /* 0 fail / 1 success */ -}; - -/* a struct that defines tuning parameters of a byte. */ -struct tuning_position { - u8 phase; /* DQS phase */ - u8 unit; /* DQS unit delay */ - u32 bits_delay; /* Bits deskew in this byte */ -}; - -/* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */ -const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12}; - -static u8 BIST_error_max = 1; -static u32 BIST_seed = 0x1234ABCD; - -static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl) -{ - u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK; - u8 nb_bytes = NUM_BYTES; - - switch (data_bus) { - case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF: - nb_bytes /= 2; - break; - case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER: - nb_bytes /= 4; - break; - default: - break; - } - - return nb_bytes; -} - -static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl) -{ - /* Count bank address bits */ - u8 bits = 0; - u32 reg, val; - - reg = readl(&ctl->addrmap1); - /* addrmap1.addrmap_bank_b1 */ - val = (reg & GENMASK(5, 0)) >> 0; - if (val <= 31) - bits++; - /* addrmap1.addrmap_bank_b2 */ - val = (reg & GENMASK(13, 8)) >> 8; - if (val <= 31) - bits++; - /* addrmap1.addrmap_bank_b3 */ - val = (reg & GENMASK(21, 16)) >> 16; - if (val <= 31) - bits++; - - return bits; -} - -static u8 get_nb_col(struct stm32mp1_ddrctl *ctl) -{ - u8 bits; - u32 reg, val; - - /* Count column address bits, start at 2 for b0 and b1 (fixed) */ - bits = 2; - - reg = readl(&ctl->addrmap2); - /* addrmap2.addrmap_col_b2 */ - val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 7) - bits++; - /* addrmap2.addrmap_col_b3 */ - val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 7) - bits++; - /* addrmap2.addrmap_col_b4 */ - val = (reg & GENMASK(19, 16)) >> 16; - if (val <= 7) - bits++; - /* addrmap2.addrmap_col_b5 */ - val = (reg & GENMASK(27, 24)) >> 24; - if (val <= 7) - bits++; - - reg = readl(&ctl->addrmap3); - /* addrmap3.addrmap_col_b6 */ - val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 7) - bits++; - /* addrmap3.addrmap_col_b7 */ - val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 7) - bits++; - /* addrmap3.addrmap_col_b8 */ - val = (reg & GENMASK(19, 16)) >> 16; - if (val <= 7) - bits++; - /* addrmap3.addrmap_col_b9 */ - val = (reg & GENMASK(27, 24)) >> 24; - if (val <= 7) - bits++; - - reg = readl(&ctl->addrmap4); - /* addrmap4.addrmap_col_b10 */ - val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 7) - bits++; - /* addrmap4.addrmap_col_b11 */ - val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 7) - bits++; - - return bits; -} - -static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) -{ - /* Count row address bits */ - u8 bits = 0; - u32 reg, val; - - reg = readl(&ctl->addrmap5); - /* addrmap5.addrmap_row_b0 */ - val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 11) - bits++; - /* addrmap5.addrmap_row_b1 */ - val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 11) - bits++; - /* addrmap5.addrmap_row_b2_10 */ - val = (reg & GENMASK(19, 16)) >> 16; - if (val <= 11) - bits += 9; - else - printf("warning: addrmap5.addrmap_row_b2_10 not supported\n"); - /* addrmap5.addrmap_row_b11 */ - val = (reg & GENMASK(27, 24)) >> 24; - if (val <= 11) - bits++; - - reg = readl(&ctl->addrmap6); - /* addrmap6.addrmap_row_b12 */ - val = (reg & GENMASK(3, 0)) >> 0; - if (val <= 7) - bits++; - /* addrmap6.addrmap_row_b13 */ - val = (reg & GENMASK(11, 8)) >> 8; - if (val <= 7) - bits++; - /* addrmap6.addrmap_row_b14 */ - val = (reg & GENMASK(19, 16)) >> 16; - if (val <= 7) - bits++; - /* addrmap6.addrmap_row_b15 */ - val = (reg & GENMASK(27, 24)) >> 24; - if (val <= 7) - bits++; - - return bits; -} - -static void itm_soft_reset(struct stm32mp1_ddrphy *phy) -{ - stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); -} - -/* Read DQ unit delay register and provides the retrieved value for DQS - * We are assuming that we have the same delay when clocking - * by DQS and when clocking by DQSN - */ -static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit) -{ - u32 index; - u32 addr = DXNDQTR(phy, byte); - - /* We are assuming that we have the same delay when clocking by DQS - * and when clocking by DQSN : use only the low bits - */ - index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)) - & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK; - - log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index); - - return index; -} - -/* Sets the DQS phase delay for a byte lane. - *phase delay is specified by giving the index of the desired delay - * in the dx_dll_phase array. - */ -static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx) -{ - u8 sdphase_val = 0; - - /* Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */ - sdphase_val = dx_dll_phase[phase_idx]; - clrsetbits_le32(DXNDLLCR(phy, byte), - DDRPHYC_DXNDLLCR_SDPHASE_MASK, - sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT); -} - -/* Sets the DQS unit delay for a byte lane. - * unit delay is specified by giving the index of the desired delay - * for dgsdly and dqsndly (same value). - */ -static void DQS_unit_delay(struct stm32mp1_ddrphy *phy, - u8 byte, u8 unit_dly_idx) -{ - /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */ - clrsetbits_le32(DXNDQSTR(phy, byte), - DDRPHYC_DXNDQSTR_DQSDLY_MASK | - DDRPHYC_DXNDQSTR_DQSNDLY_MASK, - (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) | - (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT)); - - /* After changing this value, an ITM soft reset (PIR.ITMSRST=1, - * plus PIR.INIT=1) must be issued. - */ - stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST); -} - -/* Sets the DQ unit delay for a bit line in particular byte lane. - * unit delay is specified by giving the desired delay - */ -static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy, - u8 byte, u8 bit, - u8 dq_delay_index) -{ - u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2); - - /* same value on delay for clock DQ an DQS_b */ - clrsetbits_le32(DXNDQTR(phy, byte), - DDRPHYC_DXNDQTR_DQDLY_MASK - << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit), - dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit)); -} - -static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy, - u8 byte, u8 r0dgsl_idx) -{ - clrsetbits_le32(DXNDQSTR(phy, byte), - DDRPHYC_DXNDQSTR_R0DGSL_MASK, - r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT); -} - -static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy, - u8 byte, u8 r0dgps_idx) -{ - clrsetbits_le32(DXNDQSTR(phy, byte), - DDRPHYC_DXNDQSTR_R0DGPS_MASK, - r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT); -} - -/* Basic BIST configuration for data lane tests. */ -static void config_BIST(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy) -{ - u8 nb_bank = get_nb_bank(ctl); - u8 nb_row = get_nb_row(ctl); - u8 nb_col = get_nb_col(ctl); - - /* Selects the SDRAM bank address to be used during BIST. */ - u32 bbank = 0; - /* Selects the SDRAM row address to be used during BIST. */ - u32 brow = 0; - /* Selects the SDRAM column address to be used during BIST. */ - u32 bcol = 0; - /* Selects the value by which the SDRAM address is incremented - * for each write/read access. - */ - u32 bainc = 0x00000008; - /* Specifies the maximum SDRAM rank to be used during BIST. - * The default value is set to maximum ranks minus 1. - * must be 0 with single rank - */ - u32 bmrank = 0; - /* Selects the SDRAM rank to be used during BIST. - * must be 0 with single rank - */ - u32 brank = 0; - - /* Specifies the maximum SDRAM bank address to be used during - * BIST before the address & increments to the next rank. - */ - u32 bmbank = (1 << nb_bank) - 1; - /* Specifies the maximum SDRAM row address to be used during - * BIST before the address & increments to the next bank. - */ - u32 bmrow = (1 << nb_row) - 1; - /* Specifies the maximum SDRAM column address to be used during - * BIST before the address & increments to the next row. - */ - u32 bmcol = (1 << nb_col) - 1; - - u32 bmode_conf = 0x00000001; /* DRam mode */ - u32 bdxen_conf = 0x00000001; /* BIST on Data byte */ - u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */ - - /*Setup BIST for DRAM mode, and LFSR-random data pattern.*/ - /*Write BISTRR.BMODE = 1?b1;*/ - /*Write BISTRR.BDXEN = 1?b1;*/ - /*Write BISTRR.BDPAT = 2?b10;*/ - - /* reset BIST */ - writel(0x3, &phy->bistrr); - - writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17), - &phy->bistrr); - - /*Setup BIST Word Count*/ - /*Write BISTWCR.BWCNT = 16?b0008;*/ - writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */ - - writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0); - writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1); - writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2); -} - -/* Select the Byte lane to be tested by BIST. */ -static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8) -{ - clrsetbits_le32(&phy->bistrr, - DDRPHYC_BISTRR_BDXSEL_MASK, - datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT); - - /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/ - /* Write BISTRR.BDXSEL = datx8; */ -} - -/* Perform BIST Write_Read test on a byte lane and return test result. */ -static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte, - struct BIST_result *bist) -{ - bool result = true; /* BIST_SUCCESS */ - u32 cnt = 0; - u32 error = 0; - u32 val; - int ret; - - bist->test_result = true; - -run: - itm_soft_reset(phy); - - /*Perform BIST Reset*/ - /* Write BISTRR.BINST = 3?b011; */ - clrsetbits_le32(&phy->bistrr, - 0x00000007, - 0x00000003); - - /*Re-seed LFSR*/ - /* Write BISTLSR.SEED = 32'h1234ABCD; */ - if (BIST_seed) - writel(BIST_seed, &phy->bistlsr); - else - writel(rand(), &phy->bistlsr); - - /* some delay to reset BIST */ - udelay(10); - - /*Perform BIST Run*/ - clrsetbits_le32(&phy->bistrr, - 0x00000007, - 0x00000001); - /* Write BISTRR.BINST = 3?b001; */ - - /* poll on BISTGSR.BDONE and wait max 1000 us */ - ret = readl_poll_timeout(&phy->bistgsr, val, - val & DDRPHYC_BISTGSR_BDDONE, 1000); - - if (ret < 0) { - printf("warning: BIST timeout\n"); - result = false; /* BIST_FAIL; */ - /*Perform BIST Stop */ - clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002); - } else { - /*Check if received correct number of words*/ - /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */ - if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) - == readl(&phy->bistwcr)) { - /*Determine if there is a data comparison error*/ - /* if (Read BISTGSR.BDXERR = 1?b0) */ - if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR) - result = false; /* BIST_FAIL; */ - else - result = true; /* BIST_SUCCESS; */ - } else { - result = false; /* BIST_FAIL; */ - } - } - - /* loop while success */ - cnt++; - if (result && cnt != 1000) - goto run; - - if (!result) - error++; - - if (error < BIST_error_max) { - if (cnt != 1000) - goto run; - bist->test_result = true; - } else { - bist->test_result = false; - } -} - -/* After running the deskew algo, this function applies the new DQ delays - * by reading them from the array "deskew_delay"and writing in PHY registers. - * The bits that are not deskewed parfectly (too much skew on them, - * or data eye very wide) are marked in the array deskew_non_converge. - */ -static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte, - u8 deskew_delay[NUM_BYTES][8], - u8 deskew_non_converge[NUM_BYTES][8]) -{ - u8 bit_i; - u8 index; - - for (bit_i = 0; bit_i < 8; bit_i++) { - set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]); - index = DQ_unit_index(phy, byte, bit_i); - log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]", - byte, bit_i, deskew_delay[byte][bit_i], - index, index - 3); - printf("Byte %d, bit %d, DQ delay = %d", - byte, bit_i, deskew_delay[byte][bit_i]); - if (deskew_non_converge[byte][bit_i] == 1) - log_debug(" - not converged : still more skew"); - printf("\n"); - } -} - -/* DQ Bit de-skew algorithm. - * Deskews data lines as much as possible. - * 1. Add delay to DQS line until finding the failure - * (normally a hold time violation) - * 2. Reduce DQS line by small steps until finding the very first time - * we go back to "Pass" condition. - * 3. For each DQ line, Reduce DQ delay until finding the very first failure - * (normally a hold time fail) - * 4. When all bits are at their first failure delay, we can consider them - * aligned. - * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions - * at any step) - * TODO Provide a return Status. Improve doc - */ -static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, char *string) -{ - /* New DQ delay value (index), set during Deskew algo */ - u8 deskew_delay[NUM_BYTES][8]; - /*If there is still skew on a bit, mark this bit. */ - u8 deskew_non_converge[NUM_BYTES][8]; - struct BIST_result result; - s8 dqs_unit_delay_index = 0; - u8 datx8 = 0; - u8 bit_i = 0; - s8 phase_idx = 0; - s8 bit_i_delay_index = 0; - u8 success = 0; - struct tuning_position last_right_ok; - u8 force_stop = 0; - u8 fail_found; - u8 error = 0; - u8 nb_bytes = get_nb_bytes(ctl); - /* u8 last_pass_dqs_unit = 0; */ - - memset(deskew_delay, 0, sizeof(deskew_delay)); - memset(deskew_non_converge, 0, sizeof(deskew_non_converge)); - - /*Disable DQS Drift Compensation*/ - clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); - /*Disable all bytes*/ - /* Disable automatic power down of DLL and IOs when disabling - * a byte (To avoid having to add programming and delay - * for a DLL re-lock when later re-enabling a disabled Byte Lane) - */ - clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); - - /* Disable all data bytes */ - clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - /* Config the BIST block */ - config_BIST(ctl, phy); - log_debug("BIST Config done.\n"); - - /* Train each byte */ - for (datx8 = 0; datx8 < nb_bytes; datx8++) { - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - datx8 + 1, nb_bytes, error); - return TEST_FAILED; - } - log_debug("\n======================\n"); - log_debug("Start deskew byte %d .\n", datx8); - log_debug("======================\n"); - /* Enable Byte (DXNGCR, bit DXEN) */ - setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); - - /* Select the byte lane for comparison of read data */ - BIST_datx8_sel(phy, datx8); - - /* Set all DQDLYn to maximum value. All bits within the byte - * will be delayed with DQSTR = 2 instead of max = 3 - * to avoid inter bits fail influence - */ - writel(0xAAAAAAAA, DXNDQTR(phy, datx8)); - - /* Set the DQS phase delay to 90 DEG (default). - * What is defined here is the index of the desired config - * in the PHASE array. - */ - phase_idx = _90deg; - - /* Set DQS unit delay to the max value. */ - dqs_unit_delay_index = MAX_DQS_UNIT_IDX; - DQS_unit_delay(phy, datx8, dqs_unit_delay_index); - DQS_phase_delay(phy, datx8, phase_idx); - - /* Issue a DLL soft reset */ - clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST); - setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST); - - /* Test this typical init condition */ - BIST_test(phy, datx8, &result); - success = result.test_result; - - /* If the test pass in this typical condition, - * start the algo with it. - * Else, look for Pass init condition - */ - if (!success) { - log_debug("Fail at init condtion. Let's look for a good init condition.\n"); - success = 0; /* init */ - /* Make sure we start with a PASS condition before - * looking for a fail condition. - * Find the first PASS PHASE condition - */ - - /* escape if we find a PASS */ - log_debug("increase Phase idx\n"); - while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) { - DQS_phase_delay(phy, datx8, phase_idx); - BIST_test(phy, datx8, &result); - success = result.test_result; - phase_idx++; - } - /* if ended with success - * ==>> Restore the fist success condition - */ - if (success) - phase_idx--; /* because it ended with ++ */ - } - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - datx8 + 1, nb_bytes, error); - return TEST_FAILED; - } - /* We couldn't find a successful condition, its seems - * we have hold violation, lets try reduce DQS_unit Delay - */ - if (!success) { - /* We couldn't find a successful condition, its seems - * we have hold violation, lets try reduce DQS_unit - * Delay - */ - log_debug("Still fail. Try decrease DQS Unit delay\n"); - - phase_idx = 0; - dqs_unit_delay_index = 0; - DQS_phase_delay(phy, datx8, phase_idx); - - /* escape if we find a PASS */ - while (!success && - (dqs_unit_delay_index <= - MAX_DQS_UNIT_IDX)) { - DQS_unit_delay(phy, datx8, - dqs_unit_delay_index); - BIST_test(phy, datx8, &result); - success = result.test_result; - dqs_unit_delay_index++; - } - if (success) { - /* Restore the first success condition*/ - dqs_unit_delay_index--; - /* last_pass_dqs_unit = dqs_unit_delay_index;*/ - DQS_unit_delay(phy, datx8, - dqs_unit_delay_index); - } else { - /* No need to continue, - * there is no pass region. - */ - force_stop = 1; - } - } - - /* There is an initial PASS condition - * Look for the first failing condition by PHASE stepping. - * This part of the algo can finish without converging. - */ - if (force_stop) { - printf("Result: Failed "); - printf("[Cannot Deskew lines, "); - printf("there is no PASS region]\n"); - error++; - continue; - } - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - datx8 + 1, nb_bytes, error); - return TEST_FAILED; - } - - log_debug("there is a pass region for phase idx %d\n", - phase_idx); - log_debug("Step1: Find the first failing condition\n"); - /* Look for the first failing condition by PHASE stepping. - * This part of the algo can finish without converging. - */ - - /* escape if we find a fail (hold time violation) - * condition at any bit or if out of delay range. - */ - while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) { - DQS_phase_delay(phy, datx8, phase_idx); - BIST_test(phy, datx8, &result); - success = result.test_result; - phase_idx++; - } - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - datx8 + 1, nb_bytes, error); - return TEST_FAILED; - } - - /* if the loop ended with a failing condition at any bit, - * lets look for the first previous success condition by unit - * stepping (minimal delay) - */ - if (!success) { - log_debug("Fail region (PHASE) found phase idx %d\n", - phase_idx); - log_debug("Let's look for first success by DQS Unit steps\n"); - /* This part, the algo always converge */ - phase_idx--; - - /* escape if we find a success condition - * or if out of delay range. - */ - while (!success && dqs_unit_delay_index >= 0) { - DQS_unit_delay(phy, datx8, - dqs_unit_delay_index); - BIST_test(phy, datx8, &result); - success = result.test_result; - dqs_unit_delay_index--; - } - /* if the loop ended with a success condition, - * the last delay Right OK (before hold violation) - * condition is then defined as following: - */ - if (success) { - /* Hold the dely parameters of the the last - * delay Right OK condition. - * -1 to get back to current condition - */ - last_right_ok.phase = phase_idx; - /*+1 to get back to current condition */ - last_right_ok.unit = dqs_unit_delay_index + 1; - last_right_ok.bits_delay = 0xFFFFFFFF; - log_debug("Found %d\n", dqs_unit_delay_index); - } else { - /* the last OK condition is then with the - * previous phase_idx. - * -2 instead of -1 because at the last - * iteration of the while(), - * we incremented phase_idx - */ - last_right_ok.phase = phase_idx - 1; - /* Nominal+1. Because we want the previous - * delay after reducing the phase delay. - */ - last_right_ok.unit = 1; - last_right_ok.bits_delay = 0xFFFFFFFF; - log_debug("Not Found : try previous phase %d\n", - phase_idx - 1); - - DQS_phase_delay(phy, datx8, phase_idx - 1); - dqs_unit_delay_index = 0; - success = true; - while (success && - (dqs_unit_delay_index < - MAX_DQS_UNIT_IDX)) { - DQS_unit_delay(phy, datx8, - dqs_unit_delay_index); - BIST_test(phy, datx8, &result); - success = result.test_result; - dqs_unit_delay_index++; - log_debug("dqs_unit_delay_index = %d, result = %d\n", - dqs_unit_delay_index, success); - } - - if (!success) { - last_right_ok.unit = - dqs_unit_delay_index - 1; - } else { - last_right_ok.unit = 0; - log_debug("ERROR: failed region not FOUND"); - } - } - } else { - /* we can't find a failing condition at all bits - * ==> Just hold the last test condition - * (the max DQS delay) - * which is the most likely, - * the closest to a hold violation - * If we can't find a Fail condition after - * the Pass region, stick at this position - * In order to have max chances to find a fail - * when reducing DQ delays. - */ - last_right_ok.phase = MAX_DQS_PHASE_IDX; - last_right_ok.unit = MAX_DQS_UNIT_IDX; - last_right_ok.bits_delay = 0xFFFFFFFF; - log_debug("Can't find the a fail condition\n"); - } - - /* step 2: - * if we arrive at this stage, it means that we found the last - * Right OK condition (by tweeking the DQS delay). Or we simply - * pushed DQS delay to the max - * This means that by reducing the delay on some DQ bits, - * we should find a failing condition. - */ - printf("Byte %d, DQS unit = %d, phase = %d\n", - datx8, last_right_ok.unit, last_right_ok.phase); - log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n", - last_right_ok.unit, last_right_ok.phase, - last_right_ok.bits_delay); - - /* Restore the last_right_ok condtion. */ - DQS_unit_delay(phy, datx8, last_right_ok.unit); - DQS_phase_delay(phy, datx8, last_right_ok.phase); - writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8)); - - /* train each bit - * reduce delay on each bit, and perform a write/read test - * and stop at the very first time it fails. - * the goal is the find the first failing condition - * for each bit. - * When we achieve this condition< for all the bits, - * we are sure they are aligned (+/- step resolution) - */ - fail_found = 0; - for (bit_i = 0; bit_i < 8; bit_i++) { - if (ctrlc()) { - sprintf(string, - "interrupted at byte %d/%d, error=%d", - datx8 + 1, nb_bytes, error); - return error; - } - log_debug("deskewing bit %d:\n", bit_i); - success = 1; /* init */ - /* Set all DQDLYn to maximum value. - * Only bit_i will be down-delayed - * ==> if we have a fail, it will be definitely - * from bit_i - */ - writel(0xFFFFFFFF, DXNDQTR(phy, datx8)); - /* Arriving at this stage, - * we have a success condition with delay = 3; - */ - bit_i_delay_index = 3; - - /* escape if bit delay is out of range or - * if a fatil occurs - */ - while ((bit_i_delay_index >= 0) && success) { - set_DQ_unit_delay(phy, datx8, - bit_i, - bit_i_delay_index); - BIST_test(phy, datx8, &result); - success = result.test_result; - bit_i_delay_index--; - } - - /* if escape with a fail condition - * ==> save this position for bit_i - */ - if (!success) { - /* save the delay position. - * Add 1 because the while loop ended with a --, - * and that we need to hold the last success - * delay - */ - deskew_delay[datx8][bit_i] = - bit_i_delay_index + 2; - if (deskew_delay[datx8][bit_i] > 3) - deskew_delay[datx8][bit_i] = 3; - - /* A flag that states we found at least a fail - * at one bit. - */ - fail_found = 1; - log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n", - bit_i, bit_i_delay_index + 1, - datx8, bit_i, - deskew_delay[datx8][bit_i]); - } else { - /* if we can find a success condition by - * back-delaying this bit, just set the delay - * to 0 (the best deskew - * possible) and mark the bit. - */ - deskew_delay[datx8][bit_i] = 0; - /* set a flag that will be used later - * in the report. - */ - deskew_non_converge[datx8][bit_i] = 1; - log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n", - bit_i, datx8, bit_i, - deskew_delay[datx8][bit_i]); - } - } - log_debug("**********byte %d tuning complete************\n", - datx8); - /* If we can't find any failure by back delaying DQ lines, - * hold the default values - */ - if (!fail_found) { - for (bit_i = 0; bit_i < 8; bit_i++) - deskew_delay[datx8][bit_i] = 0; - log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n"); - } - - apply_deskew_results(phy, datx8, deskew_delay, - deskew_non_converge); - /* Restore nominal value for DQS delay */ - DQS_phase_delay(phy, datx8, 3); - DQS_unit_delay(phy, datx8, 3); - /* disable byte after byte bits deskew */ - clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN); - } /* end of byte deskew */ - - /* re-enable all data bytes */ - setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); - setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); - setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); - setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - if (error) { - sprintf(string, "error = %d", error); - return TEST_FAILED; - } - - return TEST_PASSED; -} /* end function */ - -/* Trim DQS timings and set it in the centre of data eye. - * Look for a PPPPF region, then look for a FPPP region and finally select - * the mid of the FPPPPPF region - */ -static enum test_result eye_training(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, char *string) -{ - /*Stores the DQS trim values (PHASE index, unit index) */ - u8 eye_training_val[NUM_BYTES][2]; - u8 byte = 0; - struct BIST_result result; - s8 dqs_unit_delay_index = 0; - s8 phase_idx = 0; - s8 dqs_unit_delay_index_pass = 0; - s8 phase_idx_pass = 0; - u8 success = 0; - u8 left_phase_bound_found, right_phase_bound_found; - u8 left_unit_bound_found, right_unit_bound_found; - u8 left_bound_found, right_bound_found; - struct tuning_position left_bound, right_bound; - u8 error = 0; - u8 nb_bytes = get_nb_bytes(ctl); - - /*Disable DQS Drift Compensation*/ - clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); - /*Disable all bytes*/ - /* Disable automatic power down of DLL and IOs when disabling a byte - * (To avoid having to add programming and delay - * for a DLL re-lock when later re-enabling a disabled Byte Lane) - */ - clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); - - /*Disable all data bytes */ - clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - /* Config the BIST block */ - config_BIST(ctl, phy); - - for (byte = 0; byte < nb_bytes; byte++) { - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - byte + 1, nb_bytes, error); - return TEST_FAILED; - } - right_bound.phase = 0; - right_bound.unit = 0; - - left_bound.phase = 0; - left_bound.unit = 0; - - left_phase_bound_found = 0; - right_phase_bound_found = 0; - - left_unit_bound_found = 0; - right_unit_bound_found = 0; - - left_bound_found = 0; - right_bound_found = 0; - - /* Enable Byte (DXNGCR, bit DXEN) */ - setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN); - - /* Select the byte lane for comparison of read data */ - BIST_datx8_sel(phy, byte); - - /* Set DQS phase delay to the nominal value. */ - phase_idx = _90deg; - phase_idx_pass = phase_idx; - - /* Set DQS unit delay to the nominal value. */ - dqs_unit_delay_index = 3; - dqs_unit_delay_index_pass = dqs_unit_delay_index; - success = 0; - - log_debug("STEP0: Find Init delay\n"); - /* STEP0: Find Init delay: a delay that put the system - * in a "Pass" condition then (TODO) update - * dqs_unit_delay_index_pass & phase_idx_pass - */ - DQS_unit_delay(phy, byte, dqs_unit_delay_index); - DQS_phase_delay(phy, byte, phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - /* If we have a fail in the nominal condition */ - if (!success) { - /* Look at the left */ - while (phase_idx >= 0 && !success) { - phase_idx--; - DQS_phase_delay(phy, byte, phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - } - } - if (!success) { - /* if we can't find pass condition, - * then look at the right - */ - phase_idx = _90deg; - while (phase_idx <= MAX_DQS_PHASE_IDX && - !success) { - phase_idx++; - DQS_phase_delay(phy, byte, - phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - } - } - /* save the pass condition */ - if (success) { - phase_idx_pass = phase_idx; - } else { - printf("Result: Failed "); - printf("[Cannot DQS timings, "); - printf("there is no PASS region]\n"); - error++; - continue; - } - - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - byte + 1, nb_bytes, error); - return TEST_FAILED; - } - log_debug("STEP1: Find LEFT PHASE DQS Bound\n"); - /* STEP1: Find LEFT PHASE DQS Bound */ - while ((phase_idx >= 0) && - (phase_idx <= MAX_DQS_PHASE_IDX) && - !left_phase_bound_found) { - DQS_unit_delay(phy, byte, - dqs_unit_delay_index); - DQS_phase_delay(phy, byte, - phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - - /*TODO: Manage the case were at the beginning - * there is already a fail - */ - if (!success) { - /* the last pass condition */ - left_bound.phase = ++phase_idx; - left_phase_bound_found = 1; - } else if (success) { - phase_idx--; - } - } - if (!left_phase_bound_found) { - left_bound.phase = 0; - phase_idx = 0; - } - /* If not found, lets take 0 */ - - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - byte + 1, nb_bytes, error); - return TEST_FAILED; - } - log_debug("STEP2: Find UNIT left bound\n"); - /* STEP2: Find UNIT left bound */ - while ((dqs_unit_delay_index >= 0) && - !left_unit_bound_found) { - DQS_unit_delay(phy, byte, - dqs_unit_delay_index); - DQS_phase_delay(phy, byte, phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - if (!success) { - left_bound.unit = - ++dqs_unit_delay_index; - left_unit_bound_found = 1; - left_bound_found = 1; - } else if (success) { - dqs_unit_delay_index--; - } - } - - /* If not found, lets take 0 */ - if (!left_unit_bound_found) - left_bound.unit = 0; - - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - byte + 1, nb_bytes, error); - return TEST_FAILED; - } - log_debug("STEP3: Find PHase right bound\n"); - /* STEP3: Find PHase right bound, start with "pass" - * condition - */ - - /* Set DQS phase delay to the pass value. */ - phase_idx = phase_idx_pass; - - /* Set DQS unit delay to the pass value. */ - dqs_unit_delay_index = dqs_unit_delay_index_pass; - - while ((phase_idx <= MAX_DQS_PHASE_IDX) && - !right_phase_bound_found) { - DQS_unit_delay(phy, byte, - dqs_unit_delay_index); - DQS_phase_delay(phy, byte, phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - if (!success) { - /* the last pass condition */ - right_bound.phase = --phase_idx; - right_phase_bound_found = 1; - } else if (success) { - phase_idx++; - } - } - - /* If not found, lets take the max value */ - if (!right_phase_bound_found) { - right_bound.phase = MAX_DQS_PHASE_IDX; - phase_idx = MAX_DQS_PHASE_IDX; - } - - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d, error=%d", - byte + 1, nb_bytes, error); - return TEST_FAILED; - } - log_debug("STEP4: Find UNIT right bound\n"); - /* STEP4: Find UNIT right bound */ - while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) && - !right_unit_bound_found) { - DQS_unit_delay(phy, byte, - dqs_unit_delay_index); - DQS_phase_delay(phy, byte, phase_idx); - BIST_test(phy, byte, &result); - success = result.test_result; - if (!success) { - right_bound.unit = - --dqs_unit_delay_index; - right_unit_bound_found = 1; - right_bound_found = 1; - } else if (success) { - dqs_unit_delay_index++; - } - } - /* If not found, lets take the max value */ - if (!right_unit_bound_found) - right_bound.unit = MAX_DQS_UNIT_IDX; - - /* If we found a regular FAil Pass FAil pattern - * FFPPPPPPFF - * OR PPPPPFF Or FFPPPPP - */ - - if (left_bound_found || right_bound_found) { - eye_training_val[byte][0] = (right_bound.phase + - left_bound.phase) / 2; - eye_training_val[byte][1] = (right_bound.unit + - left_bound.unit) / 2; - - /* If we already lost 1/2PHASE Tuning, - * let's try to recover by ++ on unit - */ - if (((right_bound.phase + left_bound.phase) % 2 == 1) && - eye_training_val[byte][1] != MAX_DQS_UNIT_IDX) - eye_training_val[byte][1]++; - log_debug("** found phase : %d - %d & unit %d - %d\n", - right_bound.phase, left_bound.phase, - right_bound.unit, left_bound.unit); - log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n", - eye_training_val[byte][0], - eye_training_val[byte][1]); - } else { - /* PPPPPPPPPP, we're already good. - * Set nominal values. - */ - eye_training_val[byte][0] = 3; - eye_training_val[byte][1] = 3; - } - DQS_phase_delay(phy, byte, eye_training_val[byte][0]); - DQS_unit_delay(phy, byte, eye_training_val[byte][1]); - - printf("Byte %d, DQS unit = %d, phase = %d\n", - byte, - eye_training_val[byte][1], - eye_training_val[byte][0]); - } - - if (error) { - sprintf(string, "error = %d", error); - return TEST_FAILED; - } - - return TEST_PASSED; -} - -static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte) -{ - u8 i = 0; - - printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n ", - byte); - - for (i = 0; i < 8; i++) - printf("%d ", DQ_unit_index(phy, byte, i)); - printf("\n"); - - printf("dxndllcr: [%08x] val:%08x\n", - DXNDLLCR(phy, byte), - readl(DXNDLLCR(phy, byte))); - printf("dxnqdstr: [%08x] val:%08x\n", - DXNDQSTR(phy, byte), - readl(DXNDQSTR(phy, byte))); - printf("dxndqtr: [%08x] val:%08x\n", - DXNDQTR(phy, byte), - readl(DXNDQTR(phy, byte))); -} - -/* analyse the dgs gating log table, and determine the midpoint.*/ -static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte, - u8 dqs_gating[NUM_BYTES] - [MAX_GSL_IDX + 1] - [MAX_GPS_IDX + 1]) -{ - /* stores the dqs gate values (gsl index, gps index) */ - u8 dqs_gate_values[NUM_BYTES][2]; - u8 gsl_idx, gps_idx = 0; - u8 left_bound_idx[2] = {0, 0}; - u8 right_bound_idx[2] = {0, 0}; - u8 left_bound_found = 0; - u8 right_bound_found = 0; - u8 intermittent = 0; - u8 value; - - for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) { - for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) { - value = dqs_gating[byte][gsl_idx][gps_idx]; - if (value == 1 && left_bound_found == 0) { - left_bound_idx[0] = gsl_idx; - left_bound_idx[1] = gps_idx; - left_bound_found = 1; - } else if (value == 0 && - left_bound_found == 1 && - !right_bound_found) { - if (gps_idx == 0) { - right_bound_idx[0] = gsl_idx - 1; - right_bound_idx[1] = MAX_GPS_IDX; - } else { - right_bound_idx[0] = gsl_idx; - right_bound_idx[1] = gps_idx - 1; - } - right_bound_found = 1; - } else if (value == 1 && - right_bound_found == 1) { - intermittent = 1; - } - } - } - - /* if only ppppppp is found, there is no mid region. */ - if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 && - right_bound_idx[0] == 0 && right_bound_idx[1] == 0) - intermittent = 1; - - /*if we found a regular fail pass fail pattern ffppppppff - * or pppppff or ffppppp - */ - if (!intermittent) { - /*if we found a regular fail pass fail pattern ffppppppff - * or pppppff or ffppppp - */ - if (left_bound_found || right_bound_found) { - log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n", - left_bound_found, - right_bound_idx[0], left_bound_idx[0], - right_bound_found, - right_bound_idx[1], left_bound_idx[1]); - dqs_gate_values[byte][0] = - (right_bound_idx[0] + left_bound_idx[0]) / 2; - dqs_gate_values[byte][1] = - (right_bound_idx[1] + left_bound_idx[1]) / 2; - /* if we already lost 1/2gsl tuning, - * let's try to recover by ++ on gps - */ - if (((right_bound_idx[0] + - left_bound_idx[0]) % 2 == 1) && - dqs_gate_values[byte][1] != MAX_GPS_IDX) - dqs_gate_values[byte][1]++; - /* if we already lost 1/2gsl tuning and gps is on max*/ - else if (((right_bound_idx[0] + - left_bound_idx[0]) % 2 == 1) && - dqs_gate_values[byte][1] == MAX_GPS_IDX) { - dqs_gate_values[byte][1] = 0; - dqs_gate_values[byte][0]++; - } - /* if we have gsl left and write limit too close - * (difference=1) - */ - if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) { - dqs_gate_values[byte][1] = (left_bound_idx[1] + - right_bound_idx[1] + - 4) / 2; - if (dqs_gate_values[byte][1] >= 4) { - dqs_gate_values[byte][0] = - right_bound_idx[0]; - dqs_gate_values[byte][1] -= 4; - } else { - dqs_gate_values[byte][0] = - left_bound_idx[0]; - } - } - log_debug("*******calculating mid region: system latency: %d phase: %d********\n", - dqs_gate_values[byte][0], - dqs_gate_values[byte][1]); - log_debug("*******the nominal values were system latency: 0 phase: 2*******\n"); - } - } else { - /* if intermitant, restore defaut values */ - log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n"); - dqs_gate_values[byte][0] = 0; - dqs_gate_values[byte][1] = 2; - } - set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]); - set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]); - printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n", - byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]); - - /* return 0 if intermittent or if both left_bound - * and right_bound are not found - */ - return !(intermittent || (left_bound_found && right_bound_found)); -} - -static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, - char *string) -{ - /* stores the log of pass/fail */ - u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1]; - u8 byte, gsl_idx, gps_idx = 0; - struct BIST_result result; - u8 success = 0; - u8 nb_bytes = get_nb_bytes(ctl); - - memset(dqs_gating, 0x0, sizeof(dqs_gating)); - - /*disable dqs drift compensation*/ - clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); - /*disable all bytes*/ - /* disable automatic power down of dll and ios when disabling a byte - * (to avoid having to add programming and delay - * for a dll re-lock when later re-enabling a disabled byte lane) - */ - clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX); - - /* disable all data bytes */ - clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN); - clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN); - - /* config the bist block */ - config_BIST(ctl, phy); - - for (byte = 0; byte < nb_bytes; byte++) { - if (ctrlc()) { - sprintf(string, "interrupted at byte %d/%d", - byte + 1, nb_bytes); - return TEST_FAILED; - } - /* enable byte x (dxngcr, bit dxen) */ - setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN); - - /* select the byte lane for comparison of read data */ - BIST_datx8_sel(phy, byte); - for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) { - for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) { - if (ctrlc()) { - sprintf(string, - "interrupted at byte %d/%d", - byte + 1, nb_bytes); - return TEST_FAILED; - } - /* write cfg to dxndqstr */ - set_r0dgsl_delay(phy, byte, gsl_idx); - set_r0dgps_delay(phy, byte, gps_idx); - - BIST_test(phy, byte, &result); - success = result.test_result; - if (success) - dqs_gating[byte][gsl_idx][gps_idx] = 1; - itm_soft_reset(phy); - } - } - set_midpoint_read_dqs_gating(phy, byte, dqs_gating); - /* dummy reads */ - readl(0xc0000000); - readl(0xc0000000); - } - - /* re-enable drift compensation */ - /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */ - return TEST_PASSED; -} - -/**************************************************************** - * TEST - **************************************************************** - */ -static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, - char *string, int argc, - char *argv[]) -{ - u32 rfshctl3 = readl(&ctl->rfshctl3); - u32 pwrctl = readl(&ctl->pwrctl); - u32 derateen = readl(&ctl->derateen); - enum test_result res; - - writel(0x0, &ctl->derateen); - stm32mp1_refresh_disable(ctl); - - res = read_dqs_gating(ctl, phy, string); - - stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); - writel(derateen, &ctl->derateen); - - return res; -} - -static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, - char *string, int argc, char *argv[]) -{ - u32 rfshctl3 = readl(&ctl->rfshctl3); - u32 pwrctl = readl(&ctl->pwrctl); - u32 derateen = readl(&ctl->derateen); - enum test_result res; - - writel(0x0, &ctl->derateen); - stm32mp1_refresh_disable(ctl); - - res = bit_deskew(ctl, phy, string); - - stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); - writel(derateen, &ctl->derateen); - - return res; -} - -static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, - char *string, int argc, char *argv[]) -{ - u32 rfshctl3 = readl(&ctl->rfshctl3); - u32 pwrctl = readl(&ctl->pwrctl); - u32 derateen = readl(&ctl->derateen); - enum test_result res; - - writel(0x0, &ctl->derateen); - stm32mp1_refresh_disable(ctl); - - res = eye_training(ctl, phy, string); - - stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl); - writel(derateen, &ctl->derateen); - - return res; -} - -static enum test_result do_display(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, - char *string, int argc, char *argv[]) -{ - int byte; - u8 nb_bytes = get_nb_bytes(ctl); - - for (byte = 0; byte < nb_bytes; byte++) - display_reg_results(phy, byte); - - return TEST_PASSED; -} - -static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl, - struct stm32mp1_ddrphy *phy, - char *string, int argc, char *argv[]) -{ - unsigned long value; - - if (argc > 0) { - if (strict_strtoul(argv[0], 0, &value) < 0) { - sprintf(string, "invalid nbErr %s", argv[0]); - return TEST_FAILED; - } - BIST_error_max = value; - } - if (argc > 1) { - if (strict_strtoul(argv[1], 0, &value) < 0) { - sprintf(string, "invalid Seed %s", argv[1]); - return TEST_FAILED; - } - BIST_seed = value; - } - printf("Bist.nbErr = %d\n", BIST_error_max); - if (BIST_seed) - printf("Bist.Seed = 0x%x\n", BIST_seed); - else - printf("Bist.Seed = random\n"); - - return TEST_PASSED; -} - -/**************************************************************** - * TEST Description - **************************************************************** - */ - -const struct test_desc tuning[] = { - {do_read_dqs_gating, "Read DQS gating", - "software read DQS Gating", "", 0 }, - {do_bit_deskew, "Bit de-skew", "", "", 0 }, - {do_eye_training, "Eye Training", "or DQS training", "", 0 }, - {do_display, "Display registers", "", "", 0 }, - {do_bist_config, "Bist config", "[nbErr] [seed]", - "configure Bist test", 2}, -}; - -const int tuning_nb = ARRAY_SIZE(tuning); From d71587c2ab5699ac07b6332e4b3245d90cd091f4 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:17 +0100 Subject: [PATCH 21/31] Convert CONFIG_LCD_DT_SIMPLEFB to Kconfig This converts the following to Kconfig: CONFIG_LCD_DT_SIMPLEFB This patch also renames this config to CONFIG_FDT_SIMPLEFB as the code in common/lcd_simplefb.c support CONFIG_LCD and CONFIG_VIDEO. Signed-off-by: Patrick Delaunay Reviewed-by: Matthias Brugger --- common/Kconfig | 9 +++++++++ common/Makefile | 2 +- configs/rpi_0_w_defconfig | 1 + configs/rpi_2_defconfig | 1 + configs/rpi_3_32b_defconfig | 1 + configs/rpi_3_b_plus_defconfig | 1 + configs/rpi_3_defconfig | 1 + configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + configs/rpi_arm64_defconfig | 1 + configs/rpi_defconfig | 1 + include/configs/rpi.h | 1 - scripts/config_whitelist.txt | 1 - 13 files changed, 19 insertions(+), 3 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index fede7e4021..176fda9449 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -776,3 +776,12 @@ config SPL_IMAGE_SIGN_INFO Enable image_sign_info helper functions in SPL. endif + +config FDT_SIMPLEFB + bool "FDT tools for simplefb support" + depends on OF_LIBFDT + help + Enable the fdt tools to manage the simple fb nodes in device tree. + These functions can be used by board to indicate to the OS + the presence of the simple frame buffer with associated reserved + memory diff --git a/common/Makefile b/common/Makefile index c500bcd7d8..fed7e482e6 100644 --- a/common/Makefile +++ b/common/Makefile @@ -40,7 +40,7 @@ ifndef CONFIG_DM_VIDEO obj-$(CONFIG_LCD) += lcd.o lcd_console.o endif obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o -obj-$(CONFIG_LCD_DT_SIMPLEFB) += lcd_simplefb.o +obj-$(CONFIG_FDT_SIMPLEFB) += lcd_simplefb.o obj-$(CONFIG_MENU) += menu.o obj-$(CONFIG_UPDATE_COMMON) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 6d76d12910..195541c6e7 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -13,6 +13,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 1931607132..eb63fbdd8d 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -14,6 +14,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 060fd36da5..46102899f0 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -15,6 +15,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 0a69f97342..91b63b6272 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -14,6 +14,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 8016fe1d55..528b12ea5b 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -14,6 +14,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 990589de64..88f7504a60 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -12,6 +12,7 @@ CONFIG_PREBOOT="pci enum; usb start;" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 0720505c6a..59a7103154 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -12,6 +12,7 @@ CONFIG_PREBOOT="pci enum; usb start;" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 06ae3e93b2..67dbf094ef 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -12,6 +12,7 @@ CONFIG_PREBOOT="pci enum; usb start;" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 8acf04d0e4..0baef3b6ab 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -13,6 +13,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 55768a46da..bc907acd5f 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -44,7 +44,6 @@ /* GPIO */ #define CONFIG_BCM2835_GPIO /* LCD */ -#define CONFIG_LCD_DT_SIMPLEFB #define CONFIG_VIDEO_BCM2835 /* DFU over USB/UDC */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b9c1c61e13..1e1ef76175 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -699,7 +699,6 @@ CONFIG_LBA48 CONFIG_LBDAF CONFIG_LCD_ALIGNMENT CONFIG_LCD_BMP_RLE8 -CONFIG_LCD_DT_SIMPLEFB CONFIG_LCD_INFO CONFIG_LCD_INFO_BELOW_LOGO CONFIG_LCD_IN_PSRAM From 4ca979e3148d8ecffaad6212871d645162a13ca0 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:18 +0100 Subject: [PATCH 22/31] common: rename lcd_simplefb.c file to fdt_simplefb.c Rename the file lcd_simplefb.c to fdt_simplefb.c to be aligned with the configuration name and with the associated include file ./include/fdt_simplefb.h Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- common/Makefile | 2 +- common/{lcd_simplefb.c => fdt_simplefb.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename common/{lcd_simplefb.c => fdt_simplefb.c} (100%) diff --git a/common/Makefile b/common/Makefile index fed7e482e6..24be05c368 100644 --- a/common/Makefile +++ b/common/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o obj-$(CONFIG_CMD_BEDBUG) += bedbug.o +obj-$(CONFIG_FDT_SIMPLEFB) += fdt_simplefb.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_MII) += miiphyutil.o obj-$(CONFIG_CMD_MII) += miiphyutil.o @@ -40,7 +41,6 @@ ifndef CONFIG_DM_VIDEO obj-$(CONFIG_LCD) += lcd.o lcd_console.o endif obj-$(CONFIG_LCD_ROTATION) += lcd_console_rotation.o -obj-$(CONFIG_FDT_SIMPLEFB) += lcd_simplefb.o obj-$(CONFIG_MENU) += menu.o obj-$(CONFIG_UPDATE_COMMON) += update.o obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o diff --git a/common/lcd_simplefb.c b/common/fdt_simplefb.c similarity index 100% rename from common/lcd_simplefb.c rename to common/fdt_simplefb.c From fded97adcedb4c77927d06aad7a7d816059eeeab Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:19 +0100 Subject: [PATCH 23/31] common: rename functions lcd_dt_simplefb to fdt_simplefb Rename the function named lcd_dt_simplefb* to fdt_simplefb* to be aligned with the associated file name fdt_simplefb.h/fdt_simplefb.c Signed-off-by: Patrick Delaunay Reviewed-by: Matthias Brugger --- board/raspberrypi/rpi/rpi.c | 2 +- common/fdt_simplefb.c | 10 +++++----- include/fdt_simplefb.h | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 55afaa54d9..cd7d6df2a5 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -505,7 +505,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer"); if (node < 0) - lcd_dt_simplefb_add_node(blob); + fdt_simplefb_add_node(blob); #ifdef CONFIG_EFI_LOADER /* Reserve the spin table */ diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c index 1650615cdb..32173030ab 100644 --- a/common/fdt_simplefb.c +++ b/common/fdt_simplefb.c @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int lcd_dt_simplefb_configure_node(void *blob, int off) +static int fdt_simplefb_configure_node(void *blob, int off) { int xsize, ysize; int bpix; /* log2 of bits per pixel */ @@ -58,7 +58,7 @@ static int lcd_dt_simplefb_configure_node(void *blob, int off) xsize * (1 << bpix) / 8, name); } -int lcd_dt_simplefb_add_node(void *blob) +int fdt_simplefb_add_node(void *blob) { static const char compat[] = "simple-framebuffer"; static const char disabled[] = "disabled"; @@ -76,10 +76,10 @@ int lcd_dt_simplefb_add_node(void *blob) if (ret < 0) return -1; - return lcd_dt_simplefb_configure_node(blob, off); + return fdt_simplefb_configure_node(blob, off); } -int lcd_dt_simplefb_enable_existing_node(void *blob) +int fdt_simplefb_enable_existing_node(void *blob) { int off; @@ -87,5 +87,5 @@ int lcd_dt_simplefb_enable_existing_node(void *blob) if (off < 0) return -1; - return lcd_dt_simplefb_configure_node(blob, off); + return fdt_simplefb_configure_node(blob, off); } diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h index 7cc305e1fd..7e54723591 100644 --- a/include/fdt_simplefb.h +++ b/include/fdt_simplefb.h @@ -8,6 +8,6 @@ #ifndef _FDT_SIMPLEFB_H_ #define _FDT_SIMPLEFB_H_ -int lcd_dt_simplefb_add_node(void *blob); -int lcd_dt_simplefb_enable_existing_node(void *blob); +int fdt_simplefb_add_node(void *blob); +int fdt_simplefb_enable_existing_node(void *blob); #endif From 2e2e6d8cacbc80f2da0ce8f1afca5ed24020b331 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:20 +0100 Subject: [PATCH 24/31] video: Add video_is_active function Add the helper function video_is_active() to test if one video device is active. This function can be used in board code to execute operation only when the display is probed / really used. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/video/video-uclass.c | 14 ++++++++++++++ include/video.h | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 9f8cf6ef2a..43ebb3c565 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -228,6 +228,20 @@ void video_sync_all(void) } } +bool video_is_active(void) +{ + struct udevice *dev; + + for (uclass_find_first_device(UCLASS_VIDEO, &dev); + dev; + uclass_find_next_device(&dev)) { + if (device_active(dev)) + return true; + } + + return false; +} + int video_get_xsize(struct udevice *dev) { struct video_priv *priv = dev_get_uclass_priv(dev); diff --git a/include/video.h b/include/video.h index f14fb15f84..5ac1387a39 100644 --- a/include/video.h +++ b/include/video.h @@ -276,6 +276,13 @@ static inline int video_sync_copy_all(struct udevice *dev) #endif +/** + * video_is_active() - Test if one video device it active + * + * @return true if at least one video device is active, else false. + */ +bool video_is_active(void); + #ifndef CONFIG_DM_VIDEO /* Video functions */ From 77debf61ef271957515de00a78ed5486c164f850 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:21 +0100 Subject: [PATCH 25/31] common: add fdt_simplefb_enable_and_mem_rsv function Add a new function to activate an existing simple frame buffer node and add the associated reserved memory, with no-map properties. This device tree update is only done when the video device is active and the video buffer is used. This patch uses '#if CONFIG_IS_ENABLED(DM_VIDEO)' because gd->video_bottom and gd->video_top are only defined when CONFIG_DM_VIDEO is activated. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- common/fdt_simplefb.c | 27 +++++++++++++++++++++++++++ include/fdt_simplefb.h | 1 + 2 files changed, 28 insertions(+) diff --git a/common/fdt_simplefb.c b/common/fdt_simplefb.c index 32173030ab..c52846f4bc 100644 --- a/common/fdt_simplefb.c +++ b/common/fdt_simplefb.c @@ -89,3 +89,30 @@ int fdt_simplefb_enable_existing_node(void *blob) return fdt_simplefb_configure_node(blob, off); } + +#if CONFIG_IS_ENABLED(DM_VIDEO) +int fdt_simplefb_enable_and_mem_rsv(void *blob) +{ + struct fdt_memory mem; + int ret; + + /* nothing to do when video is not active */ + if (!video_is_active()) + return 0; + + ret = fdt_simplefb_enable_existing_node(blob); + if (ret) + return ret; + + /* nothing to do when the frame buffer is not defined */ + if (gd->video_bottom == gd->video_top) + return 0; + + /* reserved with no-map tag the video buffer */ + mem.start = gd->video_bottom; + mem.end = gd->video_top - 1; + + return fdtdec_add_reserved_memory(blob, "framebuffer", &mem, NULL, 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); +} +#endif diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h index 7e54723591..41cd740ac0 100644 --- a/include/fdt_simplefb.h +++ b/include/fdt_simplefb.h @@ -10,4 +10,5 @@ #define _FDT_SIMPLEFB_H_ int fdt_simplefb_add_node(void *blob); int fdt_simplefb_enable_existing_node(void *blob); +int fdt_simplefb_enable_and_mem_rsv(void *blob); #endif From 6cdeb323b89adb3649659d32a52eeaecb1e96086 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:22 +0100 Subject: [PATCH 26/31] video: stm32: stm32_ltdc: align framebuffer on 2MB Align the framebuffer size on MMU_SECTION_SIZE in kernel, = max 2MB for LPAE for armV7, to avoid issue with the simple frame buffer activation, when U-Boot add a reserved memory in the kernel device tree to preserve the splash screen until Linux driver initialization. See Linux documentation for details: Documentation/devicetree/bindings/display/simple-framebuffer.yaml Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/video/stm32/stm32_ltdc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 65c882d9f1..87e5fd54d9 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -459,7 +459,10 @@ static int stm32_ltdc_bind(struct udevice *dev) uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES * CONFIG_VIDEO_STM32_MAX_YRES * (CONFIG_VIDEO_STM32_MAX_BPP >> 3); - dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size); + /* align framebuffer on kernel MMU_SECTION_SIZE = max 2MB for LPAE */ + uc_plat->align = SZ_2M; + dev_dbg(dev, "frame buffer max size %d bytes align %x\n", + uc_plat->size, uc_plat->align); return 0; } From 8ad37e6f16d5d58128f1ca8eb2038ab89880d23e Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 16:32:23 +0100 Subject: [PATCH 27/31] board: stm32mp1: enable simple framebuffer node for splashscreen Enable an existing simple framebuffer node in the Linux kernel device tree and the add the associated reserved memory node to preserved the resources (clock, memory) used by the stm32 video driver to display the splashscreen = background in exlinux.conf file. These resources will be released by the Linux driver only when the associated driver is ready to avoid transition issues during the Linux kernel initialization between U-Boot splash screen and the final display. See Linux documentation for details: Documentation/devicetree/bindings/display/simple-framebuffer.yaml Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- board/st/stm32mp1/stm32mp1.c | 4 ++++ configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 4 files changed, 7 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 84592677e4..45f2ca81a6 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -914,6 +915,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) + fdt_simplefb_enable_and_mem_rsv(blob); + return 0; } #endif diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 2cc26d4066..c9ed2239ca 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 7b844a3e46..36ebeb4470 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 270cbaa733..63eeb50719 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_FIT=y CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_FDT_SIMPLEFB=y CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y From e84ee40b0b2d378aab66e45315ff835954b2078f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 19 Nov 2021 10:07:32 +0100 Subject: [PATCH 28/31] configs: stm32mp15: deactivate the CONFIG_STM32_IPCC The IPCC mailbox is only used for communication with M4 firmware but it is not used in the stm32 remoteproc driver; it was planed but the support of this mailbox in remoteproc for STM32MP15x is dropped. So the associated drivers and config CONFIG_STM32_IPCC can be deactivated to reduce the U-Boot size; the CONFIG_DM_MAILBOX can be also deactivated as the mailbox UCLASS is no more used. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig | 2 -- configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig | 2 -- configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig | 2 -- configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig | 2 -- configs/stm32mp15_basic_defconfig | 2 -- configs/stm32mp15_defconfig | 2 -- configs/stm32mp15_dhcom_basic_defconfig | 2 -- configs/stm32mp15_dhcor_basic_defconfig | 2 -- configs/stm32mp15_trusted_defconfig | 2 -- 9 files changed, 18 deletions(-) diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index adb8f10b17..11a2885a5c 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -51,8 +51,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index dca35db014..7973e0f46f 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -51,8 +51,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index aa6a28e6a7..5eadd63100 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -51,8 +51,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 9abd1a100c..1dde46a0ce 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -51,8 +51,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index c9ed2239ca..341aaf3702 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -103,8 +103,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 36ebeb4470..9c638abeee 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -86,8 +86,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 84375589c5..8fbcef2699 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -96,8 +96,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 2356de76ba..078d0dee74 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -92,8 +92,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 63eeb50719..7401c4f9be 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -87,8 +87,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_STM32_IPCC=y CONFIG_STM32_FMC2_EBI=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y From d72e7bbe7c2841f161848d57b723495a731d0121 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 24 Nov 2021 10:52:18 +0100 Subject: [PATCH 29/31] ram: stm32mp1: compute DDR size from DDRCTL registers Compute the DDR size from DDR controller register (mstr and addrmap) in U-Boot proper as the DDR information are useful only for SPL but not for U-Boot proper, for example with TFABOOT. This patch simplify U-Boot DT when several DDR size are supported and support of next SOC in STM32MP family. Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay --- drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 + drivers/ram/stm32mp1/stm32mp1_ram.c | 193 ++++++++++++++++++++++- 2 files changed, 191 insertions(+), 3 deletions(-) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index be89d81018..f1a26e31f6 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -239,6 +239,7 @@ struct stm32mp1_ddrphy { #define DDRCTRL_MSTR_LPDDR2 BIT(2) #define DDRCTRL_MSTR_LPDDR3 BIT(3) #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT 12 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12) #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12) #define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12) diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 3b65269b98..69f2a99e7a 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -16,6 +16,12 @@ #include #include #include "stm32mp1_ddr.h" +#include "stm32mp1_ddr_regs.h" + +/* DDR subsystem configuration */ +struct stm32mp1_ddr_cfg { + u8 nb_bytes; /* MEMC_DRAM_DATA_WIDTH */ +}; static const char *const clkname[] = { "ddrc1", @@ -165,6 +171,183 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) return 0; } +static u8 get_data_bus_width(struct stm32mp1_ddrctl *ctl) +{ + u32 reg = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK; + u8 data_bus_width = reg >> DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT; + + return data_bus_width; +} + +static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl) +{ + /* Count bank address bits */ + u8 bits = 0; + u32 reg, val; + + reg = readl(&ctl->addrmap1); + /* addrmap1.addrmap_bank_b1 */ + val = (reg & GENMASK(5, 0)) >> 0; + if (val <= 31) + bits++; + /* addrmap1.addrmap_bank_b2 */ + val = (reg & GENMASK(13, 8)) >> 8; + if (val <= 31) + bits++; + /* addrmap1.addrmap_bank_b3 */ + val = (reg & GENMASK(21, 16)) >> 16; + if (val <= 31) + bits++; + + return bits; +} + +static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width) +{ + u8 bits; + u32 reg, val; + + /* Count column address bits, start at 2 for b0 and b1 (fixed) */ + bits = 2; + + reg = readl(&ctl->addrmap2); + /* addrmap2.addrmap_col_b2 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b3 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b4 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap2.addrmap_col_b5 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + reg = readl(&ctl->addrmap3); + /* addrmap3.addrmap_col_b6 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b7 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b8 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap3.addrmap_col_b9 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + reg = readl(&ctl->addrmap4); + /* addrmap4.addrmap_col_b10 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap4.addrmap_col_b11 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + + /* + * column bits shift up: + * 1 when half the data bus is used (data_bus_width = 1) + * 2 when a quarter the data bus is used (data_bus_width = 2) + * nothing to do for full data bus (data_bus_width = 0) + */ + bits += data_bus_width; + + return bits; +} + +static u8 get_nb_row(struct stm32mp1_ddrctl *ctl) +{ + /* Count row address bits */ + u8 bits = 0; + u32 reg, val; + + reg = readl(&ctl->addrmap5); + /* addrmap5.addrmap_row_b0 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 11) + bits++; + /* addrmap5.addrmap_row_b1 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 11) + bits++; + /* addrmap5.addrmap_row_b2_10 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 11) + bits += 9; + else + printf("warning: addrmap5.addrmap_row_b2_10 not supported\n"); + /* addrmap5.addrmap_row_b11 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 11) + bits++; + + reg = readl(&ctl->addrmap6); + /* addrmap6.addrmap_row_b12 */ + val = (reg & GENMASK(3, 0)) >> 0; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b13 */ + val = (reg & GENMASK(11, 8)) >> 8; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b14 */ + val = (reg & GENMASK(19, 16)) >> 16; + if (val <= 7) + bits++; + /* addrmap6.addrmap_row_b15 */ + val = (reg & GENMASK(27, 24)) >> 24; + if (val <= 7) + bits++; + + return bits; +} + +/* + * stm32mp1_ddr_size + * + * Get the current DRAM size from the DDR CTL registers + * + * @return: DRAM size + */ +u32 stm32mp1_ddr_size(struct udevice *dev) +{ + u8 nb_bit; + u32 ddr_size; + u8 data_bus_width; + struct ddr_info *priv = dev_get_priv(dev); + struct stm32mp1_ddrctl *ctl = priv->ctl; + struct stm32mp1_ddr_cfg *cfg = (struct stm32mp1_ddr_cfg *)dev_get_driver_data(dev); + const u8 nb_bytes = cfg->nb_bytes; + + data_bus_width = get_data_bus_width(ctl); + nb_bit = get_nb_bank(ctl) + get_nb_col(ctl, data_bus_width) + + get_nb_row(ctl); + if (nb_bit > 32) { + nb_bit = 32; + debug("invalid DDR configuration: %d bits\n", nb_bit); + } + + ddr_size = (nb_bytes >> data_bus_width) << nb_bit; + if (ddr_size > STM32_DDR_SIZE) { + ddr_size = STM32_DDR_SIZE; + debug("invalid DDR configuration: size = %x\n", ddr_size); + } + + return ddr_size; +} + static int stm32mp1_ddr_probe(struct udevice *dev) { struct ddr_info *priv = dev_get_priv(dev); @@ -191,8 +374,8 @@ static int stm32mp1_ddr_probe(struct udevice *dev) return log_ret(ret); } - ofnode node = stm32mp1_ddr_get_ofnode(dev); - priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0); + priv->info.size = stm32mp1_ddr_size(dev); + return 0; } @@ -209,8 +392,12 @@ static struct ram_ops stm32mp1_ddr_ops = { .get_info = stm32mp1_ddr_get_info, }; +static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = { + .nb_bytes = 4, +}; + static const struct udevice_id stm32mp1_ddr_ids[] = { - { .compatible = "st,stm32mp1-ddr" }, + { .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg}, { } }; From b2ac9645e6989f06382909f7230c1b1fd5b4df2c Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 24 Nov 2021 10:52:19 +0100 Subject: [PATCH 30/31] ram: stm32mp1: remove __maybe_unused on stm32mp1_ddr_setup Since the commit f42045b2e750 ("stm32mp15: replace CONFIG_TFABOOT when it is possible") the function stm32mp1_ddr_setup is always called so the __maybe_unused can be removed. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/ram/stm32mp1/stm32mp1_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 69f2a99e7a..49b1262461 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -88,7 +88,7 @@ static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev) return dev_ofnode(dev); } -static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) +static int stm32mp1_ddr_setup(struct udevice *dev) { struct ddr_info *priv = dev_get_priv(dev); int ret; From c7c06fa776b3a553df922259908fad12cfa0e1e8 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 25 Nov 2021 11:54:53 +0100 Subject: [PATCH 31/31] board: stm32mp1: add support of nor1 device in dfu command Add support of mtd backend for nor1 when this device is present on the board, on STM32MP157C-EV1 for example, as the support of several MTD spi-nor instance are now supported with commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- board/st/common/stm32mp_dfu.c | 4 ++++ doc/board/st/stm32mp1.rst | 18 ++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c index 00d1fb8f59..a3f0da5b5b 100644 --- a/board/st/common/stm32mp_dfu.c +++ b/board/st/common/stm32mp_dfu.c @@ -132,6 +132,10 @@ void set_dfu_alt_info(char *interface, char *devstr) mtd = get_mtd_device_nm("nor0"); if (!IS_ERR_OR_NULL(mtd)) board_get_alt_info_mtd(mtd, buf); + + mtd = get_mtd_device_nm("nor1"); + if (!IS_ERR_OR_NULL(mtd)) + board_get_alt_info_mtd(mtd, buf); } mtd = get_mtd_device_nm("nand0"); diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 42bb94148d..0c5d3a90f0 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -645,16 +645,18 @@ On EV1 board, booting from SD card, without OP-TEE_:: dev: eMMC alt: 15 name: mmc1_rootfs layout: RAW_ADDR dev: eMMC alt: 16 name: mmc1_userfs layout: RAW_ADDR dev: MTD alt: 17 name: nor0 layout: RAW_ADDR - dev: MTD alt: 18 name: nand0 layout: RAW_ADDR - dev: VIRT alt: 19 name: OTP layout: RAW_ADDR - dev: VIRT alt: 20 name: PMIC layout: RAW_ADDR + dev: MTD alt: 18 name: nor1 layout: RAW_ADDR + dev: MTD alt: 19 name: nand0 layout: RAW_ADDR + dev: VIRT alt: 20 name: OTP layout: RAW_ADDR + dev: VIRT alt: 21 name: PMIC layout: RAW_ADDR All the supported device are exported for dfu-util tool:: $> dfu-util -l - Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="PMIC", serial="002700333338511934383330" - Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="OTP", serial="002700333338511934383330" - Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nand0", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="PMIC", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="OTP", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nand0", serial="002700333338511934383330" + Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor1", serial="002700333338511934383330" Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor0", serial="002700333338511934383330" Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="mmc1_userfs", serial="002700333338511934383330" Found DFU: [0483:df11] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="mmc1_rootfs", serial="002700333338511934383330" @@ -705,12 +707,12 @@ You can update the boot device: When the board is booting for nor0 or nand0, only the MTD partition on the boot devices are available, for example: -- NOR (nor0 = alt 20) & NAND (nand0 = alt 26) :: +- NOR (nor0 = alt 20, nor1 = alt 26) & NAND (nand0 = alt 27) : $> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1.stm32 $> dfu-util -d 0483:5720 -a 22 -D tf-a-stm32mp157c-ev1.stm32 $> dfu-util -d 0483:5720 -a 23 -D fip-stm32mp157c-ev1.bin - $> dfu-util -d 0483:5720 -a 27 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi + $> dfu-util -d 0483:5720 -a 28 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi - NAND (nand0 = alt 21)::