85xx: Get ride of old TLB setup code

Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
2008-01-17 02:19:18 -06:00
parent 3b558e26a5
commit 7dc358bb0d
19 changed files with 0 additions and 39 deletions

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@@ -64,7 +64,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */

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@@ -56,7 +56,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

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@@ -44,7 +44,6 @@
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* Using Localbus SDRAM to emulate flash before we can program the flash,
* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.

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@@ -48,7 +48,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

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@@ -43,7 +43,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

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@@ -56,7 +56,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

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@@ -48,7 +48,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

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@@ -53,7 +53,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

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@@ -50,7 +50,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

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@@ -52,7 +52,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

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@@ -52,7 +52,6 @@
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

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@@ -57,7 +57,6 @@
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE

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@@ -51,7 +51,6 @@
#endif
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

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@@ -57,7 +57,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */

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@@ -51,7 +51,6 @@
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE

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@@ -52,7 +52,6 @@
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* sysclk for MPC85xx
*/

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@@ -52,7 +52,6 @@
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
/* sysclk for MPC85xx
*/