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sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD

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DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.

Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Icenowy Zheng
2018-10-28 14:26:12 -07:00
committed by Jagan Teki
parent e6b16e7852
commit 7d121a8ea4
2 changed files with 18 additions and 8 deletions
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4
arch/arm/mach-sunxi/clock_sun6i.c
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@@ -149,7 +149,11 @@ void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#ifdef CONFIG_SUNXI_DE2
const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
#else
const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
#endif
if (clk == 0) {
clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);