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ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2

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Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Kishon Vijay Abraham I
2015-08-10 16:52:55 +05:30
committed by Tom Rini
parent 8af1be7678
commit 7beaf8b690
4 changed files with 23 additions and 0 deletions
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3
arch/arm/include/asm/arch-omap5/clock.h
View File

@@ -172,6 +172,9 @@
/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8)
/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0)
#define OPTFCLKEN_REFCLK960M (1 << 8)

2
arch/arm/include/asm/omap_common.h
View File

@@ -145,6 +145,7 @@ struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
@@ -231,6 +232,7 @@ struct prcm_regs {
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
u32 cm_l3init_usb_otg_ss1_clkctrl;
u32 cm_l3init_usb_otg_ss2_clkctrl;
u32 prm_irqstatus_mpu_2;