From 7d4541cdfbf9697c39e720690f13b9c02d3c7555 Mon Sep 17 00:00:00 2001 From: Haolin Li Date: Sun, 18 Jul 2021 10:13:39 +0800 Subject: [PATCH 01/60] mtd: nand: Fix typo in MXC Kconfig symbol description Trivial typo fix. Signed-off-by: Haolin Li Reviewed-by: Michal Simek --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 790ee34403..d4da639dd1 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -369,7 +369,7 @@ config NAND_MXC imply CMD_NAND help This enables the NAND driver for the NAND flash controller on the - i.MX27 / i.MX31 / i.MX5 rocessors. + i.MX27 / i.MX31 / i.MX5 processors. config NAND_MXS bool "MXS NAND support" From 884ba50a078f57df5bf18a1bbc8aa337f5ce404d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 6 Aug 2021 06:44:26 +0200 Subject: [PATCH 02/60] spl_fit. add hook to make fixes after fit header is loaded add hook function spl_load_simple_fit_fix_load() which is called after fit image header is loaded. Signed-off-by: Heiko Schocher Reviewed-by: Simon Glass --- common/spl/spl_fit.c | 11 +++++++++++ include/spl.h | 8 ++++++++ 2 files changed, 19 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index f41abca0cc..849e01ad8e 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -548,6 +548,15 @@ __weak bool spl_load_simple_fit_skip_processing(void) return false; } +/* + * Weak default function to allow fixes after fit header + * is loaded. + */ +__weak void *spl_load_simple_fit_fix_load(const void *fit) +{ + return (void *)fit; +} + static void warn_deprecated(const char *msg) { printf("DEPRECATED: %s\n", msg); @@ -685,6 +694,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (spl_load_simple_fit_skip_processing()) return 0; + ctx.fit = spl_load_simple_fit_fix_load(ctx.fit); + ret = spl_simple_fit_parse(&ctx); if (ret < 0) return ret; diff --git a/include/spl.h b/include/spl.h index afbf39bef4..7ddb2abe0f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -304,6 +304,14 @@ ulong spl_get_image_text_base(void); */ bool spl_load_simple_fit_skip_processing(void); +/** + * spl_load_simple_fit_fix_load() - Hook to make fixes + * after fit image header is loaded + * + * Returns pointer to fit + */ +void *spl_load_simple_fit_fix_load(const void *fit); + /** * spl_load_simple_fit() - Loads a fit image from a device. * @spl_image: Image description to set up From 9de35448580020b526b6e5a8b538a59a64c72f0e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 6 Aug 2021 06:44:27 +0200 Subject: [PATCH 03/60] imx: spl: implement spl_load_simple_fit_fix_load read the address where the IVT header must sit from IVT image header, loaded from SPL into an malloced buffer and copy the IVT header to this address May make this dependend on SoC ? Signed-off-by: Heiko Schocher --- arch/arm/mach-imx/spl.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index c2845241d9..01f6f0a1de 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -345,3 +345,36 @@ int dram_init_banksize(void) return 0; } #endif + +/* + * read the address where the IVT header must sit + * from IVT image header, loaded from SPL into + * an malloced buffer and copy the IVT header + * to this address + */ +void *spl_load_simple_fit_fix_load(const void *fit) +{ + struct ivt *ivt; + unsigned long new; + unsigned long offset; + unsigned long size; + u8 *tmp = (u8 *)fit; + + offset = ALIGN(fdt_totalsize(fit), 0x1000); + size = ALIGN(fdt_totalsize(fit), 4); + size = board_spl_fit_size_align(size); + tmp += offset; + ivt = (struct ivt *)tmp; + if (ivt->hdr.magic != IVT_HEADER_MAGIC) { + debug("no IVT header found\n"); + return (void *)fit; + } + debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size); + debug("%s: ivt self: %x\n", __func__, ivt->self); + new = ivt->self; + new -= offset; + debug("%s: new %lx\n", __func__, new); + memcpy((void *)new, fit, size); + + return (void *)new; +} From deb80ec023ecace8afa3dc13c1bef757a247b206 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 17 Aug 2021 08:17:18 +0200 Subject: [PATCH 04/60] imx: spl: fix imx8m secure boot cherry-picked from NXP code: 719d665a87c6: ("MLK-20467 imx8m: Fix issue for booting signed image through uuu") which fixes secure boot on imx8m based boards. Problem was that FIT header and so IVT header too, was loaded to memallocated address. So the ivt header address coded in IVT itself does not fit with the real position. Signed-off-by: Heiko Schocher Tested-by: Tim Harvey --- arch/arm/mach-imx/spl.c | 14 ++++++++++++++ common/spl/spl_fit.c | 7 ++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 01f6f0a1de..427b7f7859 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -334,6 +334,20 @@ void board_spl_fit_post_load(const void *fit) } #endif +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + int align_len = ARCH_DMA_MINALIGN - 1; + + /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address + * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust + * the bl_len to align with SD/MMC. + */ + if (bl_len < 512) + bl_len = 512; + + return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len - + align_len) & ~align_len); +} #endif #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 849e01ad8e..5fe0273d66 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -538,6 +538,11 @@ static void *spl_get_fit_load_buffer(size_t size) return buf; } +__weak void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return spl_get_fit_load_buffer(sectors * bl_len); +} + /* * Weak default function to allow customizing SPL fit loading for load-only * use cases by allowing to skip the parsing/processing of the FIT contents @@ -640,7 +645,7 @@ static int spl_simple_fit_read(struct spl_fit_info *ctx, * For FIT with external data, data is not loaded in this step. */ sectors = get_aligned_image_size(info, size, 0); - buf = spl_get_fit_load_buffer(sectors * info->bl_len); + buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len); count = info->read(info, sector, sectors, buf); ctx->fit = buf; From 9b7c3495500c31b4acf416c9f866947feab3e230 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 17 Aug 2021 17:09:20 +0800 Subject: [PATCH 05/60] mmc: fsl_esdhc_imx: Fix clock disable issue The SD clock disable is wrapped by MMC_SUPPORTS_TUNING. So it only works when UHS is enabled. However, in SD initialization the power cycle does not depends on UHS. But the power cycle needs disable the SD clock before power down. So this causes a problem when UHS is not enabled. Some cards can't become ready (ACMD14 timeout) due to the clock is enabled during power cycle. Signed-off-by: Ye Li Reviewed-by: Haibo Chen Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc_imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 5dfd484ef9..7c8d82afea 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -971,7 +971,6 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) if (priv->clock != clock) set_sysctl(priv, mmc, clock); -#ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); @@ -987,6 +986,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #endif } +#ifdef MMC_SUPPORTS_TUNING /* * For HS400/HS400ES mode, make sure set the strobe dll in the * target clock rate. So call esdhc_set_strobe_dll() after the From ae3f752919fa2eff4fa865e5fb09657452856a84 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 17 Aug 2021 17:10:35 +0800 Subject: [PATCH 06/60] arm: imx8m: Fix pad DSE issue for i.MX8MM/MN/MP According to 8MM/MN/MP reference manual, their pad registers only have 4 valid DSE values. And DSE2 and DSE4 are different with current definitions in iomux-v3.h. Fix the issue to align with manual. Signed-off-by: Ye Li Acked-by: Peng Fan --- arch/arm/include/asm/mach-imx/iomux-v3.h | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 1de7093355..9330a32fe9 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) #ifdef CONFIG_IMX8M -#define PAD_CTL_DSE0 (0x0 << 0) -#define PAD_CTL_DSE1 (0x1 << 0) -#define PAD_CTL_DSE2 (0x2 << 0) -#define PAD_CTL_DSE3 (0x3 << 0) -#define PAD_CTL_DSE4 (0x4 << 0) -#define PAD_CTL_DSE5 (0x5 << 0) -#define PAD_CTL_DSE6 (0x6 << 0) -#define PAD_CTL_DSE7 (0x7 << 0) - #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) @@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_DSE1 (0x0 << 1) +#define PAD_CTL_DSE2 (0x2 << 1) +#define PAD_CTL_DSE4 (0x1 << 1) +#define PAD_CTL_DSE6 (0x3 << 1) #define PAD_CTL_PE (0x1 << 8) #else +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) #define PAD_CTL_LVTTL (0x1 << 8) #endif From f68c897e2deacbf7870f3ba618d8d46efb44c149 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 17 Aug 2021 17:24:47 +0800 Subject: [PATCH 07/60] mtd: nand: mxs_nand_spl: Add nand_spl_adjust_offset Since the mxs_nand_spl has implemented adjust read offset in nand_spl_load_image, so we don't need to check the bad block in nand_spl_adjust_offset. Directly return the offset to continue read by nand_spl_load_image. Signed-off-by: Ye Li --- drivers/mtd/nand/raw/mxs_nand_spl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 6b70d68fe7..9e0b8afb52 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -296,3 +296,9 @@ int nand_default_bbt(struct mtd_info *mtd) void nand_deselect(void) { } + +u32 nand_spl_adjust_offset(u32 sector, u32 offs) +{ + /* Handle the offset adjust in nand_spl_load_image,*/ + return offs; +} From aaac39218dd0b4b3f288ea8edae1c1dbf3406ae2 Mon Sep 17 00:00:00 2001 From: Andrej Rosano Date: Tue, 17 Aug 2021 11:34:02 +0200 Subject: [PATCH 08/60] imx53: usbarmory: Add card detect configuration After the enforcement of DM_MMC the microSD card is not detected. Fix by correctly configuring the card detect in the devicetree. Signed-off-by: Andrej Rosano --- arch/arm/dts/imx53-usbarmory.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imx53-usbarmory.dts b/arch/arm/dts/imx53-usbarmory.dts index f34993a490..433b62e736 100644 --- a/arch/arm/dts/imx53-usbarmory.dts +++ b/arch/arm/dts/imx53-usbarmory.dts @@ -91,6 +91,7 @@ &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; + broken-cd; status = "okay"; }; From 9e4b38a12ae560802e7c06cc4402fc07587c0037 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Aug 2021 15:24:27 -0700 Subject: [PATCH 09/60] board: gateworks: venice: display hwmon details by default Display hwmon values by default when using the 'gsc' command. Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam --- board/gateworks/venice/gsc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c index 7d6acd7b4a..065d1fb8cc 100644 --- a/board/gateworks/venice/gsc.c +++ b/board/gateworks/venice/gsc.c @@ -527,6 +527,9 @@ static int gsc_info(int verbose) printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24); } + /* Display hwmon */ + gsc_hwmon(); + return 0; } From 45e82c379ce873c9ff2cde97b47f576971c19f96 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Aug 2021 15:24:28 -0700 Subject: [PATCH 10/60] board: gateworks: venice: do not overwrite serial# Do not overwrite existing serial# env to avoid: ## Error: Can't overwrite "serial#" ## Error inserting "serial#" variable, errno=1 Signed-off-by: Tim Harvey --- board/gateworks/venice/imx8mm_venice.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c index 2a97d55d32..46f4bff925 100644 --- a/board/gateworks/venice/imx8mm_venice.c +++ b/board/gateworks/venice/imx8mm_venice.c @@ -114,7 +114,8 @@ int board_late_init(void) led_default_state(); /* Set board serial/model */ - env_set_ulong("serial#", gsc_get_serial()); + if (!env_get("serial#")) + env_set_ulong("serial#", gsc_get_serial()); env_set("model", gsc_get_model()); /* Set fdt_file vars */ From cd7f37666a79d7cc7eaad9815e70568d64ef3115 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Aug 2021 15:24:29 -0700 Subject: [PATCH 11/60] arm: dts: imx8mm-venice-gw700x: fix mp5416 pmic config Fix various MP5416 PMIC configurations: - Update regulator names per dt-bindings - ensure values fit among valid register values - add required regulator-max-microamp property - add regulator-always-on prop Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw700x.dtsi | 56 +++++++++++++++++--------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index cc850e7dce..f182a816b5 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -282,65 +282,83 @@ reg = <0x69>; regulators { + /* vdd_0p95: DRAM/GPU/VPU */ buck1 { - regulator-name = "vdd_0p95"; - regulator-min-microvolt = <805000>; + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-max-microamp = <2500000>; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_soc */ buck2 { - regulator-name = "vdd_soc"; - regulator-min-microvolt = <805000>; + regulator-name = "buck2"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; - regulator-max-microamp = <1000000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_arm */ buck3_reg: buck3 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <805000>; + regulator-name = "buck3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1000000>; - regulator-max-microamp = <2200000>; - regulator-boot-on; + regulator-min-microamp = <3800000>; + regulator-max-microamp = <6800000>; + regulator-always-on; }; + /* vdd_1p8 */ buck4 { - regulator-name = "vdd_1p8"; + regulator-name = "buck4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-max-microamp = <500000>; + regulator-min-microamp = <2200000>; + regulator-max-microamp = <5200000>; regulator-boot-on; + regulator-always-on; }; + /* nvcc_snvs_1p8 */ ldo1 { - regulator-name = "nvcc_snvs_1p8"; + regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-max-microamp = <300000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_snvs_0p8 */ ldo2 { - regulator-name = "vdd_snvs_0p8"; + regulator-name = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_0p9 */ ldo3 { - regulator-name = "vdd_0p95"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; + regulator-name = "ldo3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; regulator-boot-on; + regulator-always-on; }; + /* vdd_1p8 */ ldo4 { - regulator-name = "vdd_1p8"; + regulator-name = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; + regulator-always-on; }; }; }; From f8a792e51d17c32b62e957d10be93d6ab9008f53 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Aug 2021 15:24:30 -0700 Subject: [PATCH 12/60] board: gateworks: venice: update thermal temp thresholds per cpu grade Update the passive/critical thermal zone dt config per CPU temperature grade. Signed-off-by: Tim Harvey --- board/gateworks/venice/imx8mm_venice.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c index 46f4bff925..4e05802b6f 100644 --- a/board/gateworks/venice/imx8mm_venice.c +++ b/board/gateworks/venice/imx8mm_venice.c @@ -156,8 +156,26 @@ int board_mmc_get_env_dev(int devno) int ft_board_setup(void *blob, struct bd_info *bd) { + int off; + /* set board model dt prop */ fdt_setprop_string(blob, 0, "board", gsc_get_model()); + /* update temp thresholds */ + off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips"); + if (off >= 0) { + int minc, maxc, prop; + + get_cpu_temp_grade(&minc, &maxc); + fdt_for_each_subnode(prop, blob, off) { + const char *type = fdt_getprop(blob, prop, "type", NULL); + + if (type && (!strcmp("critical", type))) + fdt_setprop_u32(blob, prop, "temperature", maxc * 1000); + else if (type && (!strcmp("passive", type))) + fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000); + } + } + return 0; } From 0cf5622998542f63943f03d041009a9997cea04f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 18 Aug 2021 15:24:31 -0700 Subject: [PATCH 13/60] arm: dts: imx8mm-venice*: remove thermal zone overrides Remove the unnecessary thermal zone overrides. Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7901.dts | 12 ------------ arch/arm/dts/imx8mm-venice-gw7902.dts | 12 ------------ 2 files changed, 24 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts index 124e1e4e70..d5cdbb7f99 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901.dts +++ b/arch/arm/dts/imx8mm-venice-gw7901.dts @@ -1041,15 +1041,3 @@ >; }; }; - -&cpu_alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; -}; - -&cpu_crit0 { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; -}; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 2948821644..07e436be95 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -913,15 +913,3 @@ >; }; }; - -&cpu_alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; -}; - -&cpu_crit0 { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; -}; From 5a6af8c19ab8c9a7dd44db9406b68fcb7fe5ee18 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Mon, 23 Aug 2021 10:43:06 +0800 Subject: [PATCH 14/60] imx8m: Restrict usable memory based on rom_pointer[0] When TEE is loaded, we need to restrict the memory usage based on rom_pointer[0] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Fabio Estevam Cc: Frieder Schrempf Cc: uboot-imx Reviewed-by: Frieder Schrempf --- arch/arm/mach-imx/imx8m/soc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index f2ddc834d4..863508776d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -298,16 +298,26 @@ phys_size_t get_effective_memsize(void) ulong board_get_usable_ram_top(ulong total_size) { + ulong top_addr = PHYS_SDRAM + gd->ram_size; + /* * Some IPs have their accessible address space restricted by * the interconnect. Let's make sure U-Boot only ever uses the * space below the 4G address boundary (which is 3GiB big), * even when the effective available memory is bigger. */ - if (PHYS_SDRAM + gd->ram_size > 0x80000000) - return 0x80000000; + if (top_addr > 0x80000000) + top_addr = 0x80000000; - return PHYS_SDRAM + gd->ram_size; + /* + * rom_pointer[0] stores the TEE memory start address. + * rom_pointer[1] stores the size TEE uses. + * We need to reserve the memory region for TEE. + */ + if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0]) + top_addr = rom_pointer[0]; + + return top_addr; } static u32 get_cpu_variant_type(u32 type) From 88f4f50989063a55dede30d60cb76949c88a7e17 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Mon, 23 Aug 2021 14:55:12 +0300 Subject: [PATCH 15/60] mx7ulp: Allow to enable CONFIG_IMX_HAB Secure boot support on mx7ulp was added in the commit 27117b2024b6 ("mx7ulp: Add HAB boot support"). Allow selecting CONFIG_IMX_HAB for ARCH_IMX7ULP. Fixes: 27117b2024b6 ("mx7ulp: Add HAB boot support") Signed-off-by: Ricardo Salveti Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index dd4f027f36..9aa1d84336 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -48,7 +48,7 @@ config USE_IMXIMG_PLUGIN config IMX_HAB bool "Support i.MX HAB features" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP select FSL_CAAM if HAS_CAAM imply CMD_DEKBLOB if HAS_CAAM help From 53a24dee86fb72ae41e7579607bafe13442616f2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Aug 2021 21:11:09 -0300 Subject: [PATCH 16/60] imx8mm-cl-iot-gate: Split the defconfigs Currently imx8mm-cl-iot-gate_defconfig fails to produce a working boot binary due to the lack of fip.bin: " BINMAN all Image 'main-section' is missing external blobs and is non-functional: blob-ext Some images are invalid" To make the build process more consistent with the other i.MX8M targets, split the defconfig in two: - imx8mm-cl-iot-gate_defconfig: standard defconfig that only requires ATF / DDR firmware. - imx8mm-cl-iot-gate-optee_defconfig: "more advanced" defconfig that requires ATF / Optee / mbedtls / DDR firmware. Signed-off-by: Fabio Estevam Tested-by: Ying-Chun Liu (PaulLiu) --- arch/arm/dts/Makefile | 2 + .../dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi | 255 ++++++++++++++++++ arch/arm/dts/imx8mm-cl-iot-gate-optee.dts | 6 + arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 14 +- arch/arm/mach-imx/imx8m/Kconfig | 7 + board/compulab/imx8mm-cl-iot-gate/Kconfig | 2 +- board/compulab/imx8mm-cl-iot-gate/MAINTAINERS | 1 + configs/imx8mm-cl-iot-gate-optee_defconfig | 147 ++++++++++ 8 files changed, 420 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-cl-iot-gate-optee.dts create mode 100644 configs/imx8mm-cl-iot-gate-optee_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9438bf735a..45740a48e0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1137,6 +1137,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb +dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb + dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb targets += $(dtb-y) diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi new file mode 100644 index 0000000000..12065935e4 --- /dev/null +++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + binman: binman { + multiple-images; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_uart3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart3 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl2.bin"; + }; + }; + + fip { + description = "Trusted Firmware FIP"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x40310000>; + + fip_blob: blob-ext{ + filename = "fip.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf", "fip"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts b/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts new file mode 100644 index 0000000000..4d0ef46997 --- /dev/null +++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mm-cl-iot-gate.dts" diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi index 3226a244a9..00927c1574 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi @@ -217,18 +217,6 @@ }; }; - fip { - description = "Trusted Firmware FIP"; - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <0x40310000>; - - fip_blob: blob-ext{ - filename = "fip.bin"; - }; - }; - fdt { description = "NAME"; type = "flat_dt"; @@ -246,7 +234,7 @@ conf { description = "NAME"; firmware = "uboot"; - loadables = "atf", "fip"; + loadables = "atf"; fdt = "fdt"; }; }; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index ccaf106be5..dfda4cb70e 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -138,6 +138,13 @@ config TARGET_IMX8MM_CL_IOT_GATE select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + +config TARGET_IMX8MM_CL_IOT_GATE_OPTEE + bool "CompuLab iot-gate-imx8 with optee support" + select BINMAN + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 endchoice source "board/beacon/imx8mm/Kconfig" diff --git a/board/compulab/imx8mm-cl-iot-gate/Kconfig b/board/compulab/imx8mm-cl-iot-gate/Kconfig index 30760cbf45..e6ceb9138f 100644 --- a/board/compulab/imx8mm-cl-iot-gate/Kconfig +++ b/board/compulab/imx8mm-cl-iot-gate/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MM_CL_IOT_GATE +if TARGET_IMX8MM_CL_IOT_GATE || TARGET_IMX8MM_CL_IOT_GATE_OPTEE config SYS_BOARD default "imx8mm-cl-iot-gate" diff --git a/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS b/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS index 9c6b17095c..9db1fb6950 100644 --- a/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS +++ b/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/compulab/imx8mm-cl-iot-gate/ F: include/configs/imx8mm-cl-iot-gate.h F: configs/imx8mm-cl-iot-gate_defconfig +F: configs/imx8mm-cl-iot-gate-optee_defconfig diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig new file mode 100644 index 0000000000..d918779960 --- /dev/null +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -0,0 +1,147 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_BOOTEFI_SELFTEST=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_BIND=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x44000000 +CONFIG_FASTBOOT_BUF_SIZE=0x5000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_KEYBOARD=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_ABX80X=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_TPM2_TIS_SPI=y +CONFIG_TPM2_FTPM_TEE=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPM=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_SECURE_BOOT=y From d9a6f0eed66a39206b13513ec914f14084c3bb73 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 24 Aug 2021 09:55:14 +0200 Subject: [PATCH 17/60] tree: imx: remove old fit generator script Since derivatives are moving to binman from usage of the FIT generator script, and considering the warning introduced in f4a43d2925 ("Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR"), usage of FIT generator is discouraged. Current FIT generator also generates broken output, since commit 3f04db891a ("image: Check for unit addresses in FITs") prohibits using '@' for unit addresses but the generator script still emits the old sematics. Remove the generator script and corresponding call in Makefile, all derivatives should be migrated to binman in order to provide binary images. Signed-off-by: Andrey Zhizhikin Reviewed-by: Simon Glass Reviewed-by: Fabio Estevam --- Makefile | 3 - arch/arm/mach-imx/mkimage_fit_atf.sh | 143 --------------------------- 2 files changed, 146 deletions(-) delete mode 100755 arch/arm/mach-imx/mkimage_fit_atf.sh diff --git a/Makefile b/Makefile index f911f70344..ddee4524aa 100644 --- a/Makefile +++ b/Makefile @@ -1335,9 +1335,6 @@ $(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE)) else ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),) U_BOOT_ITS := u-boot.its -ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh") -U_BOOT_ITS_DEPS += u-boot-nodtb.bin -endif ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py") U_BOOT_ITS_DEPS += u-boot endif diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh deleted file mode 100755 index 2a17968794..0000000000 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ /dev/null @@ -1,143 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0+ -# -# script to generate FIT image source for i.MX8MQ boards with -# ARM Trusted Firmware and multiple device trees (given on the command line) -# -# usage: $0 [ [&2 - exit 0 -else - echo "$BL31 size: " >&2 - stat -c %s $BL31 >&2 -fi - -BL32="tee.bin" - -if [ ! -f $BL32 ]; then - BL32=/dev/null -else - echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2 - echo "$BL32 size: " >&2 - stat -c %s $BL32 >&2 -fi - -BL33="u-boot-nodtb.bin" - -if [ ! -f $BL33 ]; then - echo "ERROR: $BL33 file NOT found" >&2 - exit 0 -else - echo "u-boot-nodtb.bin size: " >&2 - stat -c %s u-boot-nodtb.bin >&2 -fi - -for dtname in $* -do - echo "$dtname size: " >&2 - stat -c %s $dtname >&2 -done - - -cat << __HEADER_EOF -/dts-v1/; - -/ { - description = "Configuration to load ATF before U-Boot"; - - images { - uboot@1 { - description = "U-Boot (64-bit)"; - os = "u-boot"; - data = /incbin/("$BL33"); - type = "standalone"; - arch = "arm64"; - compression = "none"; - load = <$BL33_LOAD_ADDR>; - }; -__HEADER_EOF - -cnt=1 -for dtname in $* -do - cat << __FDT_IMAGE_EOF - fdt@$cnt { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname"); - type = "flat_dt"; - compression = "none"; - }; -__FDT_IMAGE_EOF -cnt=$((cnt+1)) -done - -cat << __HEADER_EOF - atf@1 { - description = "ARM Trusted Firmware"; - os = "arm-trusted-firmware"; - data = /incbin/("$BL31"); - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <$ATF_LOAD_ADDR>; - entry = <$ATF_LOAD_ADDR>; - }; -__HEADER_EOF - -if [ -f $BL32 ]; then -cat << __HEADER_EOF - tee@1 { - description = "TEE firmware"; - data = /incbin/("$BL32"); - type = "firmware"; - arch = "arm64"; - compression = "none"; - load = <$TEE_LOAD_ADDR>; - entry = <$TEE_LOAD_ADDR>; - }; -__HEADER_EOF -fi - -cat << __CONF_HEADER_EOF - }; - configurations { - default = "config@1"; - -__CONF_HEADER_EOF - -cnt=1 -for dtname in $* -do -if [ -f $BL32 ]; then -cat << __CONF_SECTION_EOF - config@$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "uboot@1"; - loadables = "atf@1", "tee@1"; - fdt = "fdt@$cnt"; - }; -__CONF_SECTION_EOF -else -cat << __CONF_SECTION1_EOF - config@$cnt { - description = "$(basename $dtname .dtb)"; - firmware = "uboot@1"; - loadables = "atf@1"; - fdt = "fdt@$cnt"; - }; -__CONF_SECTION1_EOF -fi -cnt=$((cnt+1)) -done - -cat << __ITS_EOF - }; -}; -__ITS_EOF From 0f328fcc4ccfdf575794987799eee008ae4ca3bf Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Tue, 24 Aug 2021 17:44:19 +0800 Subject: [PATCH 18/60] arm: imx8m: imx8mm-cl-iot-gate: Add support for detect memory size When purchasing imx8mm-cl-iot-gate it is able to customize the memory size. It could be 1GB, 2GB and 4GB. We implement board_phys_sdram_size() to detect the memory size for usage. Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Fabio Estevam Cc: Frieder Schrempf Cc: uboot-imx Reviewed-by: Fabio Estevam --- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index eabcc842a4..cd15410978 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -14,8 +15,32 @@ #include #include +#include "ddr/ddr.h" + DECLARE_GLOBAL_DATA_PTR; +int board_phys_sdram_size(phys_size_t *size) +{ + struct lpddr4_tcm_desc *lpddr4_tcm_desc = + (struct lpddr4_tcm_desc *)TCM_DATA_CFG; + + switch (lpddr4_tcm_desc->size) { + case 4096: + case 2048: + case 1024: + *size = (1L << 20) * lpddr4_tcm_desc->size; + break; + default: + printf("%s: DRAM size %uM is not supported\n", + __func__, + lpddr4_tcm_desc->size); + hang(); + break; + }; + + return 0; +} + static int setup_fec(void) { if (IS_ENABLED(CONFIG_FEC_MXC)) { From 42cef89e86e3a41bee5a96057b1929f3975124ec Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Thu, 26 Aug 2021 10:54:09 +0200 Subject: [PATCH 19/60] arm: dts: imx8mp: Generate single bootable binary binman conversion made flashing flash.bin and u-boot.itb necessary. Update binman config to create a single flash.bin image again. This updates imx8mp_evk and phyCORE-i.MX8MP as they share the same binman config. Updated also imx8mp_evk documentation. Tested on phyCORE-i.MX8MP. Signed-off-by: Teresa Remmet Reviewed-by: Fabio Estevam Reviewed-by: Heiko Schocher --- arch/arm/dts/imx8mp-u-boot.dtsi | 19 ++++++++++++++++++- .../imx8mp_evk/imximage-8mp-lpddr4.cfg | 2 +- .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 2 +- doc/board/nxp/imx8mp_evk.rst | 1 - 4 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index d61346da30..afb3995482 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -79,7 +79,9 @@ }; }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000"; @@ -146,4 +148,19 @@ }; }; }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + }; + + uboot: blob-ext@2 { + filename = "u-boot.itb"; + offset = <0x58000>; + }; + }; }; diff --git a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg index b2920b4908..4c3ecf5a71 100644 --- a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg +++ b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg @@ -7,4 +7,4 @@ ROM_VERSION v2 BOOT_FROM sd -LOADER mkimage.flash.mkimage 0x920000 +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg index b2920b4908..4c3ecf5a71 100644 --- a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg +++ b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg @@ -7,4 +7,4 @@ ROM_VERSION v2 BOOT_FROM sd -LOADER mkimage.flash.mkimage 0x920000 +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/doc/board/nxp/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst index 609a29f3eb..b996ae055e 100644 --- a/doc/board/nxp/imx8mp_evk.rst +++ b/doc/board/nxp/imx8mp_evk.rst @@ -52,7 +52,6 @@ Burn the flash.bin to the MicroSD card at offset 32KB: .. code-block:: bash $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync - $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync Boot ---- From 7ce83854f2af53dfdd2ca2cdaab98933c6eaf56b Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Sat, 28 Aug 2021 10:41:22 +0300 Subject: [PATCH 20/60] Kconfig: Don't use RSA_FREESCALE_EXP on MX7ULP The CAAM on IMX7ULP doesn't support public key hardware acceleration (PKHA), as in other NXP parts. Disable RSA_FREESCALE_EXP for IMX7ULP too. Fixed: f4e9ff7135 ("Kconfig: Don't use RSA_FREESCALE_EXP on IMX") Signed-off-by: Ricardo Salveti Signed-off-by: Oleksandr Suvorov --- lib/rsa/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index cf802a6d40..469596abe7 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -1,6 +1,6 @@ config RSA bool "Use RSA Library" - select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5 + select RSA_FREESCALE_EXP if FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5 select RSA_SOFTWARE_EXP if !RSA_FREESCALE_EXP help RSA support. This enables the RSA algorithm used for FIT image @@ -57,7 +57,7 @@ config RSA_SOFTWARE_EXP config RSA_FREESCALE_EXP bool "Enable RSA Modular Exponentiation with FSL crypto accelerator" - depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX6 && !ARCH_MX5 + depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5 help Enables driver for RSA modular exponentiation using Freescale cryptographic accelerator - CAAM. From 80c9cb3cb529f06faa21e63682c30833d79c374c Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Sun, 29 Aug 2021 22:39:11 +0300 Subject: [PATCH 21/60] imx8mm_evk: Increase CONFIG_SYS_BOOTM_LEN to 64MB The BSP platform LmP supports the board NXP iMX8M Mini EVK. The kernel size in LmP exceeds 32Mb. Increase the maximum size of an uncompressed kernel to fix the following error: Uncompressing Kernel Image Error: inflate() returned -5 Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Signed-off-by: Oleksandr Suvorov --- include/configs/imx8mm_evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index a03a7a72ec..4c8f562737 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) +#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR From 13586e46686bfcbd6a43c12e6bfec589d8db16f8 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Sun, 29 Aug 2021 22:39:12 +0300 Subject: [PATCH 22/60] imx8mq_evk: Increase CONFIG_SYS_BOOTM_LEN to 64MB The BSP platform LmP supports the board NXP iMX8M Plus EVK. The kernel size in LmP exceeds 32Mb. Increase the maximum size of an uncompressed kernel to fix the following error: Uncompressing Kernel Image Error: inflate() returned -5 Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Signed-off-by: Oleksandr Suvorov --- include/configs/imx8mq_evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 9b9d6fd651..f2eb777476 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) +#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) From 32139c25e4402aa7be12b5b6ab928a62734f4781 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Sun, 29 Aug 2021 22:39:13 +0300 Subject: [PATCH 23/60] imx8qm_mek: Increase CONFIG_SYS_BOOTM_LEN to 64MB The BSP platform LmP supports the board NXP iMX8QM MEK. The kernel size in LmP exceeds 32Mb. Increase the maximum size of an uncompressed kernel to fix the following error: Uncompressing Kernel Image Error: inflate() returned -5 Image too large: increase CONFIG_SYS_BOOTM_LEN Must RESET board to recover Signed-off-by: Oleksandr Suvorov --- include/configs/imx8qm_mek.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 152fa6f1c2..803daa45c8 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -10,6 +10,8 @@ #include #include +#define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) + #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) From af2d3c91d8772e3d0eacef45a3bac8a4cbdb60ae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Sep 2021 00:43:18 +0200 Subject: [PATCH 24/60] ARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID Since c6df0e2ffdc ("net: phy: micrel: add support for DLL setup on ksz9131") the Micrel PHY driver correctly configures the delay register. The Verdin PHY is RGMII-ID, so reflect that in DT, otherwise the ethernet no longer works. Signed-off-by: Marek Vasut Cc: Marcel Ziswiler Cc: Max Krummenacher Cc: Oleksandr Suvorov --- arch/arm/dts/imx8mm-verdin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index fb0756d6e1..ac2a4b69d3 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -160,7 +160,7 @@ &fec1 { fsl,magic-packet; phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_ethphy>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec1>; From 5089d2fc8e4efc3ffad861fe2d127ff40b2f8064 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Tue, 21 Sep 2021 14:48:26 +0300 Subject: [PATCH 25/60] ARM: dts: imx6-apalis: enable watchdog Add u-boot.dtsi specific to imx6-apalis with a watchdog enabled. If OP-TEE is loaded by SPL, it may use a watchdog to handle fails of u-boot running. Enable the watchdog in SPL to use it by OP-TEE. Signed-off-by: Ricardo Salveti Signed-off-by: Oleksandr Suvorov Reviewed-by: Igor Opaniuk Reviewed-by: Peng Fan --- arch/arm/dts/imx6-apalis-u-boot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 arch/arm/dts/imx6-apalis-u-boot.dtsi diff --git a/arch/arm/dts/imx6-apalis-u-boot.dtsi b/arch/arm/dts/imx6-apalis-u-boot.dtsi new file mode 100644 index 0000000000..95e7e022b9 --- /dev/null +++ b/arch/arm/dts/imx6-apalis-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2020 Foundries.IO + */ + +#include "imx6qdl-u-boot.dtsi" + +&wdog1 { + status = "okay"; + u-boot,dm-spl; +}; From e1918ce299a10797df0f0f8e3df992fd6ed89aa6 Mon Sep 17 00:00:00 2001 From: Heiko Thiery Date: Thu, 23 Sep 2021 11:14:32 +0200 Subject: [PATCH 26/60] rtc: rv8803: add epson,rx8803 and epson,rx8900 compatible The RX8803 and RX8900 register layouts are compatible with the one of the RV8803. So add these to the compatibles. The same compatible strings are used and approved in linux kernel. Signed-off-by: Heiko Thiery Reviewed-by: Michael Walle --- drivers/rtc/rv8803.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c index acd50c6564..5bae39d6e0 100644 --- a/drivers/rtc/rv8803.c +++ b/drivers/rtc/rv8803.c @@ -157,6 +157,8 @@ static const struct rtc_ops rv8803_rtc_ops = { static const struct udevice_id rv8803_rtc_ids[] = { { .compatible = "microcrystal,rv8803", }, + { .compatible = "epson,rx8803" }, + { .compatible = "epson,rx8900" }, { } }; From 64fe0ffca0cd088cf0d74f76f6cd503a844ace49 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 23 Sep 2021 17:01:15 +0300 Subject: [PATCH 27/60] mx7ulp: Update wdog disable sequence Update the mx7ulp wdog disable sequence to avoid potential reset issue in unlock or refresh sequence. Both sequence need two words write to wdog CNT register in 16 bus clocks window, if miss the window, the write will cause violation in wdog and reset the chip. Current u-boot code is using writel() function which has a DMB barrier to order the memory access. The DMB between two words write may introduce some delay in certain circumstance, causing the wdog reset due to 16 bus clock window requirement. Also, WDOG1 might have been enabled already depending on FUSE hence we need to be as close as possible to its reconfiguration timing requirement of 128 bus clock limit. This patch replaces writel() function by __raw_writel() to avoid such issue, and improve to check if watchdog is already disabled or unlocked. Signed-off-by: Ye Li Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Co-developed-by: Ricardo Salveti Signed-off-by: Ricardo Salveti Signed-off-by: Oleksandr Suvorov --- arch/arm/mach-imx/mx7ulp/soc.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 320f24dd29..7f097d6850 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -93,14 +93,31 @@ int board_postclk_init(void) static void disable_wdog(u32 wdog_base) { - writel(UNLOCK_WORD0, (wdog_base + 0x04)); - writel(UNLOCK_WORD1, (wdog_base + 0x04)); - writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ - writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ - writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ + u32 val_cs = readl(wdog_base + 0x00); - writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ - writel(REFRESH_WORD1, (wdog_base + 0x04)); + if (!(val_cs & 0x80)) + return; + + dmb(); + __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ + __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); + dmb(); + + if (!(val_cs & 800)) { + dmb(); + __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); + __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x800)); + } + dmb(); + __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */ + __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */ + __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */ + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x400)); } void init_wdog(void) From cdb18048f9356732b097567bc60ac526aea6ec27 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Thu, 23 Sep 2021 23:14:37 +0300 Subject: [PATCH 28/60] ARM: dts: imx: use generic name bus Synchronize the u-boot and kernel imx device trees, using tuned script from commit c0157bdcafa1 ("ARM: dts: imx: use generic name bus") Per devicetree specification, generic names are recommended to be used, such as bus. i.MX AIPS is an AHB - IP bridge bus, so we could use bus as node name. Script: sed -i "s/\ Reviewed-by: Peng Fan --- arch/arm/dts/imx53-m53menlo-u-boot.dtsi | 2 +- arch/arm/dts/imx53.dtsi | 4 ++-- arch/arm/dts/imx6dl.dtsi | 4 ++-- arch/arm/dts/imx6q-display5-u-boot.dtsi | 2 +- arch/arm/dts/imx6q.dtsi | 2 +- arch/arm/dts/imx6qdl-u-boot.dtsi | 4 ++-- arch/arm/dts/imx6qdl.dtsi | 4 ++-- arch/arm/dts/imx6qp.dtsi | 2 +- arch/arm/dts/imx6sl.dtsi | 4 ++-- arch/arm/dts/imx6sll.dtsi | 4 ++-- arch/arm/dts/imx6sx.dtsi | 6 +++--- arch/arm/dts/imx6ul.dtsi | 4 ++-- arch/arm/dts/imx6ull.dtsi | 2 +- arch/arm/dts/imx7s.dtsi | 6 +++--- arch/arm/dts/vf.dtsi | 4 ++-- 15 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi index bc4b3483a6..869adb9dad 100644 --- a/arch/arm/dts/imx53-m53menlo-u-boot.dtsi +++ b/arch/arm/dts/imx53-m53menlo-u-boot.dtsi @@ -7,7 +7,7 @@ soc { u-boot,dm-pre-reloc; - aips@50000000 { + bus@50000000 { u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index ed341cfd9d..8536f59f59 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -222,7 +222,7 @@ clock-names = "core_clk", "mem_iface_clk"; }; - aips@50000000 { /* AIPS1 */ + bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -654,7 +654,7 @@ }; }; - aips@60000000 { /* AIPS2 */ + bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi index f0607eb41d..ae5aad6b9e 100644 --- a/arch/arm/dts/imx6dl.dtsi +++ b/arch/arm/dts/imx6dl.dtsi @@ -84,7 +84,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6dl-iomuxc"; }; @@ -100,7 +100,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/imx6q-display5-u-boot.dtsi b/arch/arm/dts/imx6q-display5-u-boot.dtsi index aa660b5aeb..ced4dacc73 100644 --- a/arch/arm/dts/imx6q-display5-u-boot.dtsi +++ b/arch/arm/dts/imx6q-display5-u-boot.dtsi @@ -23,7 +23,7 @@ soc { u-boot,dm-pre-reloc; - aips-bus@2100000 { + bus@2100000 { u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi index 71543a4a68..c37484dce3 100644 --- a/arch/arm/dts/imx6q.dtsi +++ b/arch/arm/dts/imx6q.dtsi @@ -162,7 +162,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2000000 { /* AIPS1 */ + bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { #address-cells = <1>; diff --git a/arch/arm/dts/imx6qdl-u-boot.dtsi b/arch/arm/dts/imx6qdl-u-boot.dtsi index 1279cc2338..f74af6c423 100644 --- a/arch/arm/dts/imx6qdl-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-u-boot.dtsi @@ -13,14 +13,14 @@ u-boot,dm-spl; u-boot,dm-pre-reloc; - aips-bus@2000000 { + bus@2000000 { u-boot,dm-spl; spba-bus@2000000 { u-boot,dm-spl; }; }; - aips-bus@2100000 { + bus@2100000 { u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index e4daf15088..1cdb498c72 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -283,7 +283,7 @@ status = "disabled"; }; - aips-bus@2000000 { /* AIPS1 */ + bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -913,7 +913,7 @@ }; }; - aips-bus@2100000 { /* AIPS2 */ + bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi index 5f51f8e5c1..93b89dc1f5 100644 --- a/arch/arm/dts/imx6qp.dtsi +++ b/arch/arm/dts/imx6qp.dtsi @@ -18,7 +18,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2100000 { + bus@2100000 { pre1: pre@21c8000 { compatible = "fsl,imx6qp-pre"; reg = <0x021c8000 0x1000>; diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi index cc9572ea28..37e341c6c3 100644 --- a/arch/arm/dts/imx6sl.dtsi +++ b/arch/arm/dts/imx6sl.dtsi @@ -130,7 +130,7 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; - aips1: aips-bus@02000000 { + aips1: bus@02000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -751,7 +751,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: bus@02100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi index 349c47a03a..ebc6d9d2c9 100644 --- a/arch/arm/dts/imx6sll.dtsi +++ b/arch/arm/dts/imx6sll.dtsi @@ -176,7 +176,7 @@ arm,data-latency = <4 2 3>; }; - aips1: aips-bus@02000000 { + aips1: bus@02000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -682,7 +682,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: bus@02100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi index 531a52c1e9..8d2d396ad1 100644 --- a/arch/arm/dts/imx6sx.dtsi +++ b/arch/arm/dts/imx6sx.dtsi @@ -235,7 +235,7 @@ status = "disabled"; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -830,7 +830,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -1188,7 +1188,7 @@ }; }; - aips3: aips-bus@2200000 { + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 5644b0f34d..ad9cb37db7 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -206,7 +206,7 @@ status = "disabled"; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -763,7 +763,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 22e4a307fa..f224e20bda 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -44,7 +44,7 @@ / { soc { - aips3: aips-bus@2200000 { + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index 967023fde1..483824fc06 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -340,7 +340,7 @@ <0x31006000 0x2000>; }; - aips1: aips-bus@30000000 { + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -647,7 +647,7 @@ }; }; - aips2: aips-bus@30400000 { + aips2: bus@30400000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -739,7 +739,7 @@ }; }; - aips3: aips-bus@30800000 { + aips3: bus@30800000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index 5f69d0fd6e..5ba13dc62b 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -34,7 +34,7 @@ compatible = "simple-bus"; ranges; - aips0: aips-bus@40000000 { + aips0: bus@40000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -158,7 +158,7 @@ }; }; - aips1: aips-bus@40080000 { + aips1: bus@40080000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 33e9a6956058663c6b92ed39b0464d1693cc963a Mon Sep 17 00:00:00 2001 From: Michael Scott Date: Sat, 25 Sep 2021 19:49:28 +0300 Subject: [PATCH 29/60] misc: ocotp: Allow disabling ocotp driver in SPL This allows removal of the OCOTP driver when SPL is enabled. Disabling OCOTP reduces SPL size efficiently. Signed-off-by: Michael Scott Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov Reviewed-by: Peng Fan --- drivers/misc/Kconfig | 9 +++++++++ drivers/misc/Makefile | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 099ff29348..3bae072005 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -233,6 +233,15 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config SPL_MXC_OCOTP + bool "Enable MXC OCOTP driver in SPL" + depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) + default y + help + If you say Y here, you will get support for the One Time + Programmable memory pages, that are stored on some + Freescale i.MX processors, in SPL. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index c16a77c34c..f9826d2462 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -50,7 +50,7 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/ obj-$(CONFIG_LED_STATUS) += status_led.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o -obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o From bc959905df4b31c2b9f77e5745e9d10d229a9bfa Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 28 Sep 2021 13:40:52 +0200 Subject: [PATCH 30/60] imx: mx7: spl: fix CONFIG_SPL_MAX_SIZE definition The CONFIG_SPL_MAX_SIZE definition did not account for all areas that are used by the boot ROM according to the manual, causing boot failures due to truncated SPL images when actually hitting this limit. Signed-off-by: Matthias Schiffer --- include/configs/imx7_spl.h | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index 01d1cd83b2..128f612392 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -18,15 +18,23 @@ * - Set the stack at the end of the free area section, at 0x00946BB8. * - The BOOT ROM loads what they consider the firmware image * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000. - * 64KB is more then enough for the SPL. + * and some padding. However, the manual also states that the ROM uses the + * OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use + * this range for stack and malloc, the SPL itself must fit below 0x920000, + * or the image will be truncated in at least some boot modes like USB SDP. + * Thus our max size is really 0x00920000 - 0x00912000. If necessary, + * CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space + * for the SPL, but 56KB should be more than enough for the SPL. */ -#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0xE000 #define CONFIG_SPL_STACK 0x00946BB8 /* - * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). + * Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding) + * The extra padding could be removed, but this value was used historically + * based on an incorrect CONFIG_SPL_MAX_SIZE definition. + * This allows to write the SPL/U-Boot combination generated with + * u-boot-with-spl.imx directly to a boot media (given that boot media specific + * offset is configured properly). */ #define CONFIG_SPL_PAD_TO 0x11000 From e6f48aad153ae901ca3340b3207968e2f9c47f66 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 29 Sep 2021 16:42:41 +0200 Subject: [PATCH 31/60] imx: imx6ul: Add support for Kontron Electronics SL/BL i.MX6UL/ULL boards (N63xx/N64xx) This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by Kontron Electronics GmbH. Currently there are the following SoM flavors (SoM-Line): * N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND * N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND * N6411: SOM with i.MX6ULL, 512MB RAM, 512MB SPI NAND And the according evaluation boards (Board-Line): * N6310-S: Baseboard with SOM N6310, eMMC, display (optional), ... * N6311-S: Baseboard with SOM N6311, eMMC, display (optional), ... * N6411-S: Baseboard with SOM N6411, eMMC, display (optional), ... Currently U-Boot describes i.MX6UL and i.MX6ULL through separate config options at compile-time. Though the differences are so minor, that for the scope of these SoMs we just use a single defconfig that is compatible with both SoCs. Signed-off-by: Frieder Schrempf Reviewed-by: Stefano Babic --- arch/arm/dts/Makefile | 4 +- .../dts/imx6ul-kontron-n631x-s-u-boot.dtsi | 7 + arch/arm/dts/imx6ul-kontron-n631x-s.dts | 17 + arch/arm/dts/imx6ul-kontron-n631x-som.dtsi | 14 + .../dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi | 63 +++ arch/arm/dts/imx6ul-kontron-n6x1x-s.dts | 423 ++++++++++++++++++ arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi | 420 +++++++++++++++++ .../dts/imx6ul-kontron-n6x1x-som-common.dtsi | 124 +++++ .../dts/imx6ull-kontron-n641x-s-u-boot.dtsi | 7 + arch/arm/dts/imx6ull-kontron-n641x-s.dts | 16 + arch/arm/dts/imx6ull-kontron-n641x-som.dtsi | 13 + arch/arm/mach-imx/mx6/Kconfig | 10 + board/kontron/sl-mx6ul/Kconfig | 15 + board/kontron/sl-mx6ul/MAINTAINERS | 9 + board/kontron/sl-mx6ul/Makefile | 8 + board/kontron/sl-mx6ul/sl-mx6ul.c | 85 ++++ board/kontron/sl-mx6ul/spl.c | 377 ++++++++++++++++ configs/kontron-sl-mx6ul_defconfig | 109 +++++ doc/board/kontron/index.rst | 1 + doc/board/kontron/sl-mx6ul.rst | 43 ++ include/configs/kontron-sl-mx6ul.h | 77 ++++ 21 files changed, 1841 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-kontron-n631x-s.dts create mode 100644 arch/arm/dts/imx6ul-kontron-n631x-som.dtsi create mode 100644 arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ul-kontron-n6x1x-s.dts create mode 100644 arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi create mode 100644 arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi create mode 100644 arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ull-kontron-n641x-s.dts create mode 100644 arch/arm/dts/imx6ull-kontron-n641x-som.dtsi create mode 100644 board/kontron/sl-mx6ul/Kconfig create mode 100644 board/kontron/sl-mx6ul/MAINTAINERS create mode 100644 board/kontron/sl-mx6ul/Makefile create mode 100644 board/kontron/sl-mx6ul/sl-mx6ul.c create mode 100644 board/kontron/sl-mx6ul/spl.c create mode 100644 configs/kontron-sl-mx6ul_defconfig create mode 100644 doc/board/kontron/sl-mx6ul.rst create mode 100644 include/configs/kontron-sl-mx6ul.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 45740a48e0..a0b95d75e9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -815,7 +815,9 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb + imx6ul-pico-pi.dtb \ + imx6ul-kontron-n631x-s.dtb \ + imx6ull-kontron-n641x-s.dtb dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ diff --git a/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi new file mode 100644 index 0000000000..d3f013c58c --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ul-kontron-n631x-s.dts b/arch/arm/dts/imx6ul-kontron-n631x-s.dts new file mode 100644 index 0000000000..407d2b1dab --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n631x-s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +/dts-v1/; + +#include "imx6ul-kontron-n631x-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" + +/ { + model = "Kontron N631X S"; + compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som", + "fsl,imx6ul"; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi b/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi new file mode 100644 index 0000000000..9a1179814b --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n631x-som.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include "imx6ul.dtsi" +#include "imx6ul-kontron-n6x1x-som-common.dtsi" + +/ { + model = "Kontron N631X SOM"; + compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul"; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi new file mode 100644 index 0000000000..39cc6d05d3 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#if defined(CONFIG_FIT) + +/ { + binman: binman { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "SPL"; + }; + + uboot: blob-ext@2 { + offset = <0x11000>; + filename = "u-boot.img"; + }; + }; +}; + +#endif /* CONFIG_FIT */ + +/* + * To make the PHYs work, we need to set the reset pin once. Afterwards + * in Linux we can't assign the shared reset GPIO to the PHYs, as this + * would cause Linux to reset both PHYs every time one of them gets + * reinitialized. + * + * Also we disable the second ethernet as it currently doesn't work with + * the devicetree setup in U-Boot. + */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec2 { + status = "disabled"; + /delete-property/ phy-handle; + /delete-node/ mdio; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts new file mode 100644 index 0000000000..84d8a717ab --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dts @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +/dts-v1/; + +#include +#include "imx6ul-kontron-n6x1x-som.dtsi" + +/ { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "debug-led1"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "debug-led2"; + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "debug-led3"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm8 0 5000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_adc: regulator-vref-adc { + compatible = "regulator-fixed"; + regulator-name = "vref-adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + num-channels = <3>; + vref-supply = <®_vref_adc>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32e61w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <8192>; + address-width = <16>; + }; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + rs485-rts-active-low; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 + >; + }; + + pinctrl_enet2_mdio: enet2mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 + /* + * mux unused RTS to make sure it doesn't cause + * any interrupts when it is undefined + */ + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi new file mode 100644 index 0000000000..4682a79f5b --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include + +/ { + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "debug-led1"; + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "debug-led2"; + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "debug-led3"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm8 0 5000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_adc: regulator-vref-adc { + compatible = "regulator-fixed"; + regulator-name = "vref-adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + num-channels = <3>; + vref-supply = <®_vref_adc>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32e61w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <8192>; + address-width = <16>; + }; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + rs485-rts-active-low; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 + >; + }; + + pinctrl_enet2_mdio: enet2mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 + /* + * mux unused RTS to make sure it doesn't cause + * any interrupts when it is undefined + */ + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi new file mode 100644 index 0000000000..e9ec6b7891 --- /dev/null +++ b/arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + * Copyright (c) 2019 Krzysztof Kozlowski + */ + +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@80000000 { + reg = <0x80000000 0x10000000>; + device_type = "memory"; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec2 { + phy-mode = "rmii"; + status = "disabled"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-nand"; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + reg = <0>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_out>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 + >; + }; + + pinctrl_enet1_mdio: enet1mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_reset_out: rstoutgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi b/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi new file mode 100644 index 0000000000..d3f013c58c --- /dev/null +++ b/arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ull-kontron-n641x-s.dts b/arch/arm/dts/imx6ull-kontron-n641x-s.dts new file mode 100644 index 0000000000..01aeea4085 --- /dev/null +++ b/arch/arm/dts/imx6ull-kontron-n641x-s.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6ull-kontron-n641x-som.dtsi" +#include "imx6ul-kontron-n6x1x-s.dtsi" + +/ { + model = "Kontron N641X S"; + compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som", + "fsl,imx6ull"; +}; diff --git a/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi b/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi new file mode 100644 index 0000000000..8a64aa9a27 --- /dev/null +++ b/arch/arm/dts/imx6ull-kontron-n641x-som.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 exceet electronics GmbH + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include "imx6ull.dtsi" +#include "imx6ul-kontron-n6x1x-som-common.dtsi" + +/ { + model = "Kontron N641X SOM"; + compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull"; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index ee73006ae8..b4c8511cb8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -230,6 +230,15 @@ config TARGET_GW_VENTANA imply CMD_SATA imply CMD_SPL +config TARGET_KONTRON_MX6UL + bool "Kontron Electronics SL/BL i.MX6UL/ULL (N63xx/N64xx)" + depends on MX6UL + select BINMAN + select DM + select DM_THERMAL + select SUPPORT_SPL + imply CMD_DM + config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" select BOARD_LATE_INIT @@ -668,6 +677,7 @@ source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" +source "board/kontron/sl-mx6ul/Kconfig" source "board/kosagi/novena/Kconfig" source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" diff --git a/board/kontron/sl-mx6ul/Kconfig b/board/kontron/sl-mx6ul/Kconfig new file mode 100644 index 0000000000..4e58de2094 --- /dev/null +++ b/board/kontron/sl-mx6ul/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KONTRON_MX6UL + +config SYS_BOARD + string + default "sl-mx6ul" + +config SYS_VENDOR + string + default "kontron" + +config SYS_CONFIG_NAME + string + default "kontron-sl-mx6ul" + +endif diff --git a/board/kontron/sl-mx6ul/MAINTAINERS b/board/kontron/sl-mx6ul/MAINTAINERS new file mode 100644 index 0000000000..0f8b5512d6 --- /dev/null +++ b/board/kontron/sl-mx6ul/MAINTAINERS @@ -0,0 +1,9 @@ +Kontron SL/BL i.MX6UL/ULL Boards (N63xx/N64xx) +M: Frieder Schrempf +S: Maintained +F: arch/arm/dts/imx6ul-kontron-n6* +F: arch/arm/dts/imx6ull-kontron-n6* +F: board/kontron/sl-mx6ul +F: configs/kontron-sl-mx6ul_defconfig +F: doc/board/kontron/sl-mx6ul.rst +F: include/configs/kontron-sl-mx6ul.h diff --git a/board/kontron/sl-mx6ul/Makefile b/board/kontron/sl-mx6ul/Makefile new file mode 100644 index 0000000000..cae273c930 --- /dev/null +++ b/board/kontron/sl-mx6ul/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2018 Kontron Electronics GmbH + +ifdef CONFIG_SPL_BUILD +obj-y := spl.o +else +obj-y := sl-mx6ul.o +endif diff --git a/board/kontron/sl-mx6ul/sl-mx6ul.c b/board/kontron/sl-mx6ul/sl-mx6ul.c new file mode 100644 index 0000000000..79d4d8753b --- /dev/null +++ b/board/kontron/sl-mx6ul/sl-mx6ul.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* + * Overwrite the memory size in the devicetree that is + * passed to the kernel with the actual size detected. + */ + return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + enable_qspi_clk(0); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_fec(); + + return 0; +} diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c new file mode 100644 index 0000000000..12b0352146 --- /dev/null +++ b/board/kontron/sl-mx6ul/spl.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Kontron Electronics GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + BOARD_TYPE_KTN_N631X = 1, + BOARD_TYPE_KTN_N641X, + BOARD_TYPE_MAX +}; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#include +#include + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* RST */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + // This SDHC interface does not use a CD pin + ret = 1; + break; + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", + i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + return 0; +} + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + ? (IMX_GPIO_NR(4, 22)) : -1; +} + +static void setup_spi(void) +{ + gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0"); + gpio_direction_output(IMX_GPIO_NR(4, 22), 1); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + enable_spi_clk(true, 1); +} + +static iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +// DDR 256MB (Hynix H5TQ2G63DFR) +static struct mx6_ddr3_cfg mem_256M_ddr = { + .mem_speed = 800, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1350, + .trcmin = 4950, + .trasmin = 3600, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x01340134, + .p0_mprddlctl = 0x40405052, + .p0_mpwrdlctl = 0x40404E48, +}; + +// DDR 512MB (Hynix H5TQ4G63DFR) +static struct mx6_ddr3_cfg mem_512M_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1350, + .trcmin = 4950, + .trasmin = 3600, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0X01440144, + .p0_mprddlctl = 0x40405454, + .p0_mpwrdlctl = 0x40404E4C, +}; + +// Common DDR parameters (256MB and 512MB) +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000028, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_ctlds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_ras = 0x00000028, + .dram_cas = 0x00000028, + .dram_odt0 = 0x00000028, + .dram_odt1 = 0x00000028, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000028, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_reset = 0x00000028, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 1, /* 2 refresh commands per refresh cycle */ +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + unsigned int size; + + // DDR RAM connection is always 16 bit wide. Init IOs. + mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs); + + // Try to detect the 512MB RAM chip first. + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr); + + // Get the available RAM size + size = get_ram_size((void *)PHYS_SDRAM, SZ_512M); + + gd->ram_size = size; + + if (size == SZ_512M) { + // 512MB RAM was detected + return; + } else if (size == SZ_256M) { + // 256MB RAM was detected, use correct config and calibration + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr); + } else { + printf("Invalid DDR RAM size detected: %x\n", size); + } +} + +static int do_board_detect(void) +{ + if (is_mx6ul()) + gd->board_type = BOARD_TYPE_KTN_N631X; + else if (is_mx6ull()) + gd->board_type = BOARD_TYPE_KTN_N641X; + + printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n", + is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M); + + return 0; +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of UART and SPI */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Detect the board type */ + do_board_detect(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + u32 bootdev = spl_boot_device(); + + /* + * The default boot fuse settings use the SD card (MMC1) as primary + * boot device, but allow SPI NOR as a fallback boot device. + * We can't detect the fallback case and spl_boot_device() will return + * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR. + * Therefore we try to load U-Boot proper vom SPI NOR after loading + * from MMC has failed. + */ + spl_boot_list[0] = bootdev; + + switch (bootdev) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + spl_boot_list[1] = BOOT_DEVICE_SPI; + break; + } +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_spi(); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() && + !strcmp(name, "imx6ul-kontron-n631x-s")) + return 0; + + if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() && + !strcmp(name, "imx6ull-kontron-n641x-s")) + return 0; + + return -1; +} diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig new file mode 100644 index 0000000000..28b5d0d671 --- /dev/null +++ b/configs/kontron-sl-mx6ul_defconfig @@ -0,0 +1,109 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xF0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_TARGET_KONTRON_MX6UL=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-n631x-s" +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_IMX_CONFIG="arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y +CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)" +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="imx6ul-kontron-n631x-s imx6ull-kontron-n641x-s" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=2 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_DM_I2C=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CONS_INDEX=4 +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst index 543b22e2f5..c3fadcef76 100644 --- a/doc/board/kontron/index.rst +++ b/doc/board/kontron/index.rst @@ -7,3 +7,4 @@ Kontron :maxdepth: 2 sl28 + sl-mx6ul diff --git a/doc/board/kontron/sl-mx6ul.rst b/doc/board/kontron/sl-mx6ul.rst new file mode 100644 index 0000000000..b0b0f44db2 --- /dev/null +++ b/doc/board/kontron/sl-mx6ul.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Kontron Electronics SL i.MX6UL/ULL SoM +====================================== + +The Kontron SoM-Line i.MX6UL/ULL (N6x1x) by Kontron Electronics GmbH is a SoM module +with either an i.MX6UL or i.MX6ULL SoC, 256/512 MB DDR3 RAM, SPI NOR, SPI NAND and Ethernet PHY. + +The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0, +RGB, SD card, CAN, RS485, RS232 and much more. + +Quick Start +----------- + +- Build U-Boot +- Boot + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make kontron-sl-mx6ul_defconfig + $ make + +Burn the flash.bin to SD card at an offset of 1 KiB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc + +Boot +^^^^ + +Put the SD card in the slot on the board and apply power. + +Further Information +------------------- + +The bootloader configuration is setup to be used with kernel FIT images. Legacy +images might not be working out of the box. + +Please see https://docs.kontron-electronics.de for further vendor documentation. diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h new file mode 100644 index 0000000000..65aa250894 --- /dev/null +++ b/include/configs/kontron-sl-mx6ul.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Kontron Electronics GmbH + * + * Configuration settings for the Kontron i.MX6UL boards/SoMs. + */ +#ifndef __KONTRON_MX6UL_CONFIG_H +#define __KONTRON_MX6UL_CONFIG_H + +#include +#include + +#include "mx6_common.h" +#ifdef CONFIG_SPL_BUILD +#include "imx6_spl.h" +#endif + +/* RAM */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* Board and environment settings */ +#define CONFIG_MXC_UART_BASE UART4_BASE +#define CONFIG_HOSTNAME "kontron-mx6ul" +#define CONFIG_ETHPRIME "eth0" + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* Boot order for distro boot */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include +#else +#define BOOTENV +#endif + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + "pxefile_addr_r=0x80100000\0" \ + "scriptaddr=0x80100000\0" \ + "bootdelay=3\0" \ + "ethact=" CONFIG_ETHPRIME "\0" \ + "hostname=" CONFIG_HOSTNAME "\0" \ + BOOTENV + +#endif /* __KONTRON_MX6UL_CONFIG_H */ From 5e25a28b6156f5216086ff0b8b8edfce81596a7e Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:16 -0700 Subject: [PATCH 32/60] imx: ventana: add part command Add part command for obtaining info about disk partitions. Signed-off-by: Tim Harvey --- configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 000bdb5949..431368e179 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -54,6 +54,7 @@ CONFIG_CMD_UNZIP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 87851f3524..5c2f73e8df 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -54,6 +54,7 @@ CONFIG_CMD_UNZIP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 8ff8ab472e..587ab05625 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -57,6 +57,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y From 4ecaeb6c0ffc6fd2c7577eafd3efc176b9364818 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:17 -0700 Subject: [PATCH 33/60] imx: ventana: add U-Boot watchdog support Add watchdog support for U-Boot Signed-off-by: Tim Harvey --- configs/gwventana_emmc_defconfig | 6 +++++- configs/gwventana_gw5904_defconfig | 6 +++++- configs/gwventana_nand_defconfig | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 431368e179..51b060f6d0 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -44,7 +44,6 @@ CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER=y -CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " CONFIG_CMD_BOOTZ=y @@ -58,6 +57,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -114,6 +114,8 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y @@ -138,4 +140,6 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_IMX_WATCHDOG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 5c2f73e8df..b873c6c3af 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -44,7 +44,6 @@ CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER=y -CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " CONFIG_CMD_BOOTZ=y @@ -58,6 +57,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -118,6 +118,8 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y @@ -142,4 +144,6 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_IMX_WATCHDOG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 587ab05625..355adc45bd 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -45,7 +45,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER=y -CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Ventana > " CONFIG_CMD_BOOTZ=y @@ -61,6 +60,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -122,6 +122,8 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y @@ -146,4 +148,6 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 +CONFIG_IMX_WATCHDOG=y CONFIG_FDT_FIXUP_PARTITIONS=y From 54347344ce47005848333f953f401cd0c6f691f3 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:18 -0700 Subject: [PATCH 34/60] imx: ventana: remove phy gpio reset from dt We configure network phy configuration for internal delay, LED config, and clock config. If we leave the phy reset gpio defined in dt the kernel may issue a reset to the phy and break these configs. While some may be handled by a kernel phy driver, others may not (typically LED config). Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 79629828d0..16468060f7 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1047,6 +1047,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_board_pci_fixup(blob, bd); #endif + /* + * remove reset gpio control as we configure the PHY registers + * for internal delay, LED config, and clock config in the bootloader + */ + i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec"); + if (i) + fdt_delprop(blob, i, "phy-reset-gpios"); + /* * Peripheral Config: * remove nodes by alias path if EEPROM config tells us the From a0040df98a62b07d010d482beb9b4af77a821392 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:19 -0700 Subject: [PATCH 35/60] imx: ventana: enable additional USB ether devices Enable additional USB ethernet devices. Signed-off-by: Tim Harvey --- configs/gwventana_emmc_defconfig | 5 +++++ configs/gwventana_gw5904_defconfig | 5 +++++ configs/gwventana_nand_defconfig | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 51b060f6d0..ac54814b24 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -122,6 +122,11 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Gateworks" diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index b873c6c3af..543ac2fd8b 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -126,6 +126,11 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Gateworks" diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 355adc45bd..c79e2d75cf 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -130,6 +130,11 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Gateworks" From d75ebf3482c3feb0f7e11a469f7d2766ca7b099a Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:20 -0700 Subject: [PATCH 36/60] imx: ventana: fix splash logo drawing After mxc_ipuv3 DM_VIDEO conversion showing splash image doesn't work. Fix this by adding new requirements: - splashimage env variable. - CONFIG_SPLASH_SCREEN - CONFIG_CMD_BMP Signed-off-by: Tim Harvey --- configs/gwventana_emmc_defconfig | 3 +++ configs/gwventana_gw5904_defconfig | 3 +++ configs/gwventana_nand_defconfig | 3 +++ include/configs/gw_ventana.h | 1 + 4 files changed, 10 insertions(+) diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index ac54814b24..9763fc1239 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -61,6 +61,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y @@ -145,6 +146,8 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 543ac2fd8b..5d9db220fd 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -61,6 +61,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y @@ -149,6 +150,8 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index c79e2d75cf..8e30eea208 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -64,6 +64,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y @@ -153,6 +154,8 @@ CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 3f6afc1646..170d6a7bf0 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -107,6 +107,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ "splashpos=m,m\0" \ + "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "bootdevs=usb mmc sata flash\0" \ From 397d697fd4707043511fdad34f2f75274a4a54d0 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:21 -0700 Subject: [PATCH 37/60] imx: ventana: update LVDS support Enable LVDS display detection and panel-specific configuration Make I2C based LVDS detection and configuration model specific: - not all boards support LVDS connectors; fail detection that do not support LVDS to avoid misdetecting an I2C device as a display - GPIO configuration is panel specific; use panel name where needed Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana.c | 59 ++++++++++++++++++------- 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 16468060f7..1c82bd5067 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -158,25 +158,54 @@ static void enable_hdmi(struct display_info_t const *dev) imx_enable_hdmi_phy(); } -static int detect_i2c(struct display_info_t const *dev) +static int detect_lvds(struct display_info_t const *dev) { + /* only the following boards support LVDS connectors */ + switch (board_type) { + case GW52xx: + case GW53xx: + case GW54xx: + case GW560x: + case GW5905: + case GW5909: + break; + default: + return 0; + } + return i2c_set_bus_num(dev->bus) == 0 && i2c_probe(dev->addr) == 0; } static void enable_lvds(struct display_info_t const *dev) { - struct iomuxc *iomux = (struct iomuxc *) - IOMUXC_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ u32 reg = readl(&iomux->gpr[2]); reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; writel(reg, &iomux->gpr[2]); - /* Enable Backlight */ - gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); - gpio_direction_output(IMX_GPIO_NR(1, 10), 0); + /* Configure GPIO */ + switch (board_type) { + case GW52xx: + case GW53xx: + case GW54xx: + if (!strncmp(dev->mode.name, "Hannstar", 8)) { + SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); + gpio_request(IMX_GPIO_NR(1, 10), "cabc"); + gpio_direction_output(IMX_GPIO_NR(1, 10), 0); + } else if (!strncmp(dev->mode.name, "DLC", 3)) { + SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); + gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#"); + gpio_direction_output(IMX_GPIO_NR(1, 10), 1); + } + break; + default: + break; + } + + /* Configure backlight */ gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 18), 1); @@ -208,7 +237,7 @@ struct display_info_t const displays[] = {{ .bus = 2, .addr = 0x4, .pixfmt = IPU_PIX_FMT_LVDS666, - .detect = detect_i2c, + .detect = detect_lvds, .enable = enable_lvds, .mode = { .name = "Hannstar-XGA", @@ -228,7 +257,7 @@ struct display_info_t const displays[] = {{ /* DLC700JMG-T-4 */ .bus = 2, .addr = 0x38, - .detect = NULL, + .detect = detect_lvds, .enable = enable_lvds, .pixfmt = IPU_PIX_FMT_LVDS666, .mode = { @@ -247,9 +276,9 @@ struct display_info_t const displays[] = {{ .vmode = FB_VMODE_NONINTERLACED } }, { /* DLC0700XDP21LF-C-1 */ - .bus = 0, - .addr = 0, - .detect = NULL, + .bus = 2, + .addr = 0x38, + .detect = detect_lvds, .enable = enable_lvds, .pixfmt = IPU_PIX_FMT_LVDS666, .mode = { @@ -270,7 +299,7 @@ struct display_info_t const displays[] = {{ /* DLC800FIG-T-3 */ .bus = 2, .addr = 0x14, - .detect = NULL, + .detect = detect_lvds, .enable = enable_lvds, .pixfmt = IPU_PIX_FMT_LVDS666, .mode = { @@ -290,7 +319,7 @@ struct display_info_t const displays[] = {{ } }, { .bus = 2, .addr = 0x5d, - .detect = detect_i2c, + .detect = detect_lvds, .enable = enable_lvds, .pixfmt = IPU_PIX_FMT_LVDS666, .mode = { @@ -358,10 +387,6 @@ static void setup_display(void) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <gpr[3]); - - /* LVDS Backlight GPIO on LVDS connector - output low */ - SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); - gpio_direction_output(IMX_GPIO_NR(1, 10), 0); } #endif /* CONFIG_VIDEO_IPUV3 */ From 073b105e794d7aae9b62cac68109a6aa8caa3483 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Sep 2021 15:04:22 -0700 Subject: [PATCH 38/60] imx: ventana: fix USB hub reset Remove board_ehci_hcd_init function that is not used with DM_USB and replace its functionality with device-tree configuraton that treats USB HUB RST# as a gpio enable for the usbh1 vbus regulator. Signed-off-by: Tim Harvey --- arch/arm/dts/imx6qdl-gw53xx.dtsi | 11 +++++++- arch/arm/dts/imx6qdl-gw54xx.dtsi | 11 +++++++- arch/arm/dts/imx6qdl-gw552x.dtsi | 21 ++++++++++++++- arch/arm/dts/imx6qdl-gw560x.dtsi | 3 ++- arch/arm/dts/imx6qdl-gw5904.dtsi | 11 +++++++- arch/arm/dts/imx6qdl-gw5912.dtsi | 11 +++++++- board/gateworks/gw_ventana/gw_ventana.c | 35 ------------------------- 7 files changed, 62 insertions(+), 41 deletions(-) diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 904b228306..77ac103c2d 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -137,7 +137,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { @@ -550,6 +551,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -720,6 +723,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index ffed4fb550..98c81e9c9b 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -146,7 +146,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator@3 { @@ -620,6 +621,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -815,6 +818,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 diff --git a/arch/arm/dts/imx6qdl-gw552x.dtsi b/arch/arm/dts/imx6qdl-gw552x.dtsi index f6742e5131..b853399aec 100644 --- a/arch/arm/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/dts/imx6qdl-gw552x.dtsi @@ -121,6 +121,15 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_usb_h1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &gpmi { @@ -390,9 +399,13 @@ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; }; + status = "okay"; +}; &usbh1 { + vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -507,6 +520,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index 5da19756e0..1e95267c97 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -221,7 +221,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index b5ed2d83c1..286c7a9924 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -176,7 +176,8 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; }; reg_usb_otg_vbus: regulator-usb-otg-vbus { @@ -593,6 +594,8 @@ &usbh1 { vbus-supply = <®_usb_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; status = "okay"; }; @@ -753,6 +756,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi index 2537288627..8fd8fdb514 100644 --- a/arch/arm/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -120,7 +120,8 @@ regulator-name = "usb_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; + gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; @@ -380,6 +381,8 @@ &usbh1 { vbus-supply = <®_usb_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; status = "okay"; }; @@ -560,6 +563,12 @@ >; }; + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 1c82bd5067..8cf7914670 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -39,41 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; struct ventana_board_info ventana_info; static int board_type; -#ifdef CONFIG_USB_EHCI_MX6 -/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */ -int board_ehci_hcd_init(int port) -{ - int gpio; - - /* USB HUB is always on P1 */ - if (port == 0) - return 0; - - /* Reset USB HUB */ - switch (board_type) { - case GW53xx: - case GW552x: - case GW5906: - gpio = (IMX_GPIO_NR(1, 9)); - break; - case GW54proto: - case GW54xx: - gpio = (IMX_GPIO_NR(1, 16)); - break; - default: - return 0; - } - - /* request and toggle hub rst */ - gpio_request(gpio, "usb_hub_rst#"); - gpio_direction_output(gpio, 0); - mdelay(2); - gpio_set_value(gpio, 1); - - return 0; -} -#endif /* CONFIG_USB_EHCI_MX6 */ - /* configure eth0 PHY board-specific LED behavior */ int board_phy_config(struct phy_device *phydev) { From 23ce06b24648a46e9fc6fa82c40e95f13078c0f4 Mon Sep 17 00:00:00 2001 From: Andrej Rosano Date: Tue, 17 Aug 2021 11:34:03 +0200 Subject: [PATCH 39/60] imx53: usbarmory: Use ethernet driver model Enable ethernet driver model as it is mandatory. Signed-off-by: Andrej Rosano --- configs/usbarmory_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index f259554645..a4cdccad2b 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -39,3 +39,4 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y +CONFIG_DM_ETH=y From 9cab87f184bc7689fba1c856c3c8af0c7b4566ed Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 29 Sep 2021 16:42:42 +0200 Subject: [PATCH 40/60] imx: imx8mm: Add support for Kontron Electronics SL/BL i.MX8M-Mini boards (N801x) The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC. The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2.0, HDMI/LVDS, SD card, CAN, RS485 and much more. Signed-off-by: Frieder Schrempf Reviewed-by: Stefano Babic Tested-by: Heiko Thiery --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts | 116 ++ .../dts/imx8mm-kontron-n801x-s-u-boot.dtsi | 274 +++ arch/arm/dts/imx8mm-kontron-n801x-s.dts | 388 ++++ arch/arm/dts/imx8mm-kontron-n801x-som.dtsi | 299 +++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/kontron/sl-mx8mm/Kconfig | 15 + board/kontron/sl-mx8mm/MAINTAINERS | 8 + board/kontron/sl-mx8mm/Makefile | 9 + board/kontron/sl-mx8mm/imximage.cfg | 9 + board/kontron/sl-mx8mm/lpddr4_timing.c | 1844 +++++++++++++++++ board/kontron/sl-mx8mm/sl-mx8mm.c | 99 + board/kontron/sl-mx8mm/spl.c | 321 +++ configs/kontron-sl-mx8mm_defconfig | 140 ++ doc/board/kontron/index.rst | 1 + doc/board/kontron/sl-mx8mm.rst | 85 + include/configs/kontron-sl-mx8mm.h | 87 + 17 files changed, 3705 insertions(+) create mode 100644 arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts create mode 100644 arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-kontron-n801x-s.dts create mode 100644 arch/arm/dts/imx8mm-kontron-n801x-som.dtsi create mode 100644 board/kontron/sl-mx8mm/Kconfig create mode 100644 board/kontron/sl-mx8mm/MAINTAINERS create mode 100644 board/kontron/sl-mx8mm/Makefile create mode 100644 board/kontron/sl-mx8mm/imximage.cfg create mode 100644 board/kontron/sl-mx8mm/lpddr4_timing.c create mode 100644 board/kontron/sl-mx8mm/sl-mx8mm.c create mode 100644 board/kontron/sl-mx8mm/spl.c create mode 100644 configs/kontron-sl-mx8mm_defconfig create mode 100644 doc/board/kontron/sl-mx8mm.rst create mode 100644 include/configs/kontron-sl-mx8mm.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a0b95d75e9..6168d8d459 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -872,6 +872,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ + imx8mm-kontron-n801x-s.dtb \ + imx8mm-kontron-n801x-s-lvds.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts b/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts new file mode 100644 index 0000000000..dd1addea70 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm-kontron-n801x-s.dts" + +/ { + model = "Kontron i.MX8MM N801X S LVDS"; + compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */ + power-supply = <®_vdd_24v>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + status = "okay"; + }; + + reg_panel_pwr: regpanel-pwr { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_pwr"; + regulator-always-on; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_rst: regpanel-rst { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_rst"; + regulator-always-on; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_stby: regpanel-stby { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_stby"; + regulator-always-on; + gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_hinv: regpanel-hinv { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_hinv"; + regulator-always-on; + gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_panel_vinv: regpanel-vinv { + compatible = "regulator-fixed"; + regulator-name = "reg_panel_vinv"; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_24v: regulator-24v { + compatible = "regulator-fixed"; + regulator-name = "reg-vdd-24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-boot-on; + regulator-always-on; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + gt911@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio3>; + interrupts = <22 8>; + reset-gpios = <&gpio3 23 0>; + irq-gpios = <&gpio3 22 0>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */ + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */ + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi new file mode 100644 index 0000000000..5e368a61bc --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm-u-boot.dtsi" + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + binman: binman { + multiple-images; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&fec1 { + phy-mode = "rgmii-rxid"; +}; + +&i2c1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&i2c2 { + status = "okay"; + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + /* Disable Pullup for SD_VSEL */ + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41 + >; +}; + +&pinctrl_uart3 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pca9450 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&ecspi1 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart3 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + size = <0x4000>; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = ; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = ; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x920000>; + entry = <0x920000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "spl.bin"; + }; + + uboot: blob-ext@2 { + offset = <0x57c00>; + filename = "u-boot.itb"; + }; + }; + + u-boot-update { + filename = "firmware-update.itb"; + + fit { + description = "Configuration for firmware update file"; + + images { + flash-bin { + description = "U-Boot flash image"; + type = "firmware"; + os = "u-boot"; + arch = "arm"; + compress = "none"; + load = <0>; /* unused */ + + blob { + filename = "flash.bin"; + }; + + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s.dts b/arch/arm/dts/imx8mm-kontron-n801x-s.dts new file mode 100644 index 0000000000..c796d144e2 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-s.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n801x-som.dtsi" +#include + +/ { + model = "Kontron i.MX8MM N801X S"; + compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + aliases { + ethernet1 = &usbnet; + }; + + /* fixed crystal dedicated to mcp2515 */ + osc_can: clock-osc-can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "osc-can"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led1 { + label = "led1"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "led3"; + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + }; + + led4 { + label = "led4"; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + }; + + led5 { + label = "led5"; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + }; + + led6 { + label = "led6"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible = "regulator-fixed"; + regulator-name = "rst-usb-eth2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth2>; + gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_vdd_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&osc_can>; + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rgmii-rxid"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.0570"; + reg = <0>; + reset-assert-us = <100>; + reset-deassert-us = <100>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + vsc8531,led-0-mode = ; + vsc8531,led-1-mode = ; + vsc8531,led-0-combine-disable; + }; + }; +}; + +&gpio4 { + dsi_mux_sel: dsi_mux_sel { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "dsi-mux-sel"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_sel>; + }; + + dsi_mux_oe { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-high; + line-name = "dsi-mux-oe"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_oe>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_dsi_sel: dsiselgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + >; + }; + + pinctrl_dsi_oe: dsioegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi new file mode 100644 index 0000000000..c3418d263e --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "Kontron i.MX8MM N801X SoM"; + compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg = <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index dfda4cb70e..41088a2dcd 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -75,6 +75,13 @@ config TARGET_IMX8MM_VENICE select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_KONTRON_MX8MM + bool "Kontron Electronics N80xx" + select BINMAN + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" select BINMAN @@ -157,6 +164,7 @@ source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" source "board/gateworks/venice/Kconfig" source "board/google/imx8mq_phanbell/Kconfig" +source "board/kontron/sl-mx8mm/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" diff --git a/board/kontron/sl-mx8mm/Kconfig b/board/kontron/sl-mx8mm/Kconfig new file mode 100644 index 0000000000..9dcf407c86 --- /dev/null +++ b/board/kontron/sl-mx8mm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_KONTRON_MX8MM + +config SYS_BOARD + string + default "sl-mx8mm" + +config SYS_VENDOR + string + default "kontron" + +config SYS_CONFIG_NAME + string + default "kontron-sl-mx8mm" + +endif diff --git a/board/kontron/sl-mx8mm/MAINTAINERS b/board/kontron/sl-mx8mm/MAINTAINERS new file mode 100644 index 0000000000..5e68ae0305 --- /dev/null +++ b/board/kontron/sl-mx8mm/MAINTAINERS @@ -0,0 +1,8 @@ +Kontron SL/BL i.MX8M Mini Boards (N801x) +M: Frieder Schrempf +S: Maintained +F: arch/arm/dts/imx8mm-kontron-n801x-* +F: board/kontron/sl-mx8mm +F: configs/kontron-sl-mx8mm_defconfig +F: doc/board/kontron/sl-mx8mm.rst +F: include/configs/kontron-sl-mx8mm.h diff --git a/board/kontron/sl-mx8mm/Makefile b/board/kontron/sl-mx8mm/Makefile new file mode 100644 index 0000000000..fceed684ed --- /dev/null +++ b/board/kontron/sl-mx8mm/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2019 Kontron Electronics GmbH + +obj-y := sl-mx8mm.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/kontron/sl-mx8mm/imximage.cfg b/board/kontron/sl-mx8mm/imximage.cfg new file mode 100644 index 0000000000..f101f3d228 --- /dev/null +++ b/board/kontron/sl-mx8mm/imximage.cfg @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#define __ASSEMBLY__ + +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c new file mode 100644 index 0000000000..0eabb16018 --- /dev/null +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -0,0 +1,1844 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include +#include +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304, 0x1}, + {0x3d400030, 0x1}, + {0x3d400000, 0xa3080020}, + {0x3d400020, 0x223}, + {0x3d400024, 0x3a980}, + {0x3d400064, 0x5b0087}, + {0x3d4000d0, 0xc00305ba}, + {0x3d4000d4, 0x940000}, + {0x3d4000dc, 0xd4002d}, + {0x3d4000e0, 0x310000}, + {0x3d4000e8, 0x66004d}, + {0x3d4000ec, 0x16004d}, + {0x3d400100, 0x191e1920}, + {0x3d400104, 0x60630}, + {0x3d40010c, 0xb0b000}, + {0x3d400110, 0xe04080e}, + {0x3d400114, 0x2040c0c}, + {0x3d400118, 0x1010007}, + {0x3d40011c, 0x401}, + {0x3d400130, 0x20600}, + {0x3d400134, 0xc100002}, + {0x3d400138, 0xd8}, + {0x3d400144, 0x96004b}, + {0x3d400180, 0x2ee0017}, + {0x3d400184, 0x2605b8e}, + {0x3d400188, 0x0}, + {0x3d400190, 0x497820a}, + {0x3d400194, 0x80303}, + {0x3d4001b4, 0x170a}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0xdf00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x11}, + {0x3d4001c0, 0x1}, + {0x3d4001c4, 0x1}, + {0x3d4000f4, 0xc99}, + {0x3d400108, 0x70e1617}, + {0x3d400200, 0x17}, + {0x3d40020c, 0x0}, + {0x3d400210, 0x1f1f}, + {0x3d400204, 0x80808}, + {0x3d400214, 0x7070707}, + {0x3d400218, 0x7070707}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x2c}, + {0x3d40025c, 0x4000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x2005574}, + {0x3d400400, 0x111}, + {0x3d400408, 0x72ff}, + {0x3d400494, 0x2100e07}, + {0x3d400498, 0x620096}, + {0x3d40049c, 0x1100e07}, + {0x3d4004a0, 0xc8012c}, + {0x3d402020, 0x21}, + {0x3d402024, 0x7d00}, + {0x3d402050, 0x20d040}, + {0x3d402064, 0xc001c}, + {0x3d4020dc, 0x840000}, + {0x3d4020e0, 0x310000}, + {0x3d4020e8, 0x66004d}, + {0x3d4020ec, 0x16004d}, + {0x3d402100, 0xa040305}, + {0x3d402104, 0x30407}, + {0x3d402108, 0x203060b}, + {0x3d40210c, 0x505000}, + {0x3d402110, 0x2040202}, + {0x3d402114, 0x2030202}, + {0x3d402118, 0x1010004}, + {0x3d40211c, 0x301}, + {0x3d402130, 0x20300}, + {0x3d402134, 0xa100002}, + {0x3d402138, 0x1d}, + {0x3d402144, 0x14000a}, + {0x3d402180, 0x640004}, + {0x3d402190, 0x3818200}, + {0x3d402194, 0x80303}, + {0x3d4021b4, 0x100}, + {0x3d403020, 0x21}, + {0x3d403024, 0x1f40}, + {0x3d403050, 0x20d040}, + {0x3d403064, 0x30007}, + {0x3d4030dc, 0x840000}, + {0x3d4030e0, 0x310000}, + {0x3d4030e8, 0x66004d}, + {0x3d4030ec, 0x16004d}, + {0x3d403100, 0xa010102}, + {0x3d403104, 0x30404}, + {0x3d403108, 0x203060b}, + {0x3d40310c, 0x505000}, + {0x3d403110, 0x2040202}, + {0x3d403114, 0x2030202}, + {0x3d403118, 0x1010004}, + {0x3d40311c, 0x301}, + {0x3d403130, 0x20300}, + {0x3d403134, 0xa100002}, + {0x3d403138, 0x8}, + {0x3d403144, 0x50003}, + {0x3d403180, 0x190004}, + {0x3d403190, 0x3818200}, + {0x3d403194, 0x80303}, + {0x3d4031b4, 0x100}, + {0x3d400028, 0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x3}, + {0x110a3, 0x4}, + {0x110a4, 0x5}, + {0x110a5, 0x2}, + {0x110a6, 0x7}, + {0x110a7, 0x6}, + {0x120a0, 0x0}, + {0x120a1, 0x1}, + {0x120a2, 0x3}, + {0x120a3, 0x2}, + {0x120a4, 0x5}, + {0x120a5, 0x4}, + {0x120a6, 0x7}, + {0x120a7, 0x6}, + {0x130a0, 0x0}, + {0x130a1, 0x1}, + {0x130a2, 0x2}, + {0x130a3, 0x3}, + {0x130a4, 0x4}, + {0x130a5, 0x5}, + {0x130a6, 0x6}, + {0x130a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x1205f, 0x1ff}, + {0x1215f, 0x1ff}, + {0x1305f, 0x1ff}, + {0x1315f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x11205f, 0x1ff}, + {0x11215f, 0x1ff}, + {0x11305f, 0x1ff}, + {0x11315f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x21205f, 0x1ff}, + {0x21215f, 0x1ff}, + {0x21305f, 0x1ff}, + {0x21315f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x3055, 0x1ff}, + {0x4055, 0x1ff}, + {0x5055, 0x1ff}, + {0x6055, 0x1ff}, + {0x7055, 0x1ff}, + {0x8055, 0x1ff}, + {0x9055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0x7}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1ab}, + {0x2003a, 0x0}, + {0x120024, 0x1ab}, + {0x2003a, 0x0}, + {0x220024, 0x1ab}, + {0x2003a, 0x0}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0xe00}, + {0x1014d, 0xe00}, + {0x1104d, 0xe00}, + {0x1114d, 0xe00}, + {0x1204d, 0xe00}, + {0x1214d, 0xe00}, + {0x1304d, 0xe00}, + {0x1314d, 0xe00}, + {0x11004d, 0xe00}, + {0x11014d, 0xe00}, + {0x11104d, 0xe00}, + {0x11114d, 0xe00}, + {0x11204d, 0xe00}, + {0x11214d, 0xe00}, + {0x11304d, 0xe00}, + {0x11314d, 0xe00}, + {0x21004d, 0xe00}, + {0x21014d, 0xe00}, + {0x21104d, 0xe00}, + {0x21114d, 0xe00}, + {0x21204d, 0xe00}, + {0x21214d, 0xe00}, + {0x21304d, 0xe00}, + {0x21314d, 0xe00}, + {0x10049, 0xeba}, + {0x10149, 0xeba}, + {0x11049, 0xeba}, + {0x11149, 0xeba}, + {0x12049, 0xeba}, + {0x12149, 0xeba}, + {0x13049, 0xeba}, + {0x13149, 0xeba}, + {0x110049, 0xeba}, + {0x110149, 0xeba}, + {0x111049, 0xeba}, + {0x111149, 0xeba}, + {0x112049, 0xeba}, + {0x112149, 0xeba}, + {0x113049, 0xeba}, + {0x113149, 0xeba}, + {0x210049, 0xeba}, + {0x210149, 0xeba}, + {0x211049, 0xeba}, + {0x211149, 0xeba}, + {0x212049, 0xeba}, + {0x212149, 0xeba}, + {0x213049, 0xeba}, + {0x213149, 0xeba}, + {0x43, 0x63}, + {0x1043, 0x63}, + {0x2043, 0x63}, + {0x3043, 0x63}, + {0x4043, 0x63}, + {0x5043, 0x63}, + {0x6043, 0x63}, + {0x7043, 0x63}, + {0x8043, 0x63}, + {0x9043, 0x63}, + {0x20018, 0x3}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x20008, 0x2ee}, + {0x120008, 0x64}, + {0x220008, 0x19}, + {0x20088, 0x9}, + {0x200b2, 0xdc}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x12043, 0x5a1}, + {0x12143, 0x5a1}, + {0x13043, 0x5a1}, + {0x13143, 0x5a1}, + {0x1200b2, 0xdc}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x112043, 0x5a1}, + {0x112143, 0x5a1}, + {0x113043, 0x5a1}, + {0x113143, 0x5a1}, + {0x2200b2, 0xdc}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x212043, 0x5a1}, + {0x212143, 0x5a1}, + {0x213043, 0x5a1}, + {0x213143, 0x5a1}, + {0x200fa, 0x1}, + {0x1200fa, 0x1}, + {0x2200fa, 0x1}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x660}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5665}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x2200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, + {0x2200ca, 0x24}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x101}, + {0x54003, 0x190}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x64}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400d, 0x100}, + {0x54012, 0x310}, + {0x54019, 0x84}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x84}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0x8400}, + {0x54033, 0x3100}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0x8400}, + {0x54039, 0x3100}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + {0xd0000, 0x1}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xbb8}, + {0x54004, 0x2}, + {0x54005, 0x2228}, + {0x54006, 0x11}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x2}, + {0x5400f, 0x100}, + {0x54010, 0x1f7f}, + {0x54012, 0x310}, + {0x54019, 0x2dd4}, + {0x5401a, 0x31}, + {0x5401b, 0x4d66}, + {0x5401c, 0x4d00}, + {0x5401e, 0x16}, + {0x5401f, 0x2dd4}, + {0x54020, 0x31}, + {0x54021, 0x4d66}, + {0x54022, 0x4d00}, + {0x54024, 0x16}, + {0x5402b, 0x1000}, + {0x5402c, 0x3}, + {0x54032, 0xd400}, + {0x54033, 0x312d}, + {0x54034, 0x6600}, + {0x54035, 0x4d}, + {0x54036, 0x4d}, + {0x54037, 0x1600}, + {0x54038, 0xd400}, + {0x54039, 0x312d}, + {0x5403a, 0x6600}, + {0x5403b, 0x4d}, + {0x5403c, 0x4d}, + {0x5403d, 0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xf}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x630}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x630}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x630}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x630}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x630}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x630}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x630}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x630}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x630}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x630}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x630}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x630}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x630}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xa}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x2}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x900a4, 0x10}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x623}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x623}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x790}, + {0x900a9, 0x11a}, + {0x900aa, 0x8}, + {0x900ab, 0x7aa}, + {0x900ac, 0x2a}, + {0x900ad, 0x10}, + {0x900ae, 0x7b2}, + {0x900af, 0x2a}, + {0x900b0, 0x0}, + {0x900b1, 0x7c8}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x0}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xc}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x0}, + {0x90169, 0x8}, + {0x9016a, 0x8}, + {0x9016b, 0x448}, + {0x9016c, 0x109}, + {0x9016d, 0xf}, + {0x9016e, 0x7c0}, + {0x9016f, 0x109}, + {0x90170, 0x0}, + {0x90171, 0xe8}, + {0x90172, 0x109}, + {0x90173, 0x47}, + {0x90174, 0x630}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0x618}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0xe0}, + {0x9017b, 0x109}, + {0x9017c, 0x0}, + {0x9017d, 0x7c8}, + {0x9017e, 0x109}, + {0x9017f, 0x8}, + {0x90180, 0x8140}, + {0x90181, 0x10c}, + {0x90182, 0x0}, + {0x90183, 0x1}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x4}, + {0x90187, 0x8}, + {0x90188, 0x8}, + {0x90189, 0x7c8}, + {0x9018a, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2a}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x5d}, + {0x2000c, 0xbb}, + {0x2000d, 0x753}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x60}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x220010, 0x5a}, + {0x220011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x12011, 0x1}, + {0x12012, 0x1}, + {0x12013, 0x180}, + {0x12018, 0x1}, + {0x12002, 0x6209}, + {0x120b2, 0x1}, + {0x121b4, 0x1}, + {0x122b4, 0x1}, + {0x123b4, 0x1}, + {0x124b4, 0x1}, + {0x125b4, 0x1}, + {0x126b4, 0x1}, + {0x127b4, 0x1}, + {0x128b4, 0x1}, + {0x13011, 0x1}, + {0x13012, 0x1}, + {0x13013, 0x180}, + {0x13018, 0x1}, + {0x13002, 0x6209}, + {0x130b2, 0x1}, + {0x131b4, 0x1}, + {0x132b4, 0x1}, + {0x133b4, 0x1}, + {0x134b4, 0x1}, + {0x135b4, 0x1}, + {0x136b4, 0x1}, + {0x137b4, 0x1}, + {0x138b4, 0x1}, + {0x2003a, 0x2}, + {0xc0080, 0x2}, + {0xd0000, 0x1} +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c new file mode 100644 index 0000000000..48376cb826 --- /dev/null +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_phys_sdram_size(phys_size_t *size) +{ + u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR); + + if (ddr_size == 4) { + *size = 0x100000000; + } else if (ddr_size == 3) { + *size = 0xc0000000; + } else if (ddr_size == 2) { + *size = 0x80000000; + } else if (ddr_size == 1) { + *size = 0x40000000; + } else { + printf("Unknown DDR type!!!\n"); + *size = 0x40000000; + } + + return 0; +} + +/* + * If the SoM is mounted on a baseboard with a USB ethernet controller, + * there might be an additional MAC address programmed to the MAC OTP fuses. + * Although the i.MX8MM has only one MAC, the MAC0, MAC1 and MAC2 registers + * in the OTP fuses can still be used to store two separate addresses. + * Try to read the secondary address from MAC1 and MAC2 and adjust the + * devicetree so Linux can pick up the MAC address. + */ +int fdt_set_usb_eth_addr(void *blob) +{ + u32 value = readl(OCOTP_BASE_ADDR + 0x660); + unsigned char mac[6]; + int node, ret; + + mac[0] = value >> 24; + mac[1] = value >> 16; + mac[2] = value >> 8; + mac[3] = value; + + value = readl(OCOTP_BASE_ADDR + 0x650); + mac[4] = value >> 24; + mac[5] = value >> 16; + + node = fdt_path_offset(blob, fdt_get_alias(blob, "ethernet1")); + if (node < 0) { + /* + * There is no node for the USB ethernet in the devicetree. Just skip. + */ + return 0; + } + + if (is_zero_ethaddr(mac)) { + printf("\nNo MAC address for USB ethernet set in OTP fuses!\n"); + return 0; + } + + if (!is_valid_ethaddr(mac)) { + printf("\nInvalid MAC address for USB ethernet set in OTP fuses!\n"); + return -EINVAL; + } + + ret = fdt_setprop(blob, node, "local-mac-address", &mac, 6); + if (ret) + ret = fdt_setprop(blob, node, "mac-address", &mac, 6); + + if (ret) + printf("\nMissing mac-address or local-mac-address property in dt, skip setting MAC address for USB ethernet\n"); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int ret = fdt_set_usb_eth_addr(blob); + + if (ret) + return ret; + + return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size); +} + +int board_init(void) +{ + return 0; +} diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c new file mode 100644 index 0000000000..4ef03c8c17 --- /dev/null +++ b/board/kontron/sl-mx8mm/spl.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + BOARD_TYPE_KTN_N801X, + BOARD_TYPE_KTN_N801X_LVDS, + BOARD_TYPE_MAX +}; + +#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23) + +static iomux_v3_cfg_t const i2c1_pads[] = { + IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION, + IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION +}; + +static iomux_v3_cfg_t const i2c2_pads[] = { + IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION, + IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION +}; + +static iomux_v3_cfg_t const touch_gpio[] = { + IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL) +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case SPI_NOR_BOOT: + return BOOT_DEVICE_SPI; + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + default: + return BOOT_DEVICE_NONE; + } +} + +bool check_ram_available(long size) +{ + long sz = get_ram_size((long *)PHYS_SDRAM, size); + + if (sz == size) + return true; + + return false; +} + +static void spl_dram_init(void) +{ + u32 size = 0; + + /* + * Try the default DDR settings in lpddr4_timing.c to + * comply with the Micron 4GB DDR. + */ + if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) { + size = 4; + } else { + /* + * Overwrite some values to comply with the Micron 1GB/2GB DDRs. + */ + dram_timing.ddrc_cfg[2].val = 0xa1080020; + dram_timing.ddrc_cfg[37].val = 0x1f; + + dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1; + dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1; + dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1; + dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1; + + if (!ddr_init(&dram_timing)) { + if (check_ram_available(SZ_2G)) + size = 2; + else if (check_ram_available(SZ_1G)) + size = 1; + } + } + + if (size == 0) { + printf("Failed to initialize DDR RAM!\n"); + size = 1; + } + + printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size); + writel(size, M4_BOOTROM_BASE_ADDR); +} + +static void touch_reset(void) +{ + /* + * Toggle the reset of the touch panel. + */ + imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio)); + + gpio_request(TOUCH_RESET_GPIO, "touch_reset"); + gpio_direction_output(TOUCH_RESET_GPIO, 0); + mdelay(20); + gpio_direction_output(TOUCH_RESET_GPIO, 1); + mdelay(20); +} + +static int i2c_detect(u8 bus, u16 addr) +{ + struct udevice *udev; + int ret; + + /* + * Try to probe the touch controller to check if an LVDS panel is + * connected. + */ + ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev); + if (ret == 0) + return 0; + + return 1; +} + +int do_board_detect(void) +{ + bool lvds = false; + + /* + * Check the I2C touch controller to detect a LVDS panel. + */ + imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads)); + touch_reset(); + + if (i2c_detect(1, 0x5d) == 0) { + printf("Touch controller detected, assuming LVDS panel...\n"); + lvds = true; + } + + /* + * Check the I2C PMIC to detect the deprecated SoM with DA9063. + */ + imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); + + if (i2c_detect(0, 0x58) == 0) { + printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n"); + printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n"); + printf("### PLEASE UPGRADE TO LATEST MODULE ###\n"); + } + + if (lvds) + gd->board_type = BOARD_TYPE_KTN_N801X_LVDS; + else + gd->board_type = BOARD_TYPE_KTN_N801X; + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() && + !strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27)) + return 0; + + if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() && + !strncmp(name, "imx8mm-kontron-n801x-s", 22)) + return 0; + + return -1; +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + puts("Normal Boot\n"); + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) + printf("Failed to find clock node. Check device tree\n"); +} + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +static int power_init_board(void) +{ + struct udevice *dev; + int ret = pmic_get("pmic@25", &dev); + + if (ret == -ENODEV) + puts("No pmic found\n"); + + if (ret) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* increase VDD_DRAM to 0.95V for 1.5GHz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c); + + /* set VDD_SNVS_0V8 from default 0.85V to 0.8V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(2); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* PMIC initialization */ + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + /* Detect the board type */ + do_board_detect(); + + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + u32 bootdev = spl_boot_device(); + + /* + * The default boot fuse settings use the SD card (MMC2) as primary + * boot device, but allow SPI NOR as a fallback boot device. + * We can't detect the fallback case and spl_boot_device() will return + * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR. + * Therefore we try to load U-Boot proper vom SPI NOR after loading + * from MMC has failed. + */ + spl_boot_list[0] = bootdev; + + switch (bootdev) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + spl_boot_list[1] = BOOT_DEVICE_SPI; + break; + } +} diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig new file mode 100644 index 0000000000..06c57b7555 --- /dev/null +++ b/configs/kontron-sl-mx8mm_defconfig @@ -0,0 +1,140 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x1f0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_KONTRON_MX8MM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kontron/sl-mx8mm/imximage.cfg" +CONFIG_BOARD_TYPES=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_FIT_IMAGE_TINY is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 +CONFIG_SPL_WATCHDOG=y +CONFIG_SPL_ATF=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=80000000 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_SF=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_MACRONIX=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MSCC=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV8803=y +CONFIG_CONS_INDEX=2 +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_IMX_WATCHDOG=y +# CONFIG_HEXDUMP is not set +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst index c3fadcef76..7dfe3d9bc0 100644 --- a/doc/board/kontron/index.rst +++ b/doc/board/kontron/index.rst @@ -8,3 +8,4 @@ Kontron sl28 sl-mx6ul + sl-mx8mm diff --git a/doc/board/kontron/sl-mx8mm.rst b/doc/board/kontron/sl-mx8mm.rst new file mode 100644 index 0000000000..74ff228f20 --- /dev/null +++ b/doc/board/kontron/sl-mx8mm.rst @@ -0,0 +1,85 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Kontron Electronics SL i.MX8MM SoM +================================== + +The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module +with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC. + +The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0, +HDMI/LVDS, SD card, CAN, RS485, RS232 and much more. + +Quick Start +----------- + +- Get and Build the Trusted Firmware-A (TF-A) +- Get the DDR firmware +- Build U-Boot +- Boot + +Get and Build the Trusted Firmware-A (TF-A) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Note: builddir is U-Boot build directory (source directory for in-tree builds) + +There are two sources for the TF-A. Mainline and NXP. Get the one you prefer +(support and features might differ). + +**NXP's imx-atf** + +1. Get TF-A from: https://source.codeaurora.org/external/imx/imx-atf, branch: imx_5.4.70_2.3.0 +2. Apply the patch to select the correct UART for the console, otherwise the TF-A will lock up during boot. +3. Build + + .. code-block:: bash + + $ make PLAT=imx8mm bl31 + $ cp build/imx8mm/release/bl31.bin $(builddir) + +**Mainline TF-A** + +1. Get TF-A from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/, tag: v2.4 +2. Build + + .. code-block:: bash + + $ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- IMX_BOOT_UART_BASE="0x30880000" bl31 + $ cp build/imx8mm/release/bl31.bin $(builddir) + +Get the DDR firmware +^^^^^^^^^^^^^^^^^^^^ + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin + $ chmod +x firmware-imx-8.9.bin + $ ./firmware-imx-8.9.bin + $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir) + +Build U-Boot +^^^^^^^^^^^^ + +.. code-block:: bash + + $ make kontron-sl-mx8mm_defconfig + $ export ATF_LOAD_ADDR=0x920000 + $ make + +Burn the flash.bin to SD card at an offset of 33 KiB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 conv=notrunc + +Boot +^^^^ + +Put the SD card in the slot on the board and apply power. + +Further Information +------------------- + +The bootloader configuration is setup to be used with kernel FIT images. Legacy +images might not be working out of the box. + +Please see https://docs.kontron-electronics.de for further vendor documentation. diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h new file mode 100644 index 0000000000..4909b3679d --- /dev/null +++ b/include/configs/kontron-sl-mx8mm.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Kontron Electronics GmbH + * + * Configuration settings for the Kontron SL/BL i.MX8M-Mini boards and modules (N81xx). + */ +#ifndef __KONTRON_MX8MM_CONFIG_H +#define __KONTRON_MX8MM_CONFIG_H + +#include +#include + +#ifdef CONFIG_SPL_BUILD +#include +#endif + +/* RAM */ +#define PHYS_SDRAM DDR_CSD1_BASE_ADDR +#define PHYS_SDRAM_SIZE (SZ_4G) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 + +#define CONFIG_SYS_MALLOC_LEN SZ_64M +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Board and environment settings */ +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_HOSTNAME "kontron-mx8mm" + +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) +#include +/* Do not try to probe USB net adapters for net boot */ +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START +#else +#define BOOTENV +#endif + +#define CONFIG_LOADADDR 0x40480000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) +#define CONFIG_FSL_USDHC + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x91fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +#endif + +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x44000000\0" \ + "ramdisk_addr_r=0x46400000\0" \ + "pxefile_addr_r=0x46000000\0" \ + "scriptaddr=0x46000000\0" \ + "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \ + "bootdelay=3\0" \ + "hostname=" CONFIG_HOSTNAME "\0" \ + BOOTENV + +#endif /* __KONTRON_MX8MM_CONFIG_H */ From c7b871111b59a6840f617ae0003b8f66b4f7cf37 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 16 Aug 2021 11:48:41 +0800 Subject: [PATCH 41/60] tools: imx8mimage: not abort when mmap fail When creating flash.bin, the hdmi firmware might not be copied to U-Boot source tree. Then mkimage will fail. However we are switching to binman, binman will show the message if the file not there, and create empty file per i.MX8MQ binman node. So we not fail mkimage here othersize CI will fail if hdmi firmware not copied here. Signed-off-by: Peng Fan --- tools/imx8mimage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index 11e40ccd94..4eed683396 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -271,7 +271,7 @@ static void copy_file(int ifd, const char *datafile, int pad, int offset, if (ptr == MAP_FAILED) { fprintf(stderr, "Can't read %s: %s\n", datafile, strerror(errno)); - exit(EXIT_FAILURE); + goto err_mmap; } size = sbuf.st_size - datafile_offset; @@ -311,6 +311,7 @@ static void copy_file(int ifd, const char *datafile, int pad, int offset, } munmap((void *)ptr, sbuf.st_size); +err_mmap: close(dfd); } From 68de913c12c4d091f51009ad6f179fab825d3d82 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 16 Aug 2021 11:48:45 +0800 Subject: [PATCH 42/60] imx: makefile: drop the use of imx8mimage.sh After switch to use binman, no need to use the bash script to check file exsiting or not. And there is bug that the script will be executed everytime Makefile is used which is confusing people. Signed-off-by: Peng Fan Tested-by: Frieder Schrempf --- arch/arm/mach-imx/Makefile | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 63e28c635e..bfff79f88c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -114,8 +114,7 @@ endif DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) else ifeq ($(CONFIG_ARCH_IMX8M), y) IMAGE_TYPE := imx8mimage -IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh -DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi) +DEPFILE_EXISTS := 0 else IMAGE_TYPE := imximage DEPFILE_EXISTS := 0 @@ -150,16 +149,18 @@ endif ifdef CONFIG_ARM64 ifeq ($(CONFIG_ARCH_IMX8M), y) -SPL: + +SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) flash.bin: MKIMAGEOUTPUT = flash.log +spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE + $(Q)mkdir -p $(dir $@) + $(call if_changed_dep,cpp_cfg) + spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE -ifeq ($(DEPFILE_EXISTS),0) - $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1 -endif flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE $(call if_changed,mkimage) From 84482e4f4e9100cebd069fb59f44eb92e0eeac83 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 24 Aug 2021 07:58:46 -0300 Subject: [PATCH 43/60] smegw01: Pass 'mmcpart' to the kernel command line When using SWUpdate, it is necessary to toggle between partitions. Use the 'mmcpart' environment variable to accomplish that. Signed-off-by: Fabio Estevam --- include/configs/smegw01.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index cf80801bd8..55ca801985 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -26,9 +26,8 @@ "bootm_size=0x10000000\0" \ "mmcdev=0\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ + "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ From 75c337cf2b44181056d0d0cbb012bc9a2a922196 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 24 Aug 2021 12:03:59 -0700 Subject: [PATCH 44/60] arm64: dts: imx8mm-venice-gw700x: use imx8mm-venice-u-boot.dtsi Use the common imx8mm-venice-u-boot.dtsi (dtb for the 'DEFAULT_DEVICE_TREE) so that it inherits things like binman. Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi | 62 +++---------------- 1 file changed, 9 insertions(+), 53 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi index 1a15d6a2ad..7670243851 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi @@ -3,59 +3,7 @@ * Copyright 2021 Gateworks Corporation */ -#include "imx8mm-u-boot.dtsi" - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&i2c2 { - u-boot,dm-spl; -}; - -&pinctrl_i2c2 { - u-boot,dm-spl; -}; +#include "imx8mm-venice-u-boot.dtsi" &fec1 { phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; @@ -63,6 +11,10 @@ phy-reset-post-delay = <1>; }; +&pinctrl_fec1 { + u-boot,dm-spl; +}; + &{/soc@0/bus@30800000/i2c@30a20000/pmic@69} { u-boot,dm-spl; }; @@ -70,3 +22,7 @@ &{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} { u-boot,dm-spl; }; + +&pinctrl_pmic { + u-boot,dm-spl; +}; From 129c0c57b50ed193d40912ad8e5e6d66c06e787c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 24 Aug 2021 12:04:00 -0700 Subject: [PATCH 45/60] arm64: dts: imx8mm-venice-gw7901: use imx8mm-venice-u-boot.dtsi Use the common imx8mm-venice-u-boot.dtsi (dtb for the 'DEFAULT_DEVICE_TREE) so that it inherits things like binman. Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi | 66 ++----------------- 1 file changed, 5 insertions(+), 61 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi index a5adf27649..a801ee1deb 100644 --- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi @@ -3,67 +3,7 @@ * Copyright 2020 Gateworks Corporation */ -#include "imx8mm-u-boot.dtsi" - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&usdhc2 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&i2c2 { - u-boot,dm-spl; -}; - -&pinctrl_i2c2 { - u-boot,dm-spl; -}; +#include "imx8mm-venice-u-boot.dtsi" &fec1 { phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; @@ -71,6 +11,10 @@ phy-reset-post-delay = <1>; }; +&pinctrl_fec1 { + u-boot,dm-spl; +}; + &{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} { u-boot,dm-spl; }; From a31de244737e0005e1363fc53f7c4163c9fbc0e4 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 24 Aug 2021 12:04:01 -0700 Subject: [PATCH 46/60] arm64: dts: imx8mm-venice-gw7902: use imx8mm-venice-u-boot.dtsi Use the common imx8mm-venice-u-boot.dtsi (dtb for the 'DEFAULT_DEVICE_TREE) so that it inherits things like binman. Signed-off-by: Tim Harvey --- arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi | 54 +------------------ 1 file changed, 1 insertion(+), 53 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index 361ddaa78f..d0e5d6c5b6 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -3,59 +3,7 @@ * Copyright 2021 Gateworks Corporation */ -#include "imx8mm-u-boot.dtsi" - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart2 { - u-boot,dm-spl; -}; - -&pinctrl_uart2 { - u-boot,dm-spl; -}; - -&usdhc3 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc3 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&i2c2 { - u-boot,dm-spl; -}; - -&pinctrl_i2c2 { - u-boot,dm-spl; -}; +#include "imx8mm-venice-u-boot.dtsi" &fec1 { phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; From c1412cbb17b2f6cd6c2301d7102346bec3a260d6 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 8 Sep 2021 21:56:42 +0300 Subject: [PATCH 47/60] mmc: fsl_esdhc_imx: initialize data for imx7ulp Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only. Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Ricardo Salveti Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Jaehoon Chung Reviewed-by: Igor Opaniuk --- drivers/mmc/fsl_esdhc_imx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 7c8d82afea..2ee53c7106 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1707,6 +1707,11 @@ static struct esdhc_soc_data usdhc_imx7d_data = { | ESDHC_FLAG_HS400, }; +static struct esdhc_soc_data usdhc_imx7ulp_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, +}; + static struct esdhc_soc_data usdhc_imx8qm_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | @@ -1721,7 +1726,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, - { .compatible = "fsl,imx7ulp-usdhc", }, + { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,}, { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, From fa0223a75946ad3aec2596dac34d88f2dcca7baa Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Wed, 8 Sep 2021 21:56:43 +0300 Subject: [PATCH 48/60] mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP Import HS400 support for iMX7ULP B0 from the Linux kernel: 2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP") According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register. USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave. i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay. Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Jaehoon Chung Reviewed-by: Igor Opaniuk --- drivers/mmc/fsl_esdhc_imx.c | 10 +++++++--- include/fsl_esdhc_imx.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 2ee53c7106..4c06361bee 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -727,17 +727,20 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); + /* clear the reset bit on strobe dll before any setting */ + esdhc_write32(®s->strobe_dllctrl, 0); /* * enable strobe dll ctrl and adjust the delay target * for the uSDHC loopback read clock */ val = ESDHC_STROBE_DLL_CTRL_ENABLE | + ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | (priv->strobe_dll_delay_target << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); esdhc_write32(®s->strobe_dllctrl, val); - /* wait 1us to make sure strobe dll status register stable */ - mdelay(1); + /* wait 5us to make sure strobe dll status register stable */ + mdelay(5); val = esdhc_read32(®s->strobe_dllstat); if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) pr_warn("HS400 strobe DLL status REF not lock!\n"); @@ -1709,7 +1712,8 @@ static struct esdhc_soc_data usdhc_imx7d_data = { static struct esdhc_soc_data usdhc_imx7ulp_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING - | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_HS400, }; static struct esdhc_soc_data usdhc_imx8qm_data = { diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77..12e9163382 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -194,6 +194,7 @@ #define ESDHC_STROBE_DLL_CTRL_RESET BIT(1) #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 +#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) #define ESDHC_STROBE_DLL_STATUS 0x74 #define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1) From 1194d1711781fe30bf664c1bf2d559ffa76ccc7e Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 31 Aug 2021 11:46:05 +0200 Subject: [PATCH 49/60] colibri-imx6: use dynamic DDR calibration Enable dynamic DDR calibration to have a reliable behavior on edge temperatures conditions. Signed-off-by: Max Krummenacher Signed-off-by: Francesco Dolcini --- board/toradex/colibri_imx6/colibri_imx6.c | 22 ++++++++++++++++++++++ configs/colibri_imx6_defconfig | 1 + 2 files changed, 23 insertions(+) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 3b55f6c938..38ff637054 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -997,9 +997,28 @@ static void ddr_init(int *table, int size) writel(table[2 * i + 1], table[2 * i]); } +/* Perform DDR DRAM calibration */ +static void spl_dram_perform_cal(u8 dsize) +{ +#ifdef CONFIG_MX6_DDRCAL + int err; + struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = dsize, + }; + + err = mmdc_do_write_level_calibration(&ddr_sysinfo); + if (err) + printf("error %d from write level calibration\n", err); + err = mmdc_do_dqs_calibration(&ddr_sysinfo); + if (err) + printf("error %d from dqs calibration\n", err); +#endif +} + static void spl_dram_init(void) { int minc, maxc; + u8 dsize = 2; switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_COMMERCIAL: @@ -1009,6 +1028,7 @@ static void spl_dram_init(void) ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); + dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; @@ -1020,11 +1040,13 @@ static void spl_dram_init(void) ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } else { puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); + dsize = 1; ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); } break; }; udelay(100); + spl_dram_perform_cal(dsize); } static iomux_v3_cfg_t const gpio_reset_pad[] = { diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 62a207f554..e9c11d7940 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6DL=y +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_COLIBRI_IMX6=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y From a591e75fbc16d4b4dd26758fc6d3bdb6bd6551cb Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 31 Aug 2021 11:46:06 +0200 Subject: [PATCH 50/60] apalis-imx6: use dynamic DDR calibration Enable dynamic DDR calibration to have a reliable behavior on edge temperatures conditions. Signed-off-by: Max Krummenacher Signed-off-by: Francesco Dolcini --- board/toradex/apalis_imx6/apalis_imx6.c | 19 +++++++++++++++++++ configs/apalis_imx6_defconfig | 1 + 2 files changed, 20 insertions(+) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index f4cd28d49f..25a4cd9f38 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1076,6 +1076,24 @@ static void ddr_init(int *table, int size) writel(table[2 * i + 1], table[2 * i]); } +/* Perform DDR DRAM calibration */ +static void spl_dram_perform_cal(void) +{ +#ifdef CONFIG_MX6_DDRCAL + int err; + struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 2, + }; + + err = mmdc_do_write_level_calibration(&ddr_sysinfo); + if (err) + printf("error %d from write level calibration\n", err); + err = mmdc_do_dqs_calibration(&ddr_sysinfo); + if (err) + printf("error %d from dqs calibration\n", err); +#endif +} + static void spl_dram_init(void) { int minc, maxc; @@ -1094,6 +1112,7 @@ static void spl_dram_init(void) break; }; udelay(100); + spl_dram_perform_cal(); } void board_init_f(ulong dummy) diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 52f2539f11..329f38d1e4 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_MX6Q=y +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_APALIS_IMX6=y CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y From 04f423e41d0f109c531c9aa5116a0b71e2b35399 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 24 Aug 2021 07:58:47 -0300 Subject: [PATCH 51/60] smegw01: Add redundant environment support Add redundant environment support as it is required by SWUpdate. While at it, place the CONFIG_ENV_OFFSET at 0x100000 to allow more headroom. Signed-off-by: Fabio Estevam --- configs/smegw01_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 7a779f3429..0475dc9760 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -4,11 +4,12 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0x100000 CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01" CONFIG_TARGET_SMEGW01=y +CONFIG_ENV_OFFSET_REDUND=0x110000 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y @@ -35,6 +36,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y From 9d8f87f0cd8a81e04fa61f613fd6bf54f4c123a2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 24 Aug 2021 07:58:48 -0300 Subject: [PATCH 52/60] smegw01: Select IMX_HAB Select IMX_HAB to allow secure boot. Signed-off-by: Fabio Estevam --- configs/smegw01_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 0475dc9760..1469c4618c 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -14,6 +14,7 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_IMX_HAB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y From 4d98af69965aea4060c0352fe2c0e6fdf66fe662 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Thu, 26 Aug 2021 14:04:24 +0300 Subject: [PATCH 53/60] board: ea: mx7ulp_com: move setting CONFIG_BOOTCOMMAND to defconfig Move setting CONFIG_BOOTCOMMAND to the mx7ulp_com_defconfig file. It also allows replacing the default CONFIG_BOOTCOMMAND without code modification. Signed-off-by: Ricardo Salveti Signed-off-by: Oleksandr Suvorov Reviewed-by: Fabio Estevam Reviewed-by: Tom Rini --- configs/mx7ulp_com_defconfig | 2 ++ include/configs/mx7ulp_com.h | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig index 6e6b821d90..bd3f52dd20 100644 --- a/configs/mx7ulp_com_defconfig +++ b/configs/mx7ulp_com_defconfig @@ -9,6 +9,8 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com" CONFIG_LDO_ENABLED_MODE=y CONFIG_TARGET_MX7ULP_COM=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi" CONFIG_SYS_LOAD_ADDR=0x60800000 CONFIG_DEFAULT_FDT_FILE="imx7ulp-com" CONFIG_BOARD_EARLY_INIT_F=y diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 48172de1d0..58d48edac4 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -60,11 +60,6 @@ "bootz ${loadaddr} - ${fdt_addr}; " \ "fi;\0" \ -#define CONFIG_BOOTCOMMAND \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K From 92f671899595e08a9698f1bc80aa20a6a16a7f6a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Sep 2021 00:39:58 +0200 Subject: [PATCH 54/60] ARM: imx: mx5: Enable BMODE command on MX53 Menlo board The board can do primary/secondary boot switching, enable the bmode command. Signed-off-by: Marek Vasut Cc: Stefano Babic --- board/menlo/m53menlo/m53menlo.c | 5 +++++ configs/m53menlo_defconfig | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 2b331b32df..9545e633a3 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -334,6 +335,10 @@ int splash_screen_prepare(void) int board_late_init(void) { +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(NULL); +#endif + #if defined(CONFIG_VIDEO_IPUV3) struct udevice *dev; int xpos, ypos, ret; diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 5500d8eaf0..5903ddd13e 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -22,7 +22,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x180000 -# CONFIG_CMD_BMODE is not set CONFIG_SYS_LOAD_ADDR=0x70800000 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y From 521418daee7a1a78503d763c756df424b8fde821 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Sep 2021 00:39:59 +0200 Subject: [PATCH 55/60] ARM: imx: mx5: Enable Thumb2 build on MX53 Menlo board Build U-Boot in Thumb2 mode for M53Menlo board, this makes better use of the CPU since the instruction density is higher. Signed-off-by: Marek Vasut Cc: Stefano Babic --- configs/m53menlo_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 5903ddd13e..2c065c67ff 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX5=y CONFIG_SYS_TEXT_BASE=0x71000000 CONFIG_SPL_GPIO=y From abc6eee0e76f5418f64f8a95878ac2bd6d2b2e69 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 12 Sep 2021 00:40:00 +0200 Subject: [PATCH 56/60] ARM: imx: mx5: Add altbootcmd and resets to M53Menlo Bulletproof the default boot command with reset statements in case any command in the chain would fail. In case a failure were to happen, the board will reset, increment boot counter and retry the procedure. In case the failures persist and the boot counter reaches the bootlimit, U-Boot starts altbootcmd instead of the default bootcmd boot command. The altbootcmd swaps the default boot partition for the other boot partition, which is an identical copy or an older copy, and tries booting from that one instead. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m53menlo.h | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 5dd5ddac17..375a7588dc 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -161,6 +161,13 @@ "splashfile=boot/usplash.bmp.gz\0" \ "splashimage=0x88000000\0" \ "splashpos=m,m\0" \ + "altbootcmd=" \ + "if test ${mmcpart} -eq 1 ; then " \ + "setenv mmcpart 2 ; " \ + "else " \ + "setenv mmcpart 1 ; " \ + "fi ; " \ + "boot\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "addcons=" \ @@ -175,14 +182,14 @@ "setenv bootargs ${bootargs} ${miscargs}\0" \ "addargs=run addcons addmisc addmtd\0" \ "mmcload=" \ - "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \ - "${kernel_addr_r} ${bootfile}\0" \ + "mmc rescan || reset ; load mmc ${mmcdev}:${mmcpart} " \ + "${kernel_addr_r} ${bootfile} || reset\0" \ "miscargs=nohlt panic=1\0" \ "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \ "rootwait\0" \ "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ + "run mmcload mmcargs addargs || reset ; " \ + "bootm ${kernel_addr_r} ; reset\0" \ "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ "net_nfs=" \ "run netload nfsargs addip addargs ; " \ From bafdeb45462683692e0ae217d4683b8062c59608 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 19 Oct 2021 21:43:23 -0600 Subject: [PATCH 57/60] buildman: Write output even on fatal error At present buildman does not write any output (to the 'out' and 'err) files if the build terminates with a fatal error. This is to avoid adding lots of spam to the logs. However there are times when this is actually useful, such as when the build fails for an obscure reason such as a Kconfig loop. Update the logic to always write the output, so that the user gets a clue as to what is happening. Signed-off-by: Simon Glass --- tools/buildman/builderthread.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 48128cf673..3e450e4067 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -300,16 +300,12 @@ class BuilderThread(threading.Thread): work_in_output: Use the output directory as the work directory and don't write to a separate output directory. """ - # Fatal error - if result.return_code < 0: - return - # If we think this might have been aborted with Ctrl-C, record the # failure but not that we are 'done' with this board. A retry may fix # it. - maybe_aborted = result.stderr and 'No child processes' in result.stderr + maybe_aborted = result.stderr and 'No child processes' in result.stderr - if result.already_done: + if result.return_code >= 0 and result.already_done: return # Write the output and stderr @@ -332,6 +328,10 @@ class BuilderThread(threading.Thread): elif os.path.exists(errfile): os.remove(errfile) + # Fatal error + if result.return_code < 0: + return + if result.toolchain: # Write the build result and toolchain information. done_file = self.builder.GetDoneFile(result.commit_upto, From 7bf83a5d7be036969807c0f44ff75d211e039a02 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 19 Oct 2021 21:43:24 -0600 Subject: [PATCH 58/60] buildman: Detect Kconfig loops Hex and int Kconfig options are supposed to have defaults. This is so we can configure U-Boot without having to enter particular values for the items that don't have specific values in the board's defconfig file. If this rule is not followed, then introducing a new Kconfig can produce a loop like this: Break things (BREAK_ME) [] (NEW) Error in reading or end of file. Break things (BREAK_ME) [] (NEW) Error in reading or end of file. The continues forever since buildman passes /dev/null to 'conf', and the build system just tries again. Eventually there is so much output that buildman runs out of memory. We can detect this situation by looking for a symbol (like 'BREAK_ME') which has no default (the '[]' above) and is marked as new. If this appears multiple times in the output, we know something is wrong. Add a filter function for the output which detects this situation. Allow it to return True to terminate the process. Implement this termination in cros_subprocess. With this we get a nice message: buildman --board sandbox -T0 Building current source for 1 boards (0 threads, 32 jobs per thread) sandbox: w+ sandbox +.config:66:warning: symbol value '' invalid for BREAK_ME + +Error in reading or end of file. +make[3]: *** [scripts/kconfig/Makefile:75: syncconfig] Terminated +make[2]: *** [Makefile:569: syncconfig] Terminated +make: *** [Makefile:177: sub-make] Terminated +(** did you define an int/hex Kconfig with no default? **) Signed-off-by: Simon Glass --- tools/buildman/builder.py | 43 ++++++++++++++++++++++++++++++++- tools/patman/command.py | 7 ++++-- tools/patman/cros_subprocess.py | 10 ++++++-- 3 files changed, 55 insertions(+), 5 deletions(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index ce852eb03a..122f0d1406 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -24,6 +24,17 @@ from patman import gitutil from patman import terminal from patman.terminal import Print +# This indicates an new int or hex Kconfig property with no default +# It hangs the build since the 'conf' tool cannot proceed without valid input. +# +# We get a repeat sequence of something like this: +# >> +# Break things (BREAK_ME) [] (NEW) +# Error in reading or end of file. +# << +# which indicates that BREAK_ME has an empty default +RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)') + """ Theory of Operation @@ -200,6 +211,8 @@ class Builder: _working_dir: Base working directory containing all threads _single_builder: BuilderThread object for the singer builder, if threading is not being used + _terminated: Thread was terminated due to an error + _restarting_config: True if 'Restart config' is detected in output """ class Outcome: """Records a build outcome for a single make invocation @@ -304,6 +317,8 @@ class Builder: self.work_in_output = work_in_output if not self.squash_config_y: self.config_filenames += EXTRA_CONFIG_FILENAMES + self._terminated = False + self._restarting_config = False self.warnings_as_errors = warnings_as_errors self.col = terminal.Color() @@ -429,9 +444,35 @@ class Builder: args: Arguments to pass to make kwargs: Arguments to pass to command.RunPipe() """ + + def check_output(stream, data): + if b'Restart config' in data: + self._restarting_config = True + + # If we see 'Restart config' following by multiple errors + if self._restarting_config: + m = RE_NO_DEFAULT.findall(data) + + # Number of occurences of each Kconfig item + multiple = [m.count(val) for val in set(m)] + + # If any of them occur more than once, we have a loop + if [val for val in multiple if val > 1]: + self._terminated = True + return True + return False + + self._restarting_config = False + self._terminated = False cmd = [self.gnu_make] + list(args) result = command.RunPipe([cmd], capture=True, capture_stderr=True, - cwd=cwd, raise_on_error=False, infile='/dev/null', **kwargs) + cwd=cwd, raise_on_error=False, infile='/dev/null', + output_func=check_output, **kwargs) + + if self._terminated: + # Try to be helpful + result.stderr += '(** did you define an int/hex Kconfig with no default? **)' + if self.verbose_build: result.stdout = '%s\n' % (' '.join(cmd)) + result.stdout result.combined = '%s\n' % (' '.join(cmd)) + result.combined diff --git a/tools/patman/command.py b/tools/patman/command.py index bf8ea6c8c3..d54b1e0efc 100644 --- a/tools/patman/command.py +++ b/tools/patman/command.py @@ -49,7 +49,8 @@ test_result = None def RunPipe(pipe_list, infile=None, outfile=None, capture=False, capture_stderr=False, oneline=False, - raise_on_error=True, cwd=None, binary=False, **kwargs): + raise_on_error=True, cwd=None, binary=False, + output_func=None, **kwargs): """ Perform a command pipeline, with optional input/output filenames. @@ -63,6 +64,8 @@ def RunPipe(pipe_list, infile=None, outfile=None, capture: True to capture output capture_stderr: True to capture stderr oneline: True to strip newline chars from output + output_func: Output function to call with each output fragment + (if it returns True the function terminates) kwargs: Additional keyword arguments to cros_subprocess.Popen() Returns: CommandResult object @@ -105,7 +108,7 @@ def RunPipe(pipe_list, infile=None, outfile=None, if capture: result.stdout, result.stderr, result.combined = ( - last_pipe.CommunicateFilter(None)) + last_pipe.CommunicateFilter(output_func)) if result.stdout and oneline: result.output = result.stdout.rstrip(b'\r\n') result.return_code = last_pipe.wait() diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py index fdd5138685..88a4693fef 100644 --- a/tools/patman/cros_subprocess.py +++ b/tools/patman/cros_subprocess.py @@ -128,6 +128,9 @@ class Popen(subprocess.Popen): sys.stdout or sys.stderr. data: a string containing the data + Returns: + True to terminate the process + Note: The data read is buffered in memory, so do not use this method if the data size is large or unlimited. @@ -175,6 +178,7 @@ class Popen(subprocess.Popen): stderr = bytearray() combined = bytearray() + stop_now = False input_offset = 0 while read_set or write_set: try: @@ -212,7 +216,7 @@ class Popen(subprocess.Popen): stdout += data combined += data if output: - output(sys.stdout, data) + stop_now = output(sys.stdout, data) if self.stderr in rlist: data = b'' # We will get an error on read if the pty is closed @@ -227,7 +231,9 @@ class Popen(subprocess.Popen): stderr += data combined += data if output: - output(sys.stderr, data) + stop_now = output(sys.stderr, data) + if stop_now: + self.terminate() # All data exchanged. Translate lists into strings. stdout = self.ConvertData(stdout) From 0105bda050c89b70d632e2efc76f83b73f0e421a Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Oct 2021 11:55:25 +0200 Subject: [PATCH 59/60] kontron-sl-mx8mm: fix missing configs and deadlock in CI Even if board can be successfuly built, CI goes in deadlock (see thread on https://www.mail-archive.com/u-boot@lists.denx.de/msg419663.html). This is caused by SYS_CONFIG set in header file and because defconfig for the board is out of sync with Kconfig. As result, buildman goes on to read from stdin until an OOM is reached. Signed-off-by: Stefano Babic CC: Frieder Schrempf --- configs/kontron-sl-mx8mm_defconfig | 4 +++- include/configs/kontron-sl-mx8mm.h | 3 --- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 06c57b7555..02897818d9 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x1f0000 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s" @@ -17,6 +18,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y @@ -25,7 +27,7 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kontron/sl-mx8mm/imximage.cfg" +CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg" CONFIG_BOARD_TYPES=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 4909b3679d..0d9ab3b755 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_MALLOC_LEN SZ_64M #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_INIT_SP_OFFSET \ @@ -55,8 +54,6 @@ #define BOOTENV #endif -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SPL_MAX_SIZE (148 * SZ_1K) #define CONFIG_FSL_USDHC From f0045799c6957e374cc12a6146ac60881cd827d6 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 20 Oct 2021 12:13:44 +0200 Subject: [PATCH 60/60] imx8mm-cl-iot-gate-optee: align config with Kconfig Due to missing configs, CI goes in deadlock until an OOM is tracked. Add CONFIG_SYS_LOAD_ADDR and replace CONFIG_SYS_EXTRA_OPTIONS with CONFIG_IMX_CONFIG. Signed-off-by: Stefano Babic CC: Ying-Chun Liu (PaulLiu)" CC: Fabio Estevam --- configs/imx8mm-cl-iot-gate-optee_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index d918779960..d987328922 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -21,13 +21,14 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" +CONFIG_IMX_CONFIG="board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y