From 70ae54bd2579568372e79f69417e5cb568b24b6f Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 16 Mar 2022 21:21:18 +0100 Subject: [PATCH 1/5] cmd: sbi: add Performance Monitoring Unit Extension Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification has added the Performance Monitoring Unit Extension. The sbi command should be able to detect it. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- arch/riscv/include/asm/sbi.h | 1 + cmd/riscv/sbi.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index bfcd204953..76453121ea 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -27,6 +27,7 @@ enum sbi_ext_id { SBI_EXT_RFENCE = 0x52464E43, SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, + SBI_EXT_PMU = 0x504D55, }; enum sbi_ext_base_fid { diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index c4a9c840f3..8349123925 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -44,6 +44,7 @@ static struct sbi_ext extensions[] = { { SBI_EXT_RFENCE, "RFENCE Extension" }, { SBI_EXT_HSM, "Hart State Management Extension" }, { SBI_EXT_SRST, "System Reset Extension" }, + { SBI_EXT_PMU, "Performance Monitoring Unit Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, From ca7e93fa9f6c417a2d260440ff4c0aaded259989 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 17 Mar 2022 07:36:14 +0100 Subject: [PATCH 2/5] riscv: provide missing base extension functions Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson --- arch/riscv/include/asm/sbi.h | 3 ++ arch/riscv/lib/sbi.c | 65 ++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 76453121ea..81fcfe0b36 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -155,6 +155,9 @@ long sbi_get_spec_version(void); int sbi_get_impl_id(void); int sbi_get_impl_version(long *version); int sbi_probe_extension(int ext); +int sbi_get_mvendorid(long *mvendorid); +int sbi_get_marchid(long *marchid); +int sbi_get_mimpid(long *mimpid); void sbi_srst_reset(unsigned long type, unsigned long reason); #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index d427d1b29e..8724e3a460 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -127,6 +127,71 @@ int sbi_probe_extension(int extid) return -ENOTSUPP; } +/** + * sbi_get_mvendorid() - get machine vendor ID + * + * @mimpid: on return machine vendor ID + * Return: 0 on success + */ +int sbi_get_mvendorid(long *mvendorid) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, + 0, 0, 0, 0, 0, 0); + if (ret.error) + return -ENOTSUPP; + + if (mvendorid) + *mvendorid = ret.value; + + return 0; +} + +/** + * sbi_get_marchid() - get machine architecture ID + * + * @mimpid: on return machine architecture ID + * Return: 0 on success + */ +int sbi_get_marchid(long *marchid) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, + 0, 0, 0, 0, 0, 0); + + if (ret.error) + return -ENOTSUPP; + + if (marchid) + *marchid = ret.value; + + return 0; +} + +/** + * sbi_get_mimpid() - get machine implementation ID + * + * @mimpid: on return machine implementation ID + * Return: 0 on success + */ +int sbi_get_mimpid(long *mimpid) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, + 0, 0, 0, 0, 0, 0); + + if (ret.error) + return -ENOTSUPP; + + if (mimpid) + *mimpid = ret.value; + + return 0; +} + /** * sbi_srst_reset() - invoke system reset extension * From cfb31e0b9e23809fc3733b733b20b3443e15c704 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 17 Mar 2022 07:36:15 +0100 Subject: [PATCH 3/5] cmd/sbi: add missing SBI information Let the sbi command display: * machine vendor ID * machine architecture ID * machine implementation ID With this patch the output for the HiFive Unmatched looks like => sbi SBI 0.3 OpenSBI 0.9 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 20181004 Extensions: sbi_set_timer sbi_console_putchar sbi_console_getchar sbi_clear_ipi sbi_send_ipi sbi_remote_fence_i sbi_remote_sfence_vma sbi_remote_sfence_vma_asid sbi_shutdown SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson --- cmd/riscv/sbi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 8349123925..8fc8ab0ac5 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -52,6 +52,7 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, { int i, impl_id; long ret; + long mvendorid, marchid, mimpid; ret = sbi_get_spec_version(); if (ret >= 0) @@ -77,7 +78,17 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, if (i == ARRAY_SIZE(implementations)) printf("Unknown implementation ID %ld", ret); } - printf("\nExtensions:\n"); + printf("\nMachine:\n"); + ret = sbi_get_mvendorid(&mvendorid); + if (!ret) + printf(" Vendor ID %lx\n", mvendorid); + ret = sbi_get_marchid(&marchid); + if (!ret) + printf(" Architecture ID %lx\n", marchid); + ret = sbi_get_mimpid(&mimpid); + if (!ret) + printf(" Implementation ID %lx\n", mimpid); + printf("Extensions:\n"); for (i = 0; i < ARRAY_SIZE(extensions); ++i) { ret = sbi_probe_extension(extensions[i].id); if (ret > 0) From 22e324c6381a7c59b3ae6e6bf860f34e4c7b3fe8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 23 Mar 2022 22:46:43 +0100 Subject: [PATCH 4/5] riscv: enable CONFIG_CMD_SBI for QEMU boards Let CONFIG_TARGET_QEMU_VIRT imply CONFIG_CMD_SBI. The sbi command provides detailed information about the SBI. It is useful to test the discovery of extensions. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 02bf84725b..d8c57e6bb0 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SPL_RAM_DEVICE imply CMD_PCI imply CMD_POWEROFF + imply CMD_SBI imply CMD_SCSI imply CMD_PING imply CMD_EXT2 From 776e8aca0bad2900dc9c12b87dedb732a9f8e39b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 5 Apr 2022 16:47:15 +0200 Subject: [PATCH 5/5] riscv: alloc space exhausted When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message alloc space exhausted 32 is the current maximum number of harts for machine virt in QEMU 7.0. Raise the default for SYS_MALLOC_F_LEN to 16 KiB. Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini Reviewed-by: Rick Chen --- Kconfig | 2 +- arch/riscv/Kconfig | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/Kconfig b/Kconfig index 112745440b..678317e4d3 100644 --- a/Kconfig +++ b/Kconfig @@ -248,7 +248,7 @@ config SYS_MALLOC_F_LEN hex "Size of malloc() pool before relocation" depends on SYS_MALLOC_F default 0x1000 if AM33XX - default 0x4000 if SANDBOX + default 0x4000 if SANDBOX || RISCV default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ba29e70acf..78e964db12 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -195,9 +195,6 @@ config ANDES_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. -config SYS_MALLOC_F_LEN - default 0x1000 - config SMP bool "Symmetric Multi-Processing" depends on SBI_V01 || !RISCV_SMODE