Convert CONFIG_SYS_PCI_64BIT to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_PCI_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2021-12-12 22:12:32 -05:00
parent d06e4b7e25
commit 7856cd5a6d
29 changed files with 14 additions and 33 deletions

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@@ -26,8 +26,6 @@
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
/*
* sysclk for MPC85xx
*

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@@ -19,7 +19,6 @@
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */

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@@ -27,7 +27,6 @@
* assume U-Boot is less than 0.5MB
*/
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/*

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@@ -114,7 +114,6 @@
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
* PCI Windows

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@@ -36,7 +36,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */

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@@ -416,7 +416,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */

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@@ -85,8 +85,6 @@
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_NXP_ESBC

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@@ -414,7 +414,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

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@@ -366,7 +366,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

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@@ -60,7 +60,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/*
* These can be toggled for performance analysis, otherwise use default.

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@@ -44,7 +44,6 @@
/* Access eMMC Boot_1 and Boot_2 partitions */
/* enable 64-bit PCI resources */
#define CONFIG_SYS_PCI_64BIT 1
#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
#define MAX_CPUS "max_cpus=maxcpus=8\0"

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@@ -47,7 +47,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_SDCARD)

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@@ -16,7 +16,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000)
/* PCI CONFIG */
#define CONFIG_SYS_PCI_64BIT 1
#define CONFIG_PCI_SCAN_SHOW
/* SCSI */

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@@ -141,7 +141,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000

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@@ -104,7 +104,6 @@
/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_64BIT
#define CONFIG_PCI_SCAN_SHOW
#endif

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@@ -140,7 +140,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_LBA48

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@@ -13,8 +13,6 @@
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS
/* Needed to fill the ccsrbar pointer */

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@@ -32,8 +32,6 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
/* Environment options */

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@@ -46,7 +46,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
/* #define CONFIG_SYS_PCI_64BIT 1 */
#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
"mtd nor1=u-boot.bin raw 200000 100000;" \

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@@ -198,6 +198,4 @@
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_PCI_64BIT
#endif /* __CONFIG_UNIPHIER_H__ */