Merge branch '2019-07-26-ti-imports'
- Bring in the rest of the J271E platform - Various OMAP3/AM3517, DA850 fixes
This commit is contained in:
@@ -28,6 +28,8 @@
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* Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
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*/
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
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#ifdef CONFIG_USB_MUSB_AM35X
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#ifdef CONFIG_USB_MUSB_HOST
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@@ -22,7 +22,9 @@
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONSOLEDEV "ttyO2"
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONSOLEDEV "ttyS2"
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#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
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#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
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#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
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@@ -18,14 +18,6 @@
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#define CONFIG_USE_SPIFLASH
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#endif
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/*
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* Disable DM_* for SPL build and can be re-enabled after adding
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* DM support in SPL
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*/
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_DM_I2C
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#undef CONFIG_DM_I2C_COMPAT
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#endif
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/*
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* SoC Configuration
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*/
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@@ -268,12 +260,8 @@
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#endif
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/* USB Configs */
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "da850evm"
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#ifndef CONFIG_DIRECT_NOR_BOOT
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/* defines for SPL */
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@@ -26,9 +26,9 @@
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#endif
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#if (CONFIG_CONS_INDEX == 1)
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#define CONSOLEDEV "ttyO0"
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#define CONSOLEDEV "ttyS0"
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#elif (CONFIG_CONS_INDEX == 3)
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#define CONSOLEDEV "ttyO2"
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#define CONSOLEDEV "ttyS2"
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#endif
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#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
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#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
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103
include/configs/j721e_evm.h
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103
include/configs/j721e_evm.h
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@@ -0,0 +1,103 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration header file for K3 J721E EVM
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*
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* Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef __CONFIG_J721E_EVM_H
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#define __CONFIG_J721E_EVM_H
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#include <linux/sizes.h>
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#include <config_distro_bootcmd.h>
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#include <environment/ti/mmc.h>
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#define CONFIG_ENV_SIZE (128 << 10)
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/* DDR Configuration */
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#define CONFIG_SYS_SDRAM_BASE1 0x880000000
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/* SPL Loader Configuration */
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#ifdef CONFIG_TARGET_J721E_A72_EVM
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
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CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x280000
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#else
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/*
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* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
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* possible (to allow the build to go through), as this directly affects
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* our memory footprint. The less we use for BSS the more we have available
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* for everything else.
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*/
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#define CONFIG_SPL_BSS_MAX_SIZE 0xA000
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/*
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* Link BSS to be within SPL in a dedicated region located near the top of
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* the MCU SRAM, this way making it available also before relocation. Note
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* that we are not using the actual top of the MCU SRAM as there is a memory
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* location filled in by the boot ROM that we want to read out without any
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* interference from the C context.
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*/
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#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
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CONFIG_SPL_BSS_MAX_SIZE)
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/* Set the stack right below the SPL BSS section */
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
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/* Configure R5 SPL post-relocation malloc pool in DDR */
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#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000
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#endif
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#ifdef CONFIG_SYS_K3_SPL_ATF
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
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#endif
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#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONFIG_CQSPI_REF_CLK 133333333
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/* U-Boot general configuration */
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#define EXTRA_ENV_J721E_BOARD_SETTINGS \
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"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
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"findfdt=" \
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"setenv fdtfile ${default_device_tree};" \
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"setenv overlay_files ${name_overlays}\0" \
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"loadaddr=0x80080000\0" \
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"fdtaddr=0x82000000\0" \
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"overlayaddr=0x83000000\0" \
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"name_kern=Image\0" \
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"console=ttyS2,115200n8\0" \
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"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
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"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
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/* U-Boot MMC-specific configuration */
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#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
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"boot=mmc\0" \
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"mmcdev=1\0" \
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"bootpart=1:2\0" \
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"bootdir=/boot\0" \
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"rd_spec=-\0" \
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"init_mmc=run args_all args_mmc\0" \
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"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
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"get_overlay_mmc=" \
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"fdt address ${fdtaddr};" \
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"fdt resize 0x100000;" \
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"for overlay in $overlay_files;" \
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"do;" \
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"load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
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"fdt apply ${overlayaddr};" \
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"done;\0" \
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"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
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"${bootdir}/${name_kern}\0"
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/* Incorporate settings into the U-Boot environment */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_MMC_TI_ARGS \
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EXTRA_ENV_J721E_BOARD_SETTINGS \
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EXTRA_ENV_J721E_BOARD_SETTINGS_MMC
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/* Now for the remaining common defines */
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#include <configs/ti_armv7_common.h>
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#endif /* __CONFIG_J721E_EVM_H */
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@@ -30,6 +30,10 @@
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/* I2C */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
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#ifdef CONFIG_USB_EHCI_OMAP
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4
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#endif
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/* Board NAND Info. */
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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@@ -53,7 +53,7 @@
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/* USB Networking options */
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#define CONSOLEDEV "ttyO2"
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#define CONSOLEDEV "ttyS2"
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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@@ -35,4 +35,7 @@
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#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
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#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
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#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
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#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
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#endif
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9
include/dt-bindings/soc/ti,sci_pm_domain.h
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9
include/dt-bindings/soc/ti,sci_pm_domain.h
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@@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
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#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
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#define TI_SCI_PD_EXCLUSIVE 1
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#define TI_SCI_PD_SHARED 0
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#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */
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@@ -10,7 +10,7 @@
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#define __TI_BOOT_H
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#ifndef CONSOLEDEV
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#define CONSOLEDEV "ttyO2"
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#define CONSOLEDEV "ttyS2"
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#endif
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#define VBMETA_PART_SIZE (64 * 1024)
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@@ -105,6 +105,9 @@ struct ti_sci_board_ops {
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* -reset_state: pointer to u32 which will retrieve resets
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* Returns 0 for successful request, else returns
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* corresponding error message.
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* @release_exclusive_devices: Command to release all the exclusive devices
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* attached to this host. This should be used very carefully
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* and only at the end of execution of your software.
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*
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* NOTE: for all these functions, the following parameters are generic in
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* nature:
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@@ -117,7 +120,10 @@ struct ti_sci_board_ops {
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*/
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struct ti_sci_dev_ops {
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int (*get_device)(const struct ti_sci_handle *handle, u32 id);
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int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
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int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
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int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
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u32 id);
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int (*put_device)(const struct ti_sci_handle *handle, u32 id);
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int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
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int (*get_context_loss_count)(const struct ti_sci_handle *handle,
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@@ -134,6 +140,7 @@ struct ti_sci_dev_ops {
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u32 reset_state);
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int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
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u32 *reset_state);
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int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
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};
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/**
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@@ -263,6 +270,8 @@ struct ti_sci_core_ops {
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* @set_proc_boot_ctrl: Setup limited control flags in specific cases.
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* @proc_auth_boot_image:
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* @get_proc_boot_status: Get the state of physical processor
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* @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a
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* response.
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*
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* NOTE: for all these functions, the following parameters are generic in
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* nature:
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@@ -284,6 +293,8 @@ struct ti_sci_proc_ops {
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int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
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u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
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u32 *sts_flags);
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int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
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u8 pid);
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};
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#define TI_SCI_RING_MODE_RING (0)
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@@ -55,23 +55,12 @@ struct udevice;
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*
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* @dev: The device which implements the power domain.
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* @id: The power domain ID within the provider.
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*
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* Currently, the power domain API assumes that a single integer ID is enough
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* to identify and configure any power domain for any power domain provider. If
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* this assumption becomes invalid in the future, the struct could be expanded
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* to either (a) add more fields to allow power domain providers to store
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* additional information, or (b) replace the id field with an opaque pointer,
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* which the provider would dynamically allocate during its .of_xlate op, and
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* process during is .request op. This may require the addition of an extra op
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* to clean up the allocation.
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* @priv: Private data corresponding to each power domain.
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*/
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struct power_domain {
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struct udevice *dev;
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/*
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* Written by of_xlate. We assume a single id is enough for now. In the
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* future, we might add more fields here.
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*/
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unsigned long id;
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void *priv;
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};
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/**
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