mpc83xx: Migrate arbiter config to Kconfig
Migrate the arbiter configuration to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
@@ -33,11 +33,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* Arbiter Setup
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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@@ -67,9 +67,6 @@
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*/
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#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/*
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* Device configurations
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*/
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@@ -39,9 +39,6 @@
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*/
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#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/*
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* Device configurations
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*/
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@@ -31,11 +31,6 @@
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#define CONFIG_HWCONFIG
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/*
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* Arbiter Setup
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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@@ -20,11 +20,6 @@
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*/
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#define CONFIG_SYS_SICRL 0x00000000
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/*
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* System performance
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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#define CONFIG_SYS_SPCR_OPT 1
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@@ -328,8 +328,6 @@
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/*
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* System performance
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
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@@ -383,8 +383,6 @@
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/*
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* System performance
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
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@@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */
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/*
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* System performance
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
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@@ -12,10 +12,6 @@
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*/
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#define CONFIG_E300 1 /* E300 family */
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/* Arbiter Configuration Register */
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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/* System Priority Control Register */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
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@@ -23,10 +23,6 @@
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/* System performance - define the value i.e. CONFIG_SYS_XXX
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*/
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/* Arbiter Configuration Register */
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/* System Priority Control Regsiter */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
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@@ -21,11 +21,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* Arbiter Setup
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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@@ -20,9 +20,6 @@
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#define CONFIG_BOOT_RETRY_MIN 30
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SICRH 0x00000000
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#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
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@@ -40,14 +40,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -25,14 +25,6 @@
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#include "km/keymile-common.h"
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#include "km/km-powerpc.h"
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -45,14 +45,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -45,14 +45,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -52,14 +52,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -45,14 +45,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -44,14 +44,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -36,11 +36,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* Arbiter Setup
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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@@ -21,11 +21,6 @@
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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/*
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* Arbiter Setup
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
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/*
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@@ -42,14 +42,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -45,14 +45,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -45,14 +45,6 @@
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/*
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* Bus Arbitration Configuration Register (ACR)
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
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#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
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#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
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/*
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* DDR Setup
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*/
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@@ -27,9 +27,6 @@
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#define CONFIG_SYS_MEMTEST_START 0x00001000
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#define CONFIG_SYS_MEMTEST_END 0x07000000
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
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/*
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* Device configurations
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*/
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