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Merge branch 'master' of http://www.denx.de/git/u-boot

Browse Source
This commit is contained in:
Jon Loeliger
2006-06-07 08:49:38 -05:00
parent 9f37dc8cab e461a24113
commit 72ed528a94
225 changed files with 75292 additions and 274 deletions
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56
include/asm-arm/arch-ixp/ixp425.h
View File

@@ -73,21 +73,18 @@
* PCI Configuration space
*/
#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000)
#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
/*
* Expansion BUS Configuration registers
*/
#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000)
#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
/*
* Peripheral space
*/
#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000)
#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
/*
@@ -99,7 +96,6 @@
* Q Manager space .. not static mapped
*/
#define IXP425_QMGR_BASE_PHYS (0x60000000)
#define IXP425_QMGR_BASE_VIRT (0xFFFDE000)
#define IXP425_QMGR_REGION_SIZE (0x00004000)
/*
@@ -113,10 +109,8 @@
*/
#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000)
#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT
#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
@@ -130,20 +124,10 @@
#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000)
#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000)
#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000)
#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000)
#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000)
#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000)
#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000)
#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000)
#define IXP425_FLASH_WRITABLE (0x2)
#define IXP425_FLASH_DEFAULT (0xbcd23c40)
#define IXP425_FLASH_WRITE (0xbcd23c42)
#define IXP425_EXP_CS0_OFFSET 0x00
#define IXP425_EXP_CS1_OFFSET 0x04
#define IXP425_EXP_CS2_OFFSET 0x08
@@ -161,7 +145,7 @@
* Expansion Bus Controller registers.
*/
#ifndef __ASSEMBLY__
#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x)))
#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
#else
#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
#endif
@@ -288,7 +272,6 @@
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT
#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
/*
* Peripheral Space Registers
@@ -306,20 +289,6 @@
#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
#define IXP425_UART1_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x0000)
#define IXP425_UART2_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x1000)
#define IXP425_PMU_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x2000)
#define IXP425_INTC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x3000)
#define IXP425_GPIO_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x4000)
#define IXP425_TIMER_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x5000)
#define IXP425_NPEA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x6000)
#define IXP425_NPEB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x7000)
#define IXP425_NPEC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x8000)
#define IXP425_EthA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x9000)
#define IXP425_EthB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xA000)
#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000)
/*
* UART Register Definitions , Offsets only as there are 2 UARTS.
* IXP425_UART1_BASE , IXP425_UART2_BASE.
@@ -341,11 +310,14 @@
#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
#define N_IRQS 32
#define IXP425_TIMER_2_IRQ 11
/*
* Interrupt Controller Register Definitions.
*/
#ifndef __ASSEMBLY__
#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x)))
#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
#else
#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
#endif
@@ -375,7 +347,7 @@
* GPIO Register Definitions.
* [Only perform 32bit reads/writes]
*/
#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x)))
#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
@@ -386,6 +358,16 @@
#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
/*
* Macros to make it easy to access the GPIO registers
*/
#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line))
#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \
(*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3))
/*
* Constants to make it easy to access Timer Control/Status registers
*/
@@ -409,7 +391,9 @@
#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
#endif
#if 0 /* test-only: also defined in npe/include/... */
#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
#endif
#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
@@ -457,12 +441,12 @@
#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
/*
* PCI Control/Status Registers
*/
#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x)))
#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)

52
include/asm-arm/arch-omap/sizes.h Normal file
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@@ -0,0 +1,52 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* DO NOT EDIT!! - this file automatically generated
* from .s file by awk -f s2h.awk
*/
/* Size defintions
* Copyright (C) ARM Limited 1998. All rights reserved.
*/
#ifndef __sizes_h
#define __sizes_h 1
/* handy sizes */
#define SZ_1K 0x00000400
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_512K 0x00080000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000
#define SZ_512M 0x20000000
#define SZ_1G 0x40000000
#define SZ_2G 0x80000000
#endif
/* END */

1
include/asm-arm/mach-types.h
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@@ -736,6 +736,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_LN2410SBC 725
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
#define MACH_TYPE_PDNB3 1002
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type

4
include/asm-arm/u-boot.h
View File

@@ -48,6 +48,10 @@ typedef struct bd_info {
ulong start;
ulong size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
#ifdef CONFIG_HAS_ETH1
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
} bd_t;
#define bi_env_data bi_env->data

2
include/asm-ppc/processor.h
View File

@@ -735,7 +735,9 @@
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892

3
include/commproc.h
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@@ -2,7 +2,7 @@
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* (C) Copyright 2000-2004
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file contains structures and information for the communication
@@ -1412,6 +1412,7 @@ typedef struct scc_enet {
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
defined(CONFIG_VIRTLAB2)|| \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.

2
include/configs/M5271EVB.h
View File

@@ -50,6 +50,8 @@
#undef CONFIG_WATCHDOG /* disable watchdog */
#define CONFIG_BOOTDELAY 5
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/

2
include/configs/MPC8349EMDS.h
View File

@@ -39,7 +39,7 @@
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
#undef CONFIG_PCI
#undef CONFIG_PCI
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define PCI_66M

32
include/configs/ixdp425.h
View File

@@ -33,6 +33,9 @@
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
#define CONFIG_IXDP425 1 /* on an IXDP425 Board */
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
@@ -135,6 +138,8 @@
#define CFG_DRAM_SIZE 0x01000000
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
/*
* Expansion bus settings
@@ -152,19 +157,30 @@
* GPIO settings
*/
/*
* FLASH and environment organization
*/
/*
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_ENV_IS_IN_FLASH 1
/* FIXME */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#endif /* __CONFIG_H */

240
include/configs/ixdpg425.h Normal file
View File

@@ -0,0 +1,240 @@
/*
* (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2003
* Martijn de Gouw, Prodrive B.V., martijn.de.gouw@prodrive.nl
*
* Configuation settings for the IXDPG425 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
#define CONFIG_IXDPG425 1 /* on an IXDPG425 Board */
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/*
* Ethernet
*/
#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 5 /* NPE0 PHY address */
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 4 /* NPE1 PHY address */
#define CONFIG_MII 1 /* MII PHY management */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
/*
* Misc configuration options
*/
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_ELF | \
CFG_CMD_NET | \
CFG_CMD_MII | \
CFG_CMD_PING)
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
/* These are u-boot generic parameters */
#include <cmd_confdefs.h>
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
#define CFG_LOAD_ADDR 0x00010000 /* default load address */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/***************************************************************
* Platform/Board specific defines start here.
***************************************************************/
/*-----------------------------------------------------------------------
* Default configuration (environment varibles...)
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=ixdpg425\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/arm\0" \
"bootfile=/tftpboot/ixdpg425/uImage\0" \
"kernel_addr=50080000\0" \
"ramdisk_addr=50200000\0" \
"load=tftp 100000 /tftpboot/ixdpg425/u-boot.bin\0" \
"update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \
"cp.b 100000 50000000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
#define CFG_DRAM_BASE 0x00000000
#define CFG_DRAM_SIZE 0x01000000
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
/*
* Expansion bus settings
*/
#define CFG_EXP_CS0 0xbcd23c42
/*
* SDRAM settings
*/
#define CFG_SDR_CONFIG 0x18
#define CFG_SDR_MODE_CONFIG 0x1
#define CFG_SDRAM_REFRESH_CNT 0x81a
/*
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* GPIO settings
*/
#define CFG_GPIO_PCI_INTA_N 6
#define CFG_GPIO_PCI_INTB_N 7
#define CFG_GPIO_SWITCH_RESET_N 8
#define CFG_GPIO_SLIC_RESET_N 13
#define CFG_GPIO_PCI_CLK 14
#define CFG_GPIO_EXTBUS_CLK 15
/*
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#endif /* __CONFIG_H */

36
include/configs/omap5912osk.h
View File

@@ -35,6 +35,9 @@
#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/* input clock of PLL */
/* the OMAP5912 OSK has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
@@ -45,11 +48,13 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
@@ -142,27 +147,44 @@
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_FLASH_BASE PHYS_FLASH_1
#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
/*-----------------------------------------------------------------------
* FLASH and environment organization
* FLASH driver setup
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
/* addr of environment */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_ENV_IS_IN_FLASH 1
/* addr of environment */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CFG_ENV_OFFSET 0x20000 /* environment starts here */

412
include/configs/pcs440ep.h Normal file
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@@ -0,0 +1,412 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* pcs440ep.h - configuration for PCS440EP board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000
#define CFG_BOOT_BASE_ADDR 0xf0000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* no external clk used */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define SPD_EEPROM_ADDRESS {0x50, 0x51}
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pcs440ep\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/pcs440ep/uImage\0" \
"kernel_addr=FFF00000\0" \
"ramdisk_addr=FFF00000\0" \
"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 2
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_EXT2 | \
CFG_CMD_FAT | \
CFG_CMD_USB )
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
#define CFG_FLASH FLASH_BASE0_PRELIM
#define CFG_SRAM 0xF1000000
#define CFG_FPGA 0xF2000000
#define CFG_CF1 0xF0000000
#define CFG_CF2 0xF0100000
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
#define CFG_EBC_PB0CR (CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 1 (SRAM) initialization */
#define CFG_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
#define CFG_EBC_PB1CR (CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 2 (FPGA) initialization */
#define CFG_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
#define CFG_EBC_PB2CR (CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 3 (CompactFlash) initialization */
#define CFG_EBC_PB3AP 0x080BD400
#define CFG_EBC_PB3CR (CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 4 (CompactFlash) initialization */
#define CFG_EBC_PB4AP 0x080BD400
#define CFG_EBC_PB4CR (CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

307
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/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Configuation settings for the PDNB3 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
#define CONFIG_PDNB3 1 /* on an PDNB3 board */
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/*
* Ethernet
*/
#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
#define CONFIG_MII 1 /* MII PHY management */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
/*
* Misc configuration options
*/
#define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
#define CFG_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (1 << 20)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_NET | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CFG_CMD_I2C | \
CFG_CMD_ELF | \
CFG_CMD_PING)
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
/* These are u-boot generic parameters */
#include <cmd_confdefs.h>
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
#define CFG_LOAD_ADDR 0x00010000 /* default load address */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/***************************************************************
* Platform/Board specific defines start here.
***************************************************************/
/*-----------------------------------------------------------------------
* Default configuration (environment varibles...)
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pdnb3\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
"mtdparts=${mtdparts}\0" \
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/buildroot\0" \
"bootfile=/tftpboot/netbox/uImage\0" \
"kernel_addr=50080000\0" \
"ramdisk_addr=50200000\0" \
"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
"update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
"cp.b 100000 50000000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"ipaddr=10.0.0.233\0" \
"serverip=10.0.0.152\0" \
"netmask=255.255.0.0\0" \
"ethaddr=c6:6f:13:36:f3:81\0" \
"eth1addr=c6:6f:13:36:f3:82\0" \
"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
"4k@508k(renv)\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CFG_FLASH_BASE 0x50000000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
/*
* Expansion bus settings
*/
#define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */
#define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */
/*
* SDRAM settings
*/
#define CFG_SDR_CONFIG 0x18
#define CFG_SDR_MODE_CONFIG 0x1
#define CFG_SDRAM_REFRESH_CNT 0x81a
/*
* FLASH and environment organization
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* NAND-FLASH stuff
*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
/*
* GPIO settings
*/
/* FPGA program pin configuration */
#define CFG_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
#define CFG_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
#define CFG_GPIO_DATA 14 /* FPGA data pin (cpu output) */
#define CFG_GPIO_INIT 13 /* FPGA init pin (cpu input) */
#define CFG_GPIO_DONE 11 /* FPGA done pin (cpu input) */
/* other GPIO's */
#define CFG_GPIO_RESTORE_INT 0
#define CFG_GPIO_RESTART_INT 1
#define CFG_GPIO_SYS_RUNNING 2
#define CFG_GPIO_PCI_INTA 3
#define CFG_GPIO_PCI_INTB 4
#define CFG_GPIO_I2C_SCL 6
#define CFG_GPIO_I2C_SDA 7
#define CFG_GPIO_FPGA_RESET 9
#define CFG_GPIO_CLK_33M 15
/*
* I2C stuff
*/
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
#define CFG_I2C_SPEED 83000 /* 83 kHz is supposed to work */
#define CFG_I2C_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define PB_SCL (1 << CFG_GPIO_I2C_SCL)
#define PB_SDA (1 << CFG_GPIO_I2C_SDA)
#define I2C_INIT GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SCL)
#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CFG_GPIO_I2C_SDA)
#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CFG_GPIO_I2C_SDA)
#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SDA); \
else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SDA)
#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CFG_GPIO_I2C_SCL); \
else GPIO_OUTPUT_CLEAR(CFG_GPIO_I2C_SCL)
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
/*
* I2C RTC
*/
#define CONFIG_RTC_M41T11 1
#define CFG_I2C_RTC_ADDR 0x68
#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
/*
* Spartan3 FPGA configuration support
*/
#define CFG_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
#define CFG_FPGA_PRG (1 << CFG_GPIO_PRG) /* FPGA program pin (cpu output)*/
#define CFG_FPGA_CLK (1 << CFG_GPIO_CLK) /* FPGA clk pin (cpu output) */
#define CFG_FPGA_DATA (1 << CFG_GPIO_DATA) /* FPGA data pin (cpu output) */
#define CFG_FPGA_INIT (1 << CFG_GPIO_INIT) /* FPGA init pin (cpu input) */
#define CFG_FPGA_DONE (1 << CFG_GPIO_DONE) /* FPGA done pin (cpu input) */
/*
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
#endif /* __CONFIG_H */

2
include/configs/r5200.h
View File

@@ -72,7 +72,7 @@
#include <cmd_confdefs.h>
/* Note: We only copy one sectors worth of application code from location
* 10200000 for speed purposes. Increase the size if necessary */
* 10200000 for speed purposes. Increase the size if necessary */
#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400"
#define CONFIG_BOOTDELAY 1

461
include/configs/virtlab2.h Normal file
View File

@@ -0,0 +1,461 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
#define CONFIG_TQM8xxL 1
#ifdef CONFIG_LCD /* with LCD controller ? */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM823L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#if defined(CONFIG_LCD)
# undef CONFIG_STATUS_LED /* disturbs display */
#else
# define CONFIG_STATUS_LED 1 /* Status LED enabled */
#endif /* CONFIG_LCD */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#ifdef CONFIG_SPLASH_SCREEN
# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_BMP | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_IDE | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
#else
# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_IDE | \
CFG_CMD_NFS | \
CFG_CMD_SNTP )
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if 0
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFFF00000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else /* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*/
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
#define CFG_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/*
* FLASH timing:
*/
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_3_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
#define CFG_OR1_REMAP CFG_OR0_REMAP
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
/*
* BR2/3 and OR2/3 (SDRAM)
*
*/
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000A00
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#ifndef CONFIG_CAN_DRIVER
#define CFG_OR3_PRELIM CFG_OR2_PRELIM
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
BR_PS_8 | BR_MS_UPMB | BR_V )
#endif /* CONFIG_CAN_DRIVER */
/*
* Memory Periodic Timer Prescaler
*
* The Divider for PTA (refresh timer) configuration is based on an
* example SDRAM configuration (64 MBit, one bank). The adjustment to
* the number of chip selects (NCS) and the actually needed refresh
* rate is done by setting MPTPR.
*
* PTA is calculated from
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
*
* gclk CPU clock (not bus clock!)
* Trefresh Refresh cycle * 4 (four word bursts used)
*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
* --------------------------------------------
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
*
* 50 MHz => 50.000.000 / Divider = 98
* 66 Mhz => 66.000.000 / Divider = 129
* 80 Mhz => 80.000.000 / Divider = 156
*/
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
#define CFG_MAMR_PTA 98
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
*/
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* Map peripheral control registers on CS4 */
#define CFG_PERIPHERAL_BASE 0xA0000000
#define CFG_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
#define CFG_OR4_PRELIM (CFG_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK)
#define CFG_BR4_PRELIM ((CFG_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
#define PCMCIA_CTRL (CFG_PERIPHERAL_BASE + 0xB00)
#endif /* __CONFIG_H */

4
include/configs/yellowstone.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2005
* (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -174,7 +174,7 @@
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yellowstone/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc100000\0" \
"ramdisk_addr=fc180000\0" \
"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \

6
include/configs/yosemite.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2005
* (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -109,6 +109,8 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
@@ -174,7 +176,7 @@
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yosemite/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc100000\0" \
"ramdisk_addr=fc180000\0" \
"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \

2
include/flash.h
View File

@@ -234,6 +234,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */
#define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */
#define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */
#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */
#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */
#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
@@ -343,6 +344,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */
#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */
#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */

134
include/ppc440.h
View File

@@ -1357,56 +1357,106 @@
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
#if defined(CONFIG_440GP)
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000700)
#define GPIO0 0
#define GPIO1 1
#define GPIO0_OR (GPIO_BASE0+0x0)
#define GPIO0_TCR (GPIO_BASE0+0x4)
#define GPIO0_ODR (GPIO_BASE0+0x18)
#define GPIO0_IR (GPIO_BASE0+0x1C)
#if defined(CONFIG_440GP)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
#define GPIO0_OR (GPIO0_BASE+0x0)
#define GPIO0_TCR (GPIO0_BASE+0x4)
#define GPIO0_ODR (GPIO0_BASE+0x18)
#define GPIO0_IR (GPIO0_BASE+0x1C)
#endif /* CONFIG_440GP */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
#define GPIO0_OR (GPIO_BASE0+0x0)
#define GPIO0_TCR (GPIO_BASE0+0x4)
#define GPIO0_OSRL (GPIO_BASE0+0x8)
#define GPIO0_OSRH (GPIO_BASE0+0xC)
#define GPIO0_TSRL (GPIO_BASE0+0x10)
#define GPIO0_TSRH (GPIO_BASE0+0x14)
#define GPIO0_ODR (GPIO_BASE0+0x18)
#define GPIO0_IR (GPIO_BASE0+0x1C)
#define GPIO0_RR1 (GPIO_BASE0+0x20)
#define GPIO0_RR2 (GPIO_BASE0+0x24)
#define GPIO0_RR3 (GPIO_BASE0+0x28)
#define GPIO0_ISR1L (GPIO_BASE0+0x30)
#define GPIO0_ISR1H (GPIO_BASE0+0x34)
#define GPIO0_ISR2L (GPIO_BASE0+0x38)
#define GPIO0_ISR2H (GPIO_BASE0+0x3C)
#define GPIO0_ISR3L (GPIO_BASE0+0x40)
#define GPIO0_ISR3H (GPIO_BASE0+0x44)
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
#define GPIOx_IR 0x1C /* GPIO Input Register */
#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
#define GPIO1_OR (GPIO_BASE1+0x0)
#define GPIO1_TCR (GPIO_BASE1+0x4)
#define GPIO1_OSRL (GPIO_BASE1+0x8)
#define GPIO1_OSRH (GPIO_BASE1+0xC)
#define GPIO1_TSRL (GPIO_BASE1+0x10)
#define GPIO1_TSRH (GPIO_BASE1+0x14)
#define GPIO1_ODR (GPIO_BASE1+0x18)
#define GPIO1_IR (GPIO_BASE1+0x1C)
#define GPIO1_RR1 (GPIO_BASE1+0x20)
#define GPIO1_RR2 (GPIO_BASE1+0x24)
#define GPIO1_RR3 (GPIO_BASE1+0x28)
#define GPIO1_ISR1L (GPIO_BASE1+0x30)
#define GPIO1_ISR1H (GPIO_BASE1+0x34)
#define GPIO1_ISR2L (GPIO_BASE1+0x38)
#define GPIO1_ISR2H (GPIO_BASE1+0x3C)
#define GPIO1_ISR3L (GPIO_BASE1+0x40)
#define GPIO1_ISR3H (GPIO_BASE1+0x44)
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
#define GPIO0_OR (GPIO0_BASE+0x0)
#define GPIO0_TCR (GPIO0_BASE+0x4)
#define GPIO0_OSRL (GPIO0_BASE+0x8)
#define GPIO0_OSRH (GPIO0_BASE+0xC)
#define GPIO0_TSRL (GPIO0_BASE+0x10)
#define GPIO0_TSRH (GPIO0_BASE+0x14)
#define GPIO0_ODR (GPIO0_BASE+0x18)
#define GPIO0_IR (GPIO0_BASE+0x1C)
#define GPIO0_RR1 (GPIO0_BASE+0x20)
#define GPIO0_RR2 (GPIO0_BASE+0x24)
#define GPIO0_RR3 (GPIO0_BASE+0x28)
#define GPIO0_ISR1L (GPIO0_BASE+0x30)
#define GPIO0_ISR1H (GPIO0_BASE+0x34)
#define GPIO0_ISR2L (GPIO0_BASE+0x38)
#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
#define GPIO0_ISR3L (GPIO0_BASE+0x40)
#define GPIO0_ISR3H (GPIO0_BASE+0x44)
#define GPIO1_OR (GPIO1_BASE+0x0)
#define GPIO1_TCR (GPIO1_BASE+0x4)
#define GPIO1_OSRL (GPIO1_BASE+0x8)
#define GPIO1_OSRH (GPIO1_BASE+0xC)
#define GPIO1_TSRL (GPIO1_BASE+0x10)
#define GPIO1_TSRH (GPIO1_BASE+0x14)
#define GPIO1_ODR (GPIO1_BASE+0x18)
#define GPIO1_IR (GPIO1_BASE+0x1C)
#define GPIO1_RR1 (GPIO1_BASE+0x20)
#define GPIO1_RR2 (GPIO1_BASE+0x24)
#define GPIO1_RR3 (GPIO1_BASE+0x28)
#define GPIO1_ISR1L (GPIO1_BASE+0x30)
#define GPIO1_ISR1H (GPIO1_BASE+0x34)
#define GPIO1_ISR2L (GPIO1_BASE+0x38)
#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
#define GPIO_GROUP_MAX 2
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
/* For the other GPIO number, you must shift */
#ifndef __ASSEMBLY__
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef struct { unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
} gpio_param_s;
#endif /* __ASSEMBLY__ */
/*
* Macros for accessing the indirect EBC registers
*/