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mpc83xx: serdes: add forgotten shifts for rfcks

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The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).

Though, for SGMII we'll need 125MHz clocks.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Anton Vorontsov
2008-10-02 18:31:56 +04:00
committed by Kim Phillips
parent 55c531984d
commit 6f9cc6608b
2 changed files with 6 additions and 6 deletions
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2
cpu/mpc83xx/serdes.c
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@@ -42,7 +42,7 @@
#define FSL_SRDSRSTCTL_RST 0x80000000
#define FSL_SRDSRSTCTL_SATA_RESET 0xf
void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd)
void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
{
void *regs = (void *)CONFIG_SYS_IMMR + offset;
u32 tmp;