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Merge git://git.denx.de/u-boot-usb

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This commit is contained in:
Tom Rini
2015-07-24 16:39:56 -04:00
parent 5a9749ee12 58d6d139c3
commit 6f4e050639
53 changed files with 667 additions and 375 deletions
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28
include/linux/usb/dwc3.h
View File

@@ -109,7 +109,11 @@ struct dwc3 { /* offset: 0xC100 */
u32 g_hwparams8;
u32 reserved4[63];
u32 reserved4[11];
u32 g_fladj;
u32 reserved5[51];
u32 d_cfg;
u32 d_ctl;
@@ -118,15 +122,15 @@ struct dwc3 { /* offset: 0xC100 */
u32 d_gcmdpar;
u32 d_gcmd;
u32 reserved5[2];
u32 reserved6[2];
u32 d_alepena;
u32 reserved6[55];
u32 reserved7[55];
struct d_physical_endpoint d_phy_ep_cmd[32];
u32 reserved7[128];
u32 reserved8[128];
u32 o_cfg;
u32 o_ctl;
@@ -134,7 +138,7 @@ struct dwc3 { /* offset: 0xC100 */
u32 o_evten;
u32 o_sts;
u32 reserved8[3];
u32 reserved9[3];
u32 adp_cfg;
u32 adp_ctl;
@@ -143,7 +147,7 @@ struct dwc3 { /* offset: 0xC100 */
u32 bc_cfg;
u32 reserved9;
u32 reserved10;
u32 bc_evt;
u32 bc_evten;
@@ -191,4 +195,16 @@ struct dwc3 { /* offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 << 30)
#define DWC3_DCTL_LSFTRST (1 << 29)
/* Global Frame Length Adjustment Register */
#define GFLADJ_30MHZ_REG_SEL (1 << 7)
#define GFLADJ_30MHZ(n) ((n) & 0x3f)
#define GFLADJ_30MHZ_DEFAULT 0x20
#ifdef CONFIG_USB_XHCI_DWC3
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
int dwc3_core_init(struct dwc3 *dwc3_reg);
void usb_phy_reset(struct dwc3 *dwc3_reg);
void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
#endif
#endif /* __DWC3_H_ */

64
include/linux/usb/xhci-fsl.h Normal file
View File

@@ -0,0 +1,64 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* FSL USB HOST xHCI Controller
*
* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_XHCI_FSL_H_
#define _ASM_ARCH_XHCI_FSL_H_
/* Default to the FSL XHCI defines */
#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
#define USB3_PHY_RX_POWERON BIT(14)
#define USB3_PHY_TX_POWERON BIT(15)
#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
#define USB3_PWRCTL_CLK_CMD_SHIFT 14
#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
/* USBOTGSS_WRAPPER definitions */
#define USBOTGSS_WRAPRESET BIT(17)
#define USBOTGSS_DMADISABLE BIT(16)
#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
#define USBOTGSS_IDLEMODE_SMRT BIT(3)
#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
/* USBOTGSS_IRQENABLE_SET_0 bit */
#define USBOTGSS_COREIRQ_EN BIT(1)
/* USBOTGSS_IRQENABLE_SET_1 bits */
#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
};
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#elif defined(CONFIG_LS2085A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* _ASM_ARCH_XHCI_FSL_H_ */