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Merge branch 'kumar'

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This commit is contained in:
Andy Fleming
2008-01-17 15:52:38 -06:00
committed by Andrew Fleming-AFLEMING
parent f188896c2f 7dc358bb0d
commit 6ea66a818d
106 changed files with 3062 additions and 3972 deletions
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80
include/asm-ppc/fsl_law.h Normal file
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@@ -0,0 +1,80 @@
#ifndef _FSL_LAW_H_
#define _FSL_LAW_H_
#include <asm/io.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
enum law_size {
LAW_SIZE_4K = 0xb,
LAW_SIZE_8K,
LAW_SIZE_16K,
LAW_SIZE_32K,
LAW_SIZE_64K,
LAW_SIZE_128K,
LAW_SIZE_256K,
LAW_SIZE_512K,
LAW_SIZE_1M,
LAW_SIZE_2M,
LAW_SIZE_4M,
LAW_SIZE_8M,
LAW_SIZE_16M,
LAW_SIZE_32M,
LAW_SIZE_64M,
LAW_SIZE_128M,
LAW_SIZE_256M,
LAW_SIZE_512M,
LAW_SIZE_1G,
LAW_SIZE_2G,
LAW_SIZE_4G,
LAW_SIZE_8G,
LAW_SIZE_16G,
LAW_SIZE_32G,
};
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
#ifndef CONFIG_MPC8572
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
LAW_TRGT_IF_LBC = 0x04,
LAW_TRGT_IF_CCSR = 0x08,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
};
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
#ifdef CONFIG_MPC8641
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
#ifdef CONFIG_MPC8572
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
struct law_entry {
int index;
phys_addr_t addr;
enum law_size size;
enum law_trgt_if trgt_id;
};
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern void disable_law(u8 idx);
extern void init_laws(void);
/* define in board code */
extern struct law_entry law_table[];
extern int num_law_entries;
#endif

31
include/asm-ppc/mmu.h
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@@ -418,6 +418,37 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
#ifdef CONFIG_E500
#ifndef __ASSEMBLY__
extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
u8 ts, u8 esel, u8 tsize, u8 iprot);
extern void disable_tlb(u8 esel);
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
.wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
struct fsl_e_tlb_entry {
u8 tlb;
u32 epn;
u64 rpn;
u8 perms;
u8 wimge;
u8 ts;
u8 esel;
u8 tsize;
u8 iprot;
};
extern struct fsl_e_tlb_entry tlb_table[];
extern int num_tlb_entries;
#endif
#endif
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF
#define LAWAR_TRGT_IF 0x01F00000

2
include/configs/ATUM8548.h
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@@ -63,6 +63,8 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
#define CONFIG_SYS_CLK_FREQ 33000000

1
include/configs/MPC8540ADS.h
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@@ -55,6 +55,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

2
include/configs/MPC8540EVAL.h
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@@ -43,6 +43,8 @@
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/* Using Localbus SDRAM to emulate flash before we can program the flash,
* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
* Not availabe for EVAL board

1
include/configs/MPC8541CDS.h
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@@ -47,6 +47,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

2
include/configs/MPC8544DS.h
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@@ -42,6 +42,8 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */

1
include/configs/MPC8548CDS.h
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@@ -55,6 +55,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

1
include/configs/MPC8555CDS.h
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@@ -47,6 +47,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

1
include/configs/MPC8560ADS.h
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@@ -52,6 +52,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

1
include/configs/MPC8568MDS.h
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@@ -49,6 +49,7 @@
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* When initializing flash, if we cannot find the manufacturer ID,

1
include/configs/PM854.h
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@@ -51,6 +51,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

1
include/configs/PM856.h
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@@ -51,6 +51,7 @@
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

1
include/configs/SBC8540.h
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@@ -56,6 +56,7 @@
#undef CONFIG_PCI /* pci ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE

2
include/configs/TQM85xx.h
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@@ -50,6 +50,8 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#endif
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx
*

1
include/configs/sbc8548.h
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@@ -56,6 +56,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */

1
include/configs/sbc8560.h
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@@ -50,6 +50,7 @@
#undef CONFIG_PCI /* pci ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE

1
include/configs/stxgp3.h
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@@ -51,6 +51,7 @@
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/* sysclk for MPC85xx
*/

1
include/configs/stxssa.h
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@@ -51,6 +51,7 @@
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/* sysclk for MPC85xx
*/