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Merge tag 'u-boot-imx-20220422' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
u-boot-imx-20220422
-------------------

- Switch to DM_SERIAL
- Drop MMCROOT
- several cleanup

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11815
This commit is contained in:
Tom Rini
2022-04-22 08:12:20 -04:00
parent ea5583b90f d173b107be
commit 6e2af641e4
184 changed files with 6017 additions and 3024 deletions
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6
include/configs/apalis-imx8.h
View File

@@ -38,6 +38,7 @@
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttyLP1 earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \
@@ -49,11 +50,6 @@
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; tftp ${fdt_addr} " \
"apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
"panel=NULL\0" \
"script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \

124
include/configs/apalis-imx8x.h
View File

@@ -1,124 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Toradex
*/
#ifndef __APALIS_IMX8X_H
#define __APALIS_IMX8X_H
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include <linux/stringify.h>
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
#define MEM_LAYOUT_ENV_SETTINGS \
"kernel_addr_r=0x80280000\0" \
"fdt_addr_r=0x83100000\0" \
"ramdisk_addr_r=0x8a000000\0" \
"scriptaddr=0x83200000\0"
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
#define AHAB_ENV "sec_boot=no\0"
#endif
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
"${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
#define MFG_NAND_PARTITION ""
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#undef BOOTENV_RUN_NET_USB_START
#define BOOTENV_RUN_NET_USB_START ""
#define CONFIG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargs ${consoleargs} " \
"rdinit=/linuxrc g_mass_storage.stall=0 " \
"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
"g_mass_storage.idProduct=0x37FF " \
"g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
"${vidargs} clk_ignore_unused\0" \
"initrd_addr=0x83800000\0" \
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
"${fdt_addr};\0" \
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
AHAB_ENV \
BOOTENV \
CONFIG_MFG_ENV_SETTINGS \
M4_BOOT_ENV \
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
"consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
"fdt_file=imx8qxp-apalis-eval.dtb\0" \
"fdtfile=imx8qxp-apalis-eval.dtb\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"image=Image\0" \
"initrd_addr=0x83800000\0" \
"mmcargs=setenv bootargs ${consoleargs} " \
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"netargs=setenv bootargs ${consoleargs} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
"${vidargs}\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
"apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \
"${fdt_addr}\0" \
"panel=NULL\0" \
"script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0" \
"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Networking */
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE 0x5b040000
#define CONFIG_FEC_MXC_PHYADDR 0x4
#define PHY_ANEG_TIMEOUT 20000
#endif /* __APALIS_IMX8X_H */

12
include/configs/apalis-tk1.h
View File

@@ -59,18 +59,9 @@
"update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
"mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
"nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
"run nfsdtbload; dhcp ${kernel_addr_r} " \
"&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
"${soc}-${fdt_module}-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0"
#define BOARD_EXTRA_ENV_SETTINGS \
"boot_file=zImage\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttyS0\0" \
"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
"usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
@@ -79,7 +70,6 @@
"fdt_board=eval\0" \
"fdt_fixup=;\0" \
"fdt_module=" FDT_MODULE "\0" \
NFS_BOOTCMD \
UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \

21
include/configs/apalis_imx6.h
View File

@@ -89,32 +89,15 @@
"ramdisk_addr_r=0x12200000\0" \
"scriptaddr=0x17000000\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0:on root=/dev/nfs ro\0" \
"nfsboot=run setup; " \
"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
"run nfsdtbload; dhcp ${kernel_addr_r} " \
"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
#define FDT_FILE "imx6q-apalis-eval.dtb"
#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
#else
#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
"boot_file=zImage\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttymxc0\0" \
"defargs=enable_wait_mode=off vmalloc=400M\0" \
"fdt_file=" FDT_FILE "\0" \
"fdtfile=" FDT_FILE "\0" \
"fdt_board=eval\0" \
"fdt_fixup=;\0" \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \

3
include/configs/apalis_t30.h
View File

@@ -47,7 +47,8 @@
"mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
#define BOARD_EXTRA_ENV_SETTINGS \
UBOOT_UPDATE
UBOOT_UPDATE \
"boot_script_dhcp=boot.scr\0"
#include "tegra-common-post.h"

4
include/configs/aristainetos2.h
View File

@@ -26,12 +26,10 @@
#include "mx6_common.h"
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
@@ -183,7 +181,7 @@
"${pubkey}\0" \
"mainRargs=setenv bootargs console=${console},${baudrate} " \
"rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"mmcRargs=setenv bootargs console=${console},${baudrate} " \

1
include/configs/capricorn-common.h
View File

@@ -109,7 +109,6 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
/* On CCP board, USDHC1 is for eMMC */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000

3
include/configs/cgtqmx8.h
View File

@@ -78,7 +78,7 @@
"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -122,7 +122,6 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000

1
include/configs/cl-som-imx7.h
View File

@@ -104,7 +104,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#endif
/* USB Configs */

1
include/configs/cm_fx6.h
View File

@@ -147,7 +147,6 @@
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 0
#define IMX_FEC_BASE ENET_BASE_ADDR
/* USB */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

12
include/configs/colibri-imx6ull.h
View File

@@ -16,7 +16,6 @@
#define PHYS_SDRAM_SIZE SZ_1G
/* ENET1 */
#define IMX_FEC_BASE ENET2_BASE_ADDR
/* MMC Config */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
@@ -50,15 +49,6 @@
"ramdisk_addr_r=0x82200000\0" \
"scriptaddr=0x87000000\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
"setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${fdtfile} && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
"ubi.fm_autoconvert=1\0" \
@@ -98,9 +88,9 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
UBI_BOOTCMD \
UBOOT_UPDATE \
"boot_script_dhcp=boot.scr\0" \
"bootubipart=ubi\0" \
"console=ttymxc0\0" \
"defargs=user_debug=30\0" \

7
include/configs/colibri-imx8x.h
View File

@@ -67,6 +67,7 @@
M4_BOOT_ENV \
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
@@ -79,12 +80,6 @@
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"netargs=setenv bootargs ${consoleargs} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
"${vidargs}\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
"colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \
"${fdt_addr}\0" \
"panel=NULL\0" \
"script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \

16
include/configs/colibri_imx6.h
View File

@@ -78,27 +78,15 @@
"ramdisk_addr_r=0x12200000\0" \
"scriptaddr=0x17000000\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
"nfsboot=run setup; " \
"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
"run nfsdtbload; dhcp ${kernel_addr_r} " \
"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
"boot_file=zImage\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttymxc0\0" \
"defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
"fdt_file=" FDT_FILE "\0" \
"fdtfile=" FDT_FILE "\0" \
"fdt_board=eval-v3\0" \
"fdt_fixup=;\0" \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
UBOOT_UPDATE \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \

11
include/configs/colibri_imx7.h
View File

@@ -89,15 +89,6 @@
"ramdisk_addr_r=0x82100000\0" \
"scriptaddr=0x87000000\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
"setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
"ubi.fm_autoconvert=1\0" \
@@ -136,10 +127,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
MODULE_EXTRA_ENV_SETTINGS \
UBOOT_UPDATE \
"boot_file=zImage\0" \
"boot_script_dhcp=boot.scr\0" \
"bootubipart=ubi\0" \
"console=ttymxc0\0" \
"defargs=\0" \

150
include/configs/colibri_pxa270.h
View File

@@ -1,150 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Board Configuration Options
*/
/*
* Environment settings
*/
/*
* Serial Console Configuration
*/
/*
* Bootloader Components Configuration
*/
/* I2C support */
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
#define CONFIG_SYS_I2C_PXA
#define CONFIG_PXA_STD_I2C
#define CONFIG_PXA_PWR_I2C
#endif
/* LCD support */
#ifdef CONFIG_LCD
#define CONFIG_PXA_LCD
#define CONFIG_PXA_VGA
#endif
/*
* Networking Configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_DM9000_BASE 0x08000000
#define DM9000_IO (CONFIG_DM9000_BASE)
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#endif
/*
* Clock Configuration
*/
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
/*
* DRAM Map
*/
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
/*
* NOR FLASH
*/
#ifdef CONFIG_CMD_FLASH
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
#endif
#define CONFIG_SYS_MONITOR_LEN 0x40000
/* Skip factory configuration block */
/*
* GPIO settings
*/
#define CONFIG_SYS_GPSR0_VAL 0x00000000
#define CONFIG_SYS_GPSR1_VAL 0x00020000
#define CONFIG_SYS_GPSR2_VAL 0x0002c000
#define CONFIG_SYS_GPSR3_VAL 0x00000000
#define CONFIG_SYS_GPCR0_VAL 0x00000000
#define CONFIG_SYS_GPCR1_VAL 0x00000000
#define CONFIG_SYS_GPCR2_VAL 0x00000000
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0xc8008000
#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
#define CONFIG_SYS_GPDR3_VAL 0x0061e804
#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
#define CONFIG_SYS_PSSR_VAL 0x30
/*
* Clock settings
*/
#define CONFIG_SYS_CKEN 0x00500240
#define CONFIG_SYS_CCCR 0x02000290
/*
* Memory settings
*/
#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
#define CONFIG_SYS_MDREFR_VAL 0x2003a031
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
/*
* PCMCIA and CF Interfaces
*/
#define CONFIG_SYS_MECR_VAL 0x00000000
#define CONFIG_SYS_MCMEM0_VAL 0x00028307
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
#define CONFIG_SYS_MCATT0_VAL 0x00038787
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
#define CONFIG_SYS_MCIO0_VAL 0x0002830f
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
#include "pxa-common.h"
#endif /* __CONFIG_H */

1
include/configs/colibri_t20.h
View File

@@ -24,6 +24,7 @@
/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
#define BOARD_EXTRA_ENV_SETTINGS \
"boot_script_dhcp=boot.scr\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
UBOOT_UPDATE

3
include/configs/colibri_t30.h
View File

@@ -45,7 +45,8 @@
"mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
#define BOARD_EXTRA_ENV_SETTINGS \
UBOOT_UPDATE
UBOOT_UPDATE \
"boot_script_dhcp=boot.scr\0"
#include "tegra-common-post.h"

11
include/configs/colibri_vf.h
View File

@@ -35,15 +35,6 @@
"update_uboot=nand erase.part u-boot && " \
"nand write ${loadaddr} u-boot ${filesize}\0" \
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
"setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
"ubi.fm_autoconvert=1\0" \
@@ -68,9 +59,9 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
UBI_BOOTCMD \
UBOOT_UPDATE \
"boot_script_dhcp=boot.scr\0" \
"console=ttyLP0\0" \
"defargs=user_debug=30\0" \
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \

1
include/configs/dh_imx6.h
View File

@@ -31,7 +31,6 @@
#define CONFIG_SYS_BOOTCOUNT_BE
/* FEC ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 7
/* MMC Configs */

1
include/configs/ge_bx50v3.h
View File

@@ -123,6 +123,5 @@
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5)
#endif /* __GE_BX50V3_CONFIG_H */

3
include/configs/gw_ventana.h
View File

@@ -31,9 +31,6 @@
#undef CONFIG_SYS_BOOTM_LEN
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* I2C Configs */
#define CONFIG_I2C_GSC 0
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0

3
include/configs/imx7-cm.h
View File

@@ -31,7 +31,7 @@
"fdt_addr=0x83000000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
@@ -83,7 +83,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

3
include/configs/imx8mm-cl-iot-gate.h
View File

@@ -88,7 +88,7 @@
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -140,7 +140,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000

8
include/configs/imx8mm_evk.h
View File

@@ -52,7 +52,7 @@
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
/* Link Definitions */
@@ -63,7 +63,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
@@ -78,11 +77,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC

15
include/configs/imx8mm_venice.h
View File

@@ -29,16 +29,19 @@
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x44000000\0" \
"kernel_addr_r=0x42000000\0" \
"ramdisk_addr_r=0x46400000\0" \
"scriptaddr=0x46000000\0"
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdt_addr_r=0x50200000\0" \
"scriptaddr=0x50280000\0" \
"ramdisk_addr_r=0x50300000\0" \
"kernel_comp_addr_r=0x40200000\0"
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(USB, usb, 0) \
func(USB, usb, 1) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#else
@@ -108,10 +111,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* FEC */
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC

24
include/configs/imx8mn_evk.h
View File

@@ -39,19 +39,27 @@
#endif
/* Initial environment variables */
/* see include/configs/ti_armv7_common.h */
#define ENV_MEM_LAYOUT_SETTINGS \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=0x42000000\0" \
"fdt_addr_r=0x48000000\0" \
"fdtoverlay_addr_r=0x49000000\0" \
"ramdisk_addr_r=0x48080000\0" \
"initrd_addr=0x48080000\0" \
"scriptaddr=0x40000000\0" \
"pxefile_addr_r=0x40100000\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=Image\0" \
BOOTENV \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"console=ttymxc1,115200\0" \
"fdt_addr_r=0x43000000\0" \
"boot_fit=no\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
ENV_MEM_LAYOUT_SETTINGS
/* Link Definitions */
@@ -62,7 +70,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
@@ -77,9 +84,4 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif

13
include/configs/imx8mn_venice.h
View File

@@ -26,16 +26,18 @@
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x44000000\0" \
"kernel_addr_r=0x42000000\0" \
"ramdisk_addr_r=0x46400000\0" \
"scriptaddr=0x46000000\0"
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdt_addr_r=0x50200000\0" \
"scriptaddr=0x50280000\0" \
"ramdisk_addr_r=0x50300000\0" \
"kernel_comp_addr_r=0x40200000\0"
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(USB, usb, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#else
@@ -104,9 +106,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* FEC */
#define CONFIG_FEC_MXC_PHYADDR 0

6
include/configs/imx8mp_evk.h
View File

@@ -61,7 +61,7 @@
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
/* Link Definitions */
@@ -72,7 +72,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* Totally 6GB DDR */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
@@ -90,7 +89,4 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif

3
include/configs/imx8mp_rsb3720.h
View File

@@ -104,7 +104,7 @@
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -155,7 +155,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* Totally 6GB or 4G DDR */
#define CONFIG_SYS_SDRAM_BASE 0x40000000

109
include/configs/imx8mp_venice.h Normal file
View File

@@ -0,0 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2022 Gateworks Corporation
*/
#ifndef __IMX8MP_VENICE_H
#define __IMX8MP_VENICE_H
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdt_addr_r=0x50200000\0" \
"scriptaddr=0x50280000\0" \
"ramdisk_addr_r=0x50300000\0" \
"kernel_comp_addr_r=0x40200000\0"
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(USB, usb, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#else
#define BOOTENV
#endif
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"script=boot.scr\0" \
"bootm_size=0x10000000\0" \
"dev=2\0" \
"preboot=gsc wd-disable\0" \
"console=ttymxc1,115200\0" \
"update_firmware=" \
"tftpboot $loadaddr $image && " \
"setexpr blkcnt $filesize + 0x1ff && " \
"setexpr blkcnt $blkcnt / 0x200 && " \
"mmc dev $dev && " \
"mmc write $loadaddr 0x40 $blkcnt\0" \
"loadfdt=" \
"if $fsload $fdt_addr_r $dir/$fdt_file1; " \
"then echo loaded $fdt_file1; " \
"elif $fsload $fdt_addr_r $dir/$fdt_file2; " \
"then echo loaded $fdt_file2; " \
"elif $fsload $fdt_addr_r $dir/$fdt_file3; " \
"then echo loaded $fdt_file3; " \
"elif $fsload $fdt_addr_r $dir/$fdt_file4; " \
"then echo loaded $fdt_file4; " \
"elif $fsload $fdt_addr_r $dir/$fdt_file5; " \
"then echo loaded $fdt_file5; " \
"fi\0" \
"boot_net=" \
"setenv fsload tftpboot; " \
"run loadfdt && tftpboot $kernel_addr_r $dir/Image && " \
"booti $kernel_addr_r - $fdt_addr_r\0" \
"update_rootfs=" \
"tftpboot $loadaddr $image && " \
"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
"update_all=" \
"tftpboot $loadaddr $image && " \
"gzwrite mmc $dev $loadaddr $filesize\0" \
"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_4G
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#endif

3
include/configs/imx8mq_cm.h
View File

@@ -55,7 +55,7 @@
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
/* Link Definitions */
@@ -66,7 +66,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000

3
include/configs/imx8mq_evk.h
View File

@@ -62,7 +62,7 @@
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
/* Link Definitions */
@@ -73,7 +73,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000

3
include/configs/imx8mq_phanbell.h
View File

@@ -52,7 +52,7 @@
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -101,7 +101,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000

8
include/configs/imx8qm_mek.h
View File

@@ -29,10 +29,6 @@
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
@@ -54,7 +50,7 @@
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -121,8 +117,6 @@
/* Default environment is in SD */
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000

3
include/configs/imx8qm_rom7720.h
View File

@@ -66,7 +66,7 @@
"initrd_addr=0x83800000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -114,7 +114,6 @@
* USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
* USDHC2 is for SD, USDHC3 is for SD on base board
*/
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000

8
include/configs/imx8qxp_mek.h
View File

@@ -27,10 +27,6 @@
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
@@ -52,7 +48,7 @@
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -119,8 +115,6 @@
/* Default environment is in SD */
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000

3
include/configs/imx8ulp_evk.h
View File

@@ -56,7 +56,7 @@
"initrd_addr=0x83800000\0" \
"bootm_size=0x10000000\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
/* Link Definitions */
@@ -65,7 +65,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk2p2"
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000

4
include/configs/liteboard.h
View File

@@ -35,7 +35,7 @@
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
@@ -100,7 +100,6 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* USB Configs */
#ifdef CONFIG_CMD_USB
@@ -113,7 +112,6 @@
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#endif

1
include/configs/m53menlo.h
View File

@@ -69,7 +69,6 @@
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#endif

1
include/configs/mccmon6.h
View File

@@ -40,7 +40,6 @@
#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) }
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_EXTRA_ENV_SETTINGS \

3
include/configs/mx6sllevk.h
View File

@@ -25,7 +25,7 @@
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
@@ -92,7 +92,6 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment organization */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR

3
include/configs/mx6sxsabresd.h
View File

@@ -126,7 +126,6 @@
/* Network */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#ifdef CONFIG_CMD_USB
@@ -149,6 +148,4 @@
#endif
#endif
#define CONFIG_SYS_FSL_USDHC_NUM 3
#endif /* __CONFIG_H */

5
include/configs/mx6ul_14x14_evk.h
View File

@@ -47,7 +47,7 @@
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
@@ -121,7 +121,6 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* USB Configs */
#ifdef CONFIG_CMD_USB
@@ -135,10 +134,8 @@
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x2
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#endif
#endif

3
include/configs/mx6ullevk.h
View File

@@ -43,7 +43,7 @@
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
@@ -118,7 +118,6 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_IOMUX_LPSR

9
include/configs/mx7dsabresd.h
View File

@@ -14,9 +14,6 @@
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_IMX_BOOTAUX
/* Set to QSPI1 A flash at default */
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
@@ -111,12 +108,6 @@
/* DMA stuff, needed for GPMI/MXS NAND support */
#endif
#ifdef CONFIG_NAND_MXS
#define CONFIG_SYS_FSL_USDHC_NUM 1
#else
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

4
include/configs/mx7ulp_com.h
View File

@@ -17,8 +17,6 @@
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
@@ -41,7 +39,7 @@
"fdt_addr=0x63000000\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \

3
include/configs/mx7ulp_evk.h
View File

@@ -13,7 +13,6 @@
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
@@ -47,7 +46,7 @@
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \

1
include/configs/npi_imx6ull.h
View File

@@ -46,7 +46,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#ifdef CONFIG_CMD_NET
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#endif

5
include/configs/phycore_imx8mm.h
View File

@@ -77,7 +77,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
@@ -92,8 +91,4 @@
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif /* __PHYCORE_IMX8MM_H */

5
include/configs/phycore_imx8mp.h
View File

@@ -77,7 +77,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
@@ -92,8 +91,4 @@
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif /* __PHYCORE_IMX8MP_H */

1
include/configs/pico-imx6.h
View File

@@ -117,7 +117,6 @@
/* Environment organization */
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 1
/* Framebuffer */

1
include/configs/pico-imx6ul.h
View File

@@ -27,7 +27,6 @@
/* Network support */
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR

3
include/configs/pico-imx8mq.h
View File

@@ -46,7 +46,7 @@
"initrd_high=0xffffffffffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=" \
@@ -80,7 +80,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000

27
include/configs/pxa-common.h
View File

@@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __CONFIG_PXA_COMMON_H__
#define __CONFIG_PXA_COMMON_H__
/*
* OHCI USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#ifdef CONFIG_CPU_PXA27X
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
#else
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci"
#endif
#endif /* __CONFIG_PXA_COMMON_H__ */

1
include/configs/somlabs_visionsom_6ull.h
View File

@@ -78,7 +78,6 @@
#endif
#ifdef CONFIG_CMD_NET
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#endif

1
include/configs/tqma6.h
View File

@@ -55,7 +55,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define IMX_FEC_BASE ENET_BASE_ADDR
#if defined(CONFIG_TQMA6X_MMC_BOOT)

10
include/configs/verdin-imx8mm.h
View File

@@ -52,17 +52,12 @@
MEM_LAYOUT_ENV_SETTINGS \
"bootcmd_mfg=fastboot 0\0" \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttymxc0\0" \
"fdt_addr=0x43000000\0" \
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \
"tftp ${fdt_addr} verdin/${fdtfile}; " \
"booti ${loadaddr} - ${fdt_addr}\0" \
"setup=setenv setupargs console=${console},${baudrate} " \
"console=tty1 consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
@@ -97,9 +92,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* ENET */
#define CONFIG_FEC_MXC_PHYADDR 7

10
include/configs/verdin-imx8mp.h
View File

@@ -76,12 +76,6 @@
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
"\0" \
"nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \
"tftp ${fdt_addr} verdin/${fdtfile}; " \
"booti ${loadaddr} - ${fdt_addr}\0" \
"setup=setenv setupargs console=${console},${baudrate} console=tty1 " \
"consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
@@ -116,8 +110,4 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif /* __VERDIN_IMX8MP_H */

1
include/configs/vf610twr.h
View File

@@ -23,7 +23,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
/* I2C Configs */

1
include/configs/vining_2000.h
View File

@@ -44,7 +44,6 @@
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* Network */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

4
include/configs/xpress.h
View File

@@ -34,7 +34,6 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment is in stored in the eMMC boot partition */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -43,7 +42,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_UBOOT_SECTOR_START 0x2
@@ -61,7 +59,7 @@
"ip_dyn=yes\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \

46
include/dt-bindings/power/imx8mp-power.h Normal file
View File

@@ -0,0 +1,46 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
*/
#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0
#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1
#define IMX8MP_POWER_DOMAIN_USB1_PHY 2
#define IMX8MP_POWER_DOMAIN_USB2_PHY 3
#define IMX8MP_POWER_DOMAIN_MLMIX 4
#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5
#define IMX8MP_POWER_DOMAIN_GPU2D 6
#define IMX8MP_POWER_DOMAIN_GPUMIX 7
#define IMX8MP_POWER_DOMAIN_VPUMIX 8
#define IMX8MP_POWER_DOMAIN_GPU3D 9
#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10
#define IMX8MP_POWER_DOMAIN_VPU_G1 11
#define IMX8MP_POWER_DOMAIN_VPU_G2 12
#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13
#define IMX8MP_POWER_DOMAIN_HDMIMIX 14
#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15
#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16
#define IMX8MP_POWER_DOMAIN_HSIOMIX 17
#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18
#define IMX8MP_HSIOBLK_PD_USB 0
#define IMX8MP_HSIOBLK_PD_USB_PHY1 1
#define IMX8MP_HSIOBLK_PD_USB_PHY2 2
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
#define IMX8MP_MEDIABLK_PD_ISI 3
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
#define IMX8MP_MEDIABLK_PD_ISP2 6
#define IMX8MP_MEDIABLK_PD_ISP1 7
#define IMX8MP_MEDIABLK_PD_DWE 8
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9
#endif

21
include/power-domain.h
View File

@@ -107,6 +107,27 @@ int power_domain_get_by_index(struct udevice *dev,
}
#endif
/**
* power_domain_get_by_name - Get the named power domain for a device.
*
* @dev: The client device.
* @power_domain: A pointer to a power domain struct to initialize.
* @name: Power domain name to be powered on.
*
* Return: 0 if OK, or a negative error code.
*/
#if CONFIG_IS_ENABLED(POWER_DOMAIN)
int power_domain_get_by_name(struct udevice *dev,
struct power_domain *power_domain, const char *name);
#else
static inline
int power_domain_get_by_name(struct udevice *dev,
struct power_domain *power_domain, const char *name)
{
return -ENOSYS;
}
#endif
/**
* power_domain_free - Free a previously requested power domain.
*