Add support for Eukrea CPUAT91 SBC
CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
This commit is contained in:
Tom Rix
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include/configs/cpuat91.h
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228
include/configs/cpuat91.h
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/*
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* CPUAT91 by (C) Copyright 2006 Eric Benard
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* eric@eukrea.com
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*
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* Configuration settings for the CPUAT91 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_CPUAT91_RAM
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#define CONFIG_SKIP_LOWLEVEL_INIT 1
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#define CONFIG_SKIP_RELOCATE_UBOOT 1
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#define CONFIG_CPUAT91 1
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#else
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#define CONFIG_BOOTDELAY 1
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#endif
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#define AT91C_MAIN_CLOCK 179712000
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#define AT91C_MASTER_CLOCK 59904000
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#define AT91_SLOW_CLOCK 32768
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#define CONFIG_ARM920T 1
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#define CONFIG_AT91RM9200 1
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#undef CONFIG_USE_IRQ
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#define USE_920T_MMU 1
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
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#define CONFIG_SYS_MC_PUP_VAL 0x00000000
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#define CONFIG_SYS_MC_PUER_VAL 0x00000000
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#define CONFIG_SYS_MC_ASR_VAL 0x00000000
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#define CONFIG_SYS_MC_AASR_VAL 0x00000000
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
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#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
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#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
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/* sdram */
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#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
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#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
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#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
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#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
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#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
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#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
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#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/* define one of these to choose the DBGU, USART0 or USART1 as console */
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#define CONFIG_AT91RM9200_USART 1
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#define CONFIG_DBGU 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#define CONFIG_HARD_I2C 1
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#if defined(CONFIG_HARD_I2C)
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#endif
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_BOOTP_BOOTPATH 1
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#define CONFIG_BOOTP_GATEWAY 1
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#define CONFIG_BOOTP_HOSTNAME 1
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP 1
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#define CONFIG_CMD_PING 1
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#define CONFIG_CMD_MII 1
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#define CONFIG_CMD_CACHE 1
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#undef CONFIG_CMD_USB
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NFS
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#if defined(CONFIG_HARD_I2C)
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#define CONFIG_CMD_EEPROM 1
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#define CONFIG_CMD_I2C 1
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#endif
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x02000000
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END \
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(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
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#define CONFIG_DRIVER_ETHER 1
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91C_USE_RMII 1
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#define CONFIG_PHY_ADDRESS (1 << 5)
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#define CONFIG_KS8721_PHY 1
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_EMPTY_INFO 1
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define PHYS_FLASH_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#if defined(CONFIG_CMD_USB)
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_AT91C_PQFP_UHPBU 1
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#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#endif
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_SYS_LOAD_ADDR 0x21000000
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
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#define CONFIG_SYS_PROMPT "CPUAT91=> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 32
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define CONFIG_STACKSIZE (32 * 1024)
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#if defined(CONFIG_USE_IRQ)
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#error CONFIG_USE_IRQ not supported
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#endif
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#define CONFIG_DEVICE_NULLDEV 1
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#define CONFIG_SILENT_CONSOLE 1
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_VERSION_VARIABLE 1
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
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#define MTDPARTS_DEFAULT \
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"mtdparts=physmap-flash.0:" \
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"128k(u-boot)ro," \
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"128k(u-boot-env)," \
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"1408k(kernel)," \
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"-(rootfs)"
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#define CONFIG_BOOTARGS \
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"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
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#define CONFIG_BOOTCOMMAND "run flashboot"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mtdid=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
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"1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
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"10000000 ${filesize}\0" \
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"flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
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"1019ffff; erase 10040000 1019ffff; cp.b 21000000 " \
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"10040000 ${filesize}\0" \
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"flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
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"101a0000 10ffffff; erase 101a0000 10ffffff; cp.b " \
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"21000000 101A0000 ${filesize}\0" \
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"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"flashboot=run ramargs;bootm 10040000\0" \
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"netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
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"bootm 21000000\0"
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#endif /* __CONFIG_H */
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78
include/ks8721.h
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78
include/ks8721.h
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/*
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* NOTE: MICREL ethernet Physical layer
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*
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* Version: KS8721.h
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*
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* Authors: Eric Benard (based on dm9161.h)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/* MICREL PHYSICAL LAYER TRANSCEIVER KS8721 */
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#define KS8721_BMCR 0
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#define KS8721_BMSR 1
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#define KS8721_PHYID1 2
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#define KS8721_PHYID2 3
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#define KS8721_ANAR 4
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#define KS8721_ANLPAR 5
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#define KS8721_ANER 6
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#define KS8721_RECR 15
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#define KS8721_MDINTR 27
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#define KS8721_100BT 31
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/* --Bit definitions: KS8721_BMCR */
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#define KS8721_RESET (1 << 15)
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#define KS8721_LOOPBACK (1 << 14)
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#define KS8721_SPEED_SELECT (1 << 13)
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#define KS8721_AUTONEG (1 << 12)
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#define KS8721_POWER_DOWN (1 << 11)
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#define KS8721_ISOLATE (1 << 10)
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#define KS8721_RESTART_AUTONEG (1 << 9)
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#define KS8721_DUPLEX_MODE (1 << 8)
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#define KS8721_COLLISION_TEST (1 << 7)
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#define KS8721_DISABLE (1 << 0)
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/*--Bit definitions: KS8721_BMSR */
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#define KS8721_100BASE_T4 (1 << 15)
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#define KS8721_100BASE_TX_FD (1 << 14)
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#define KS8721_100BASE_T4_HD (1 << 13)
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#define KS8721_10BASE_T_FD (1 << 12)
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#define KS8721_10BASE_T_HD (1 << 11)
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#define KS8721_MF_PREAMB_SUPPR (1 << 6)
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#define KS8721_AUTONEG_COMP (1 << 5)
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#define KS8721_REMOTE_FAULT (1 << 4)
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#define KS8721_AUTONEG_ABILITY (1 << 3)
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#define KS8721_LINK_STATUS (1 << 2)
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#define KS8721_JABBER_DETECT (1 << 1)
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#define KS8721_EXTEND_CAPAB (1 << 0)
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/*--Bit definitions: KS8721_PHYID */
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#define KS8721_PHYID_OUI 0x0885
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#define KS8721_LSB_MASK 0x3F
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#define KS8721BL_MODEL 0x21
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#define KS8721_MODELMASK 0x3F0
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#define KS8721BL_REV 0x9
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#define KS8721_REVMASK 0xF
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/*--Bit definitions: KS8721_ANAR, KS8721_ANLPAR */
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#define KS8721_NP (1 << 15)
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#define KS8721_ACK (1 << 14)
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#define KS8721_RF (1 << 13)
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#define KS8721_PAUSE (1 << 10)
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#define KS8721_T4 (1 << 9)
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#define KS8721_TX_FDX (1 << 8)
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#define KS8721_TX_HDX (1 << 7)
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#define KS8721_10_FDX (1 << 6)
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#define KS8721_10_HDX (1 << 5)
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#define KS8721_AN_IEEE_802_3 0x0001
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/****************** function prototypes **********************/
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unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac);
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unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac);
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unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status);
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unsigned char ks8721_initphy(AT91PS_EMAC p_mac);
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