i2c: fsl_i2c: Migrate to Kconfig
- As there are no boards that use different values for speed / slave on different buses, use a single option. - Switch to using the common SYS_I2C_SPEED / SYS_I2C_SLAVE options. - Introduce _HAS_ options for additional buses as only the first one is common to all users. - Convert all remaining symbols to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
@@ -40,10 +40,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@@ -49,10 +49,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_i2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
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#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
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@@ -70,10 +70,6 @@
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#define CONFIG_HOSTNAME "M5253DEMO"
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
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#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
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@@ -59,10 +59,6 @@
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
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#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
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@@ -55,10 +55,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@@ -49,10 +49,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@@ -51,10 +51,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@@ -165,13 +165,6 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* SPI */
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@@ -220,13 +220,6 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* SPI */
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@@ -203,10 +203,6 @@
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#define CONFIG_FSL_SERDES2 0xe3100
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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/*
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@@ -206,10 +206,6 @@
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* RapidIO MMU */
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@@ -295,16 +295,12 @@ extern unsigned long get_clock_freq(void);
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* I2C
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*/
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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#else
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define CONFIG_SYS_I2C_FSL
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_CCID
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@@ -202,10 +202,6 @@
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* RapidIO MMU */
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@@ -497,21 +497,13 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define I2C_PCA9557_ADDR1 0x18
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#define I2C_PCA9557_ADDR2 0x19
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#define I2C_PCA9557_BUS_NUM 0
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#define CONFIG_SYS_I2C_FSL
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/* I2C EEPROM */
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#if defined(CONFIG_TARGET_P1010RDB_PB)
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@@ -256,18 +256,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define CONFIG_SYS_I2C_FSL
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/*
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@@ -417,19 +417,11 @@ unsigned long get_board_ddr_clk(void);
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#endif
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
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#define I2C_PCA6408_BUS_NUM 1
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#define I2C_PCA6408_ADDR 0x20
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@@ -452,25 +452,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
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#endif
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C3_SPEED 400000
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#define CONFIG_SYS_FSL_I2C4_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
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#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR 0x70
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#define I2C_MUX_CH_DEFAULT 0x8
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@@ -367,22 +367,6 @@ unsigned long get_board_ddr_clk(void);
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/*
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* I2C
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*/
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
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#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
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#define CONFIG_SYS_FSL_I2C_SPEED 100000
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#define CONFIG_SYS_FSL_I2C2_SPEED 100000
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#define CONFIG_SYS_FSL_I2C3_SPEED 100000
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#define CONFIG_SYS_FSL_I2C4_SPEED 100000
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#endif
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#define CONFIG_SYS_I2C_FSL
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
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#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
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@@ -319,26 +319,11 @@ unsigned long get_board_ddr_clk(void);
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/*
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* I2C
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*/
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
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#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
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#define CONFIG_SYS_FSL_I2C_SPEED 100000
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#define CONFIG_SYS_FSL_I2C2_SPEED 100000
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#define CONFIG_SYS_FSL_I2C3_SPEED 100000
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#define CONFIG_SYS_FSL_I2C4_SPEED 100000
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define CONFIG_SYS_I2C_FSL
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
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#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
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#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
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@@ -154,18 +154,11 @@
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
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#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
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#endif
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#define CONFIG_SYS_I2C_FSL
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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@@ -428,8 +421,6 @@ unsigned long get_board_ddr_clk(void);
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#endif
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/* I2C */
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#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
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#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
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#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
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@@ -310,13 +310,6 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
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#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
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@@ -58,10 +58,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 80000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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/*
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@@ -266,18 +266,10 @@
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#else
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#if CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
|
||||
@@ -194,14 +194,8 @@
|
||||
* I2C
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0
|
||||
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_DS1338
|
||||
#define CONFIG_I2C_RTC_ADDR 0x68
|
||||
|
||||
@@ -163,10 +163,6 @@
|
||||
/*
|
||||
* I2C setup
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
||||
|
||||
/*
|
||||
|
||||
@@ -64,14 +64,6 @@
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_NUM_I2C_BUSES 4
|
||||
#define CONFIG_SYS_I2C_MAX_HOPS 1
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 200000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 200000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
|
||||
|
||||
@@ -464,19 +464,12 @@
|
||||
|
||||
/* I2C */
|
||||
#if !CONFIG_IS_ENABLED(DM_I2C)
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
#else
|
||||
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
|
||||
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
|
||||
|
||||
/*
|
||||
|
||||
Reference in New Issue
Block a user