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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse Source
This commit is contained in:
Wolfgang Denk
2009-02-01 21:38:07 +01:00
parent ee924e0030 4e69087a1d
commit 6c6e042ab3
113 changed files with 12041 additions and 28 deletions
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2
include/asm-arm/arch-mx31/mx31-regs.h
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@@ -34,7 +34,7 @@
#define CCM_PDR1 (CCM_BASE + 0x08)
#define CCM_RCSR (CCM_BASE + 0x0c)
#define CCM_MPCTL (CCM_BASE + 0x10)
#define CCM_UPCTL (CCM_BASE + 0x10)
#define CCM_UPCTL (CCM_BASE + 0x14)
#define CCM_SPCTL (CCM_BASE + 0x18)
#define CCM_COSR (CCM_BASE + 0x1C)
#define CCM_CGR0 (CCM_BASE + 0x20)

62
include/asm-arm/arch-omap3/clocks.h Normal file
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@@ -0,0 +1,62 @@
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CLOCKS_H_
#define _CLOCKS_H_
#define LDELAY 12000000
#define S12M 12000000
#define S13M 13000000
#define S19_2M 19200000
#define S24M 24000000
#define S26M 26000000
#define S38_4M 38400000
#define FCK_IVA2_ON 0x00000001
#define FCK_CORE1_ON 0x03fffe29
#define ICK_CORE1_ON 0x3ffffffb
#define ICK_CORE2_ON 0x0000001f
#define FCK_WKUP_ON 0x000000e9
#define ICK_WKUP_ON 0x0000003f
#define FCK_DSS_ON 0x00000005
#define ICK_DSS_ON 0x00000001
#define FCK_CAM_ON 0x00000001
#define ICK_CAM_ON 0x00000001
#define FCK_PER_ON 0x0003ffff
#define ICK_PER_ON 0x0003ffff
/* Used to index into DPLL parameter tables */
typedef struct {
unsigned int m;
unsigned int n;
unsigned int fsel;
unsigned int m2;
} dpll_param;
/* Following functions are exported from lowlevel_init.S */
extern dpll_param *get_mpu_dpll_param(void);
extern dpll_param *get_iva_dpll_param(void);
extern dpll_param *get_core_dpll_param(void);
extern dpll_param *get_per_dpll_param(void);
extern void *_end_vect, *_start;
#endif

285
include/asm-arm/arch-omap3/clocks_omap3.h Normal file
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@@ -0,0 +1,285 @@
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CLOCKS_OMAP3_H_
#define _CLOCKS_OMAP3_H_
#define PLL_STOP 1 /* PER & IVA */
#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
/*
* The following configurations are OPP and SysClk value independant
* and hence are defined here. All the other DPLL related values are
* tabulated in lowlevel_init.S.
*/
/* CORE DPLL */
#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
#define CORE_FUSB_DIV 2 /* 41.5MHz: */
#define CORE_L4_DIV 2 /* 83MHz : L4 */
#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
/* PER DPLL */
#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */
#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
/* MPU DPLL */
#define MPU_M_12_ES1 0x0FE
#define MPU_N_12_ES1 0x07
#define MPU_FSEL_12_ES1 0x05
#define MPU_M2_12_ES1 0x01
#define MPU_M_12_ES2 0x0FA
#define MPU_N_12_ES2 0x05
#define MPU_FSEL_12_ES2 0x07
#define MPU_M2_ES2 0x01
#define MPU_M_12 0x085
#define MPU_N_12 0x05
#define MPU_FSEL_12 0x07
#define MPU_M2_12 0x01
#define MPU_M_13_ES1 0x17D
#define MPU_N_13_ES1 0x0C
#define MPU_FSEL_13_ES1 0x03
#define MPU_M2_13_ES1 0x01
#define MPU_M_13_ES2 0x1F4
#define MPU_N_13_ES2 0x0C
#define MPU_FSEL_13_ES2 0x03
#define MPU_M2_13_ES2 0x01
#define MPU_M_13 0x10A
#define MPU_N_13 0x0C
#define MPU_FSEL_13 0x03
#define MPU_M2_13 0x01
#define MPU_M_19P2_ES1 0x179
#define MPU_N_19P2_ES1 0x12
#define MPU_FSEL_19P2_ES1 0x04
#define MPU_M2_19P2_ES1 0x01
#define MPU_M_19P2_ES2 0x271
#define MPU_N_19P2_ES2 0x17
#define MPU_FSEL_19P2_ES2 0x03
#define MPU_M2_19P2_ES2 0x01
#define MPU_M_19P2 0x14C
#define MPU_N_19P2 0x17
#define MPU_FSEL_19P2 0x03
#define MPU_M2_19P2 0x01
#define MPU_M_26_ES1 0x17D
#define MPU_N_26_ES1 0x19
#define MPU_FSEL_26_ES1 0x03
#define MPU_M2_26_ES1 0x01
#define MPU_M_26_ES2 0x0FA
#define MPU_N_26_ES2 0x0C
#define MPU_FSEL_26_ES2 0x07
#define MPU_M2_26_ES2 0x01
#define MPU_M_26 0x085
#define MPU_N_26 0x0C
#define MPU_FSEL_26 0x07
#define MPU_M2_26 0x01
#define MPU_M_38P4_ES1 0x1FA
#define MPU_N_38P4_ES1 0x32
#define MPU_FSEL_38P4_ES1 0x03
#define MPU_M2_38P4_ES1 0x01
#define MPU_M_38P4_ES2 0x271
#define MPU_N_38P4_ES2 0x2F
#define MPU_FSEL_38P4_ES2 0x03
#define MPU_M2_38P4_ES2 0x01
#define MPU_M_38P4 0x14C
#define MPU_N_38P4 0x2F
#define MPU_FSEL_38P4 0x03
#define MPU_M2_38P4 0x01
/* IVA DPLL */
#define IVA_M_12_ES1 0x07D
#define IVA_N_12_ES1 0x05
#define IVA_FSEL_12_ES1 0x07
#define IVA_M2_12_ES1 0x01
#define IVA_M_12_ES2 0x0B4
#define IVA_N_12_ES2 0x05
#define IVA_FSEL_12_ES2 0x07
#define IVA_M2_12_ES2 0x01
#define IVA_M_12 0x085
#define IVA_N_12 0x05
#define IVA_FSEL_12 0x07
#define IVA_M2_12 0x01
#define IVA_M_13_ES1 0x0FA
#define IVA_N_13_ES1 0x0C
#define IVA_FSEL_13_ES1 0x03
#define IVA_M2_13_ES1 0x01
#define IVA_M_13_ES2 0x168
#define IVA_N_13_ES2 0x0C
#define IVA_FSEL_13_ES2 0x03
#define IVA_M2_13_ES2 0x01
#define IVA_M_13 0x10A
#define IVA_N_13 0x0C
#define IVA_FSEL_13 0x03
#define IVA_M2_13 0x01
#define IVA_M_19P2_ES1 0x082
#define IVA_N_19P2_ES1 0x09
#define IVA_FSEL_19P2_ES1 0x07
#define IVA_M2_19P2_ES1 0x01
#define IVA_M_19P2_ES2 0x0E1
#define IVA_N_19P2_ES2 0x0B
#define IVA_FSEL_19P2_ES2 0x06
#define IVA_M2_19P2_ES2 0x01
#define IVA_M_19P2 0x14C
#define IVA_N_19P2 0x17
#define IVA_FSEL_19P2 0x03
#define IVA_M2_19P2 0x01
#define IVA_M_26_ES1 0x07D
#define IVA_N_26_ES1 0x0C
#define IVA_FSEL_26_ES1 0x07
#define IVA_M2_26_ES1 0x01
#define IVA_M_26_ES2 0x0B4
#define IVA_N_26_ES2 0x0C
#define IVA_FSEL_26_ES2 0x07
#define IVA_M2_26_ES2 0x01
#define IVA_M_26 0x085
#define IVA_N_26 0x0C
#define IVA_FSEL_26 0x07
#define IVA_M2_26 0x01
#define IVA_M_38P4_ES1 0x13F
#define IVA_N_38P4_ES1 0x30
#define IVA_FSEL_38P4_ES1 0x03
#define IVA_M2_38P4_ES1 0x01
#define IVA_M_38P4_ES2 0x0E1
#define IVA_N_38P4_ES2 0x17
#define IVA_FSEL_38P4_ES2 0x06
#define IVA_M2_38P4_ES2 0x01
#define IVA_M_38P4 0x14C
#define IVA_N_38P4 0x2F
#define IVA_FSEL_38P4 0x03
#define IVA_M2_38P4 0x01
/* CORE DPLL */
#define CORE_M_12 0xA6
#define CORE_N_12 0x05
#define CORE_FSEL_12 0x07
#define CORE_M2_12 0x01 /* M3 of 2 */
#define CORE_M_12_ES1 0x19F
#define CORE_N_12_ES1 0x0E
#define CORE_FSL_12_ES1 0x03
#define CORE_M2_12_ES1 0x1 /* M3 of 2 */
#define CORE_M_13 0x14C
#define CORE_N_13 0x0C
#define CORE_FSEL_13 0x03
#define CORE_M2_13 0x01 /* M3 of 2 */
#define CORE_M_13_ES1 0x1B2
#define CORE_N_13_ES1 0x10
#define CORE_FSL_13_ES1 0x03
#define CORE_M2_13_ES1 0x01 /* M3 of 2 */
#define CORE_M_19P2 0x19F
#define CORE_N_19P2 0x17
#define CORE_FSEL_19P2 0x03
#define CORE_M2_19P2 0x01 /* M3 of 2 */
#define CORE_M_19P2_ES1 0x19F
#define CORE_N_19P2_ES1 0x17
#define CORE_FSL_19P2_ES1 0x03
#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */
#define CORE_M_26 0xA6
#define CORE_N_26 0x0C
#define CORE_FSEL_26 0x07
#define CORE_M2_26 0x01 /* M3 of 2 */
#define CORE_M_26_ES1 0x1B2
#define CORE_N_26_ES1 0x21
#define CORE_FSL_26_ES1 0x03
#define CORE_M2_26_ES1 0x01 /* M3 of 2 */
#define CORE_M_38P4 0x19F
#define CORE_N_38P4 0x2F
#define CORE_FSEL_38P4 0x03
#define CORE_M2_38P4 0x01 /* M3 of 2 */
#define CORE_M_38P4_ES1 0x19F
#define CORE_N_38P4_ES1 0x2F
#define CORE_FSL_38P4_ES1 0x03
#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */
/* PER DPLL */
#define PER_M_12 0xD8
#define PER_N_12 0x05
#define PER_FSEL_12 0x07
#define PER_M2_12 0x09
#define PER_M_13 0x1B0
#define PER_N_13 0x0C
#define PER_FSEL_13 0x03
#define PER_M2_13 0x09
#define PER_M_19P2 0xE1
#define PER_N_19P2 0x09
#define PER_FSEL_19P2 0x07
#define PER_M2_19P2 0x09
#define PER_M_26 0xD8
#define PER_N_26 0x0C
#define PER_FSEL_26 0x07
#define PER_M2_26 0x09
#define PER_M_38P4 0xE1
#define PER_N_38P4 0x13
#define PER_FSEL_38P4 0x07
#define PER_M2_38P4 0x09
#endif /* endif _CLOCKS_OMAP3_H_ */

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include/asm-arm/arch-omap3/cpu.h Normal file
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/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _CPU_H
#define _CPU_H
/* Register offsets of common modules */
/* Control */
#ifndef __ASSEMBLY__
typedef struct ctrl {
unsigned char res1[0xC0];
unsigned short gpmc_nadv_ale; /* 0xC0 */
unsigned short gpmc_noe; /* 0xC2 */
unsigned short gpmc_nwe; /* 0xC4 */
unsigned char res2[0x22A];
unsigned int status; /* 0x2F0 */
} ctrl_t;
#else /* __ASSEMBLY__ */
#define CONTROL_STATUS 0x2F0
#endif /* __ASSEMBLY__ */
/* device type */
#define DEVICE_MASK (0x7 << 8)
#define SYSBOOT_MASK 0x1F
#define TST_DEVICE 0x0
#define EMU_DEVICE 0x1
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
/* GPMC CS3/cs4/cs6 not avaliable */
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
#define GPMC_CONFIG_CS6 0x150
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
#define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
#ifndef __ASSEMBLY__
typedef struct gpmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned char res2[0x4];
unsigned int irqstatus; /* 0x18 */
unsigned int irqenable; /* 0x1C */
unsigned char res3[0x20];
unsigned int timeout_control; /* 0x40 */
unsigned char res4[0xC];
unsigned int config; /* 0x50 */
unsigned int status; /* 0x54 */
unsigned char res5[0x19C];
unsigned int ecc_config; /* 0x1F4 */
unsigned int ecc_control; /* 0x1F8 */
unsigned int ecc_size_config; /* 0x1FC */
unsigned int ecc1_result; /* 0x200 */
unsigned int ecc2_result; /* 0x204 */
unsigned int ecc3_result; /* 0x208 */
unsigned int ecc4_result; /* 0x20C */
unsigned int ecc5_result; /* 0x210 */
unsigned int ecc6_result; /* 0x214 */
unsigned int ecc7_result; /* 0x218 */
unsigned int ecc8_result; /* 0x21C */
unsigned int ecc9_result; /* 0x220 */
} gpmc_t;
typedef struct gpmc_csx {
unsigned int config1; /* 0x00 */
unsigned int config2; /* 0x04 */
unsigned int config3; /* 0x08 */
unsigned int config4; /* 0x0C */
unsigned int config5; /* 0x10 */
unsigned int config6; /* 0x14 */
unsigned int config7; /* 0x18 */
unsigned int nand_cmd; /* 0x1C */
unsigned int nand_adr; /* 0x20 */
unsigned int nand_dat; /* 0x24 */
} gpmc_csx_t;
#else /* __ASSEMBLY__ */
#define GPMC_CONFIG1 0x00
#define GPMC_CONFIG2 0x04
#define GPMC_CONFIG3 0x08
#define GPMC_CONFIG4 0x0C
#define GPMC_CONFIG5 0x10
#define GPMC_CONFIG6 0x14
#define GPMC_CONFIG7 0x18
#endif /* __ASSEMBLY__ */
/* GPMC Mapping */
#define FLASH_BASE 0x10000000 /* NOR flash, */
/* aligned to 256 Meg */
#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
/* aligned to 64 Meg */
#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
/* aligned to 256 Meg */
#define DEBUG_BASE 0x08000000 /* debug board */
#define NAND_BASE 0x30000000 /* NAND addr */
/* (actual size small port) */
#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
#define ONENAND_MAP 0x20000000 /* OneNand addr */
/* (actual size small port) */
/* SMS */
#ifndef __ASSEMBLY__
typedef struct sms {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned char res2[0x34];
unsigned int rg_att0; /* 0x48 */
unsigned char res3[0x84];
unsigned int class_arb0; /* 0xD0 */
} sms_t;
#endif /* __ASSEMBLY__ */
#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
/* SDRC */
#ifndef __ASSEMBLY__
typedef struct sdrc_cs {
unsigned int mcfg; /* 0x80 || 0xB0 */
unsigned int mr; /* 0x84 || 0xB4 */
unsigned char res1[0x4];
unsigned int emr2; /* 0x8C || 0xBC */
unsigned char res2[0x14];
unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
unsigned int manual; /* 0xA8 || 0xD8 */
unsigned char res3[0x4];
} sdrc_cs_t;
typedef struct sdrc_actim {
unsigned int ctrla; /* 0x9C || 0xC4 */
unsigned int ctrlb; /* 0xA0 || 0xC8 */
} sdrc_actim_t;
typedef struct sdrc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int status; /* 0x14 */
unsigned char res2[0x28];
unsigned int cs_cfg; /* 0x40 */
unsigned int sharing; /* 0x44 */
unsigned char res3[0x18];
unsigned int dlla_ctrl; /* 0x60 */
unsigned int dlla_status; /* 0x64 */
unsigned int dllb_ctrl; /* 0x68 */
unsigned int dllb_status; /* 0x6C */
unsigned int power; /* 0x70 */
unsigned char res4[0xC];
sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
} sdrc_t;
#endif /* __ASSEMBLY__ */
#define DLLPHASE_90 (0x1 << 1)
#define LOADDLL (0x1 << 2)
#define ENADLL (0x1 << 3)
#define DLL_DELAY_MASK 0xFF00
#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)
#define DEEPPD (0x1 << 3)
#define B32NOT16 (0x1 << 4)
#define BANKALLOCATION (0x2 << 6)
#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
#define ADDRMUXLEGACY (0x1 << 19)
#define CASWIDTH_10BITS (0x5 << 20)
#define RASWIDTH_13BITS (0x2 << 24)
#define BURSTLENGTH4 (0x2 << 0)
#define CASL3 (0x3 << 4)
#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
#define ARE_ARCV_1 (0x1 << 0)
#define ARCV (0x4e2 << 8) /* Autorefresh count */
#define OMAP34XX_SDRC_CS0 0x80000000
#define OMAP34XX_SDRC_CS1 0xA0000000
#define CMD_NOP 0x0
#define CMD_PRECHARGE 0x1
#define CMD_AUTOREFRESH 0x2
#define CMD_ENTR_PWRDOWN 0x3
#define CMD_EXIT_PWRDOWN 0x4
#define CMD_ENTR_SRFRSH 0x5
#define CMD_CKE_HIGH 0x6
#define CMD_CKE_LOW 0x7
#define SOFTRESET (0x1 << 1)
#define SMART_IDLE (0x2 << 3)
#define REF_ON_IDLE (0x1 << 6)
/* timer regs offsets (32 bit regs) */
#ifndef __ASSEMBLY__
typedef struct gptimer {
unsigned int tidr; /* 0x00 r */
unsigned char res[0xc];
unsigned int tiocp_cfg; /* 0x10 rw */
unsigned int tistat; /* 0x14 r */
unsigned int tisr; /* 0x18 rw */
unsigned int tier; /* 0x1c rw */
unsigned int twer; /* 0x20 rw */
unsigned int tclr; /* 0x24 rw */
unsigned int tcrr; /* 0x28 rw */
unsigned int tldr; /* 0x2c rw */
unsigned int ttgr; /* 0x30 rw */
unsigned int twpc; /* 0x34 r*/
unsigned int tmar; /* 0x38 rw*/
unsigned int tcar1; /* 0x3c r */
unsigned int tcicr; /* 0x40 rw */
unsigned int tcar2; /* 0x44 r */
} gptimer_t;
#endif /* __ASSEMBLY__ */
/* enable sys_clk NO-prescale /1 */
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
/* Watchdog */
#ifndef __ASSEMBLY__
typedef struct watchdog {
unsigned char res1[0x34];
unsigned int wwps; /* 0x34 r */
unsigned char res2[0x10];
unsigned int wspr; /* 0x48 rw */
} watchdog_t;
#endif /* __ASSEMBLY__ */
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
/* PRCM */
#define PRCM_BASE 0x48004000
#ifndef __ASSEMBLY__
typedef struct prcm {
unsigned int fclken_iva2; /* 0x00 */
unsigned int clken_pll_iva2; /* 0x04 */
unsigned char res1[0x1c];
unsigned int idlest_pll_iva2; /* 0x24 */
unsigned char res2[0x18];
unsigned int clksel1_pll_iva2 ; /* 0x40 */
unsigned int clksel2_pll_iva2; /* 0x44 */
unsigned char res3[0x8bc];
unsigned int clken_pll_mpu; /* 0x904 */
unsigned char res4[0x1c];
unsigned int idlest_pll_mpu; /* 0x924 */
unsigned char res5[0x18];
unsigned int clksel1_pll_mpu; /* 0x940 */
unsigned int clksel2_pll_mpu; /* 0x944 */
unsigned char res6[0xb8];
unsigned int fclken1_core; /* 0xa00 */
unsigned char res7[0xc];
unsigned int iclken1_core; /* 0xa10 */
unsigned int iclken2_core; /* 0xa14 */
unsigned char res8[0x28];
unsigned int clksel_core; /* 0xa40 */
unsigned char res9[0xbc];
unsigned int fclken_gfx; /* 0xb00 */
unsigned char res10[0xc];
unsigned int iclken_gfx; /* 0xb10 */
unsigned char res11[0x2c];
unsigned int clksel_gfx; /* 0xb40 */
unsigned char res12[0xbc];
unsigned int fclken_wkup; /* 0xc00 */
unsigned char res13[0xc];
unsigned int iclken_wkup; /* 0xc10 */
unsigned char res14[0xc];
unsigned int idlest_wkup; /* 0xc20 */
unsigned char res15[0x1c];
unsigned int clksel_wkup; /* 0xc40 */
unsigned char res16[0xbc];
unsigned int clken_pll; /* 0xd00 */
unsigned char res17[0x1c];
unsigned int idlest_ckgen; /* 0xd20 */
unsigned char res18[0x1c];
unsigned int clksel1_pll; /* 0xd40 */
unsigned int clksel2_pll; /* 0xd44 */
unsigned int clksel3_pll; /* 0xd48 */
unsigned char res19[0xb4];
unsigned int fclken_dss; /* 0xe00 */
unsigned char res20[0xc];
unsigned int iclken_dss; /* 0xe10 */
unsigned char res21[0x2c];
unsigned int clksel_dss; /* 0xe40 */
unsigned char res22[0xbc];
unsigned int fclken_cam; /* 0xf00 */
unsigned char res23[0xc];
unsigned int iclken_cam; /* 0xf10 */
unsigned char res24[0x2c];
unsigned int clksel_cam; /* 0xf40 */
unsigned char res25[0xbc];
unsigned int fclken_per; /* 0x1000 */
unsigned char res26[0xc];
unsigned int iclken_per; /* 0x1010 */
unsigned char res27[0x2c];
unsigned int clksel_per; /* 0x1040 */
unsigned char res28[0xfc];
unsigned int clksel1_emu; /* 0x1140 */
} prcm_t;
#else /* __ASSEMBLY__ */
#define CM_CLKSEL_CORE 0x48004a40
#define CM_CLKSEL_GFX 0x48004b40
#define CM_CLKSEL_WKUP 0x48004c40
#define CM_CLKEN_PLL 0x48004d00
#define CM_CLKSEL1_PLL 0x48004d40
#define CM_CLKSEL1_EMU 0x48005140
#endif /* __ASSEMBLY__ */
#define PRM_BASE 0x48306000
#ifndef __ASSEMBLY__
typedef struct prm {
unsigned char res1[0xd40];
unsigned int clksel; /* 0xd40 */
unsigned char res2[0x50c];
unsigned int rstctrl; /* 0x1250 */
unsigned char res3[0x1c];
unsigned int clksrc_ctrl; /* 0x1270 */
} prm_t;
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL 0x48307250
#endif /* __ASSEMBLY__ */
#define SYSCLKDIV_1 (0x1 << 6)
#define SYSCLKDIV_2 (0x1 << 7)
#define CLKSEL_GPT1 (0x1 << 0)
#define EN_GPT1 (0x1 << 0)
#define EN_32KSYNC (0x1 << 2)
#define ST_WDT2 (0x1 << 5)
#define ST_MPU_CLK (0x1 << 0)
#define ST_CORE_CLK (0x1 << 0)
#define ST_PERIPH_CLK (0x1 << 1)
#define ST_IVA2_CLK (0x1 << 0)
#define RESETDONE (0x1 << 0)
#define TCLR_ST (0x1 << 0)
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/* SMX-APE */
#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
#ifndef __ASSEMBLY__
typedef struct pm {
unsigned char res1[0x48];
unsigned int req_info_permission_0; /* 0x48 */
unsigned char res2[0x4];
unsigned int read_permission_0; /* 0x50 */
unsigned char res3[0x4];
unsigned int wirte_permission_0; /* 0x58 */
unsigned char res4[0x4];
unsigned int addr_match_1; /* 0x58 */
unsigned char res5[0x4];
unsigned int req_info_permission_1; /* 0x68 */
unsigned char res6[0x14];
unsigned int addr_match_2; /* 0x80 */
} pm_t;
#endif /*__ASSEMBLY__ */
/* Permission values for registers -Full fledged permissions to all */
#define UNLOCK_1 0xFFFFFFFF
#define UNLOCK_2 0x00000000
#define UNLOCK_3 0x0000FFFF
#define NOT_EARLY 0
/* I2C base */
#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
#endif /* _CPU_H */

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/*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _I2C_H_
#define _I2C_H_
#define I2C_DEFAULT_BASE I2C_BASE1
#define I2C_REV (I2C_DEFAULT_BASE + 0x00)
#define I2C_IE (I2C_DEFAULT_BASE + 0x04)
#define I2C_STAT (I2C_DEFAULT_BASE + 0x08)
#define I2C_IV (I2C_DEFAULT_BASE + 0x0c)
#define I2C_BUF (I2C_DEFAULT_BASE + 0x14)
#define I2C_CNT (I2C_DEFAULT_BASE + 0x18)
#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c)
#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20)
#define I2C_CON (I2C_DEFAULT_BASE + 0x24)
#define I2C_OA (I2C_DEFAULT_BASE + 0x28)
#define I2C_SA (I2C_DEFAULT_BASE + 0x2c)
#define I2C_PSC (I2C_DEFAULT_BASE + 0x30)
#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34)
#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38)
#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c)
/* I2C masks */
/* I2C Interrupt Enable Register (I2C_IE): */
#define I2C_IE_GC_IE (1 << 5)
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Status Register (I2C_STAT): */
#define I2C_STAT_SBD (1 << 15) /* Single byte data */
#define I2C_STAT_BB (1 << 12) /* Bus busy */
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
#define I2C_STAT_AAS (1 << 9) /* Address as slave */
#define I2C_STAT_GC (1 << 5)
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Interrupt Code Register (I2C_INTCODE): */
#define I2C_INTCODE_MASK 7
#define I2C_INTCODE_NONE 0
#define I2C_INTCODE_AL 1 /* Arbitration lost */
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
#define I2C_INTCODE_ARDY 3 /* Register access ready */
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
/* I2C Buffer Configuration Register (I2C_BUF): */
#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
/* I2C Configuration Register (I2C_CON): */
#define I2C_CON_EN (1 << 15) /* I2C module enable */
#define I2C_CON_BE (1 << 14) /* Big endian mode */
#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
#define I2C_CON_MST (1 << 10) /* Master/slave mode */
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
/* (master mode only) */
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
/* I2C System Test Register (I2C_SYSTEST): */
#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
#define I2C_SCLL_SCLL 0
#define I2C_SCLL_SCLL_M 0xFF
#define I2C_SCLL_HSSCLL 8
#define I2C_SCLH_HSSCLL_M 0xFF
#define I2C_SCLH_SCLH 0
#define I2C_SCLH_SCLH_M 0xFF
#define I2C_SCLH_HSSCLH 8
#define I2C_SCLH_HSSCLH_M 0xFF
#define OMAP_I2C_STANDARD 100
#define OMAP_I2C_FAST_MODE 400
#define OMAP_I2C_HIGH_SPEED 3400
#define SYSTEM_CLOCK_12 12000
#define SYSTEM_CLOCK_13 13000
#define SYSTEM_CLOCK_192 19200
#define SYSTEM_CLOCK_96 96000
#define I2C_IP_CLK SYSTEM_CLOCK_96
#define I2C_PSC_MAX 0x0f
#define I2C_PSC_MIN 0x00
#endif /* _I2C_H_ */

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/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MEM_H_
#define _MEM_H_
#define CS0 0x0
#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
#ifndef __ASSEMBLY__
typedef enum {
STACKED = 0,
IP_DDR = 1,
COMBO_DDR = 2,
IP_SDR = 3,
} mem_t;
#endif /* __ASSEMBLY__ */
#define EARLY_INIT 1
/* Slower full frequency range default timings for x32 operation*/
#define SDP_SDRC_SHARING 0x00000100
#define SDP_SDRC_MR_0_SDR 0x00000031
/* optimized timings good for current shipping parts */
#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
#define DLL_OFFSET 0
#define DLL_WRITEDDRCLKX2DIS 1
#define DLL_ENADLL 1
#define DLL_LOCKDLL 0
#define DLL_DLLPHASE_72 0
#define DLL_DLLPHASE_90 1
/* rkw - need to find of 90/72 degree recommendation for speed like before */
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
* ACTIMA
* TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
* TDPL (Twr) = 15/6 = 2.5 -> 3
* TRRD = 12/6 = 2
* TRCD = 18/6 = 3
* TRP = 18/6 = 3
* TRAS = 42/6 = 7
* TRC = 60/6 = 10
* TRFC = 72/6 = 12
* ACTIMB
* TCKE = 2
* XSR = 120/6 = 20
*/
#define TDAL_165 6
#define TDPL_165 3
#define TRRD_165 2
#define TRCD_165 3
#define TRP_165 3
#define TRAS_165 7
#define TRC_165 10
#define TRFC_165 21
#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
(TRAS_165 << 18) | (TRP_165 << 15) | \
(TRCD_165 << 12) | (TRRD_165 << 9) | \
(TDPL_165 << 6) | (TDAL_165))
#define TWTR_165 1
#define TCKE_165 1
#define TXP_165 5
#define XSR_165 23
#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
(TXP_165 << 8) | (TWTR_165 << 16))
#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165
#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165
#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
/*
* GPMC settings -
* Definitions is as per the following format
* #define <PART>_GPMC_CONFIG<x> <value>
* Where:
* PART is the part name e.g. STNOR - Intel Strata Flash
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
* Value is corresponding value
*
* For every valid PRCM configuration there should be only one definition of
* the same. if values are independent of the board, this definition will be
* present in this file if values are dependent on the board, then this should
* go into corresponding mem-boardName.h file
*
* Currently valid part Names are (PART):
* STNOR - Intel Strata Flash
* SMNAND - Samsung NAND
* MPDB - H4 MPDB board
* SBNOR - Sibley NOR
* MNAND - Micron Large page x16 NAND
* ONNAND - Samsung One NAND
*
* include/configs/file.h contains the defn - for all CS we are interested
* #define OMAP34XX_GPMC_CSx PART
* #define OMAP34XX_GPMC_CSx_SIZE Size
* #define OMAP34XX_GPMC_CSx_MAP Map
* Where:
* x - CS number
* PART - Part Name as defined above
* SIZE - how big is the mapping to be
* GPMC_SIZE_128M - 0x8
* GPMC_SIZE_64M - 0xC
* GPMC_SIZE_32M - 0xE
* GPMC_SIZE_16M - 0xF
* MAP - Map this CS to which address(GPMC address space)- Absolute address
* >>24 before being used.
*/
#define GPMC_SIZE_128M 0x8
#define GPMC_SIZE_64M 0xC
#define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF
#define SMNAND_GPMC_CONFIG1 0x00000800
#define SMNAND_GPMC_CONFIG2 0x00141400
#define SMNAND_GPMC_CONFIG3 0x00141400
#define SMNAND_GPMC_CONFIG4 0x0F010F01
#define SMNAND_GPMC_CONFIG5 0x010C1414
#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
#define SMNAND_GPMC_CONFIG7 0x00000C44
#define M_NAND_GPMC_CONFIG1 0x00001800
#define M_NAND_GPMC_CONFIG2 0x00141400
#define M_NAND_GPMC_CONFIG3 0x00141400
#define M_NAND_GPMC_CONFIG4 0x0F010F01
#define M_NAND_GPMC_CONFIG5 0x010C1414
#define M_NAND_GPMC_CONFIG6 0x1f0f0A80
#define M_NAND_GPMC_CONFIG7 0x00000C44
#define STNOR_GPMC_CONFIG1 0x3
#define STNOR_GPMC_CONFIG2 0x00151501
#define STNOR_GPMC_CONFIG3 0x00060602
#define STNOR_GPMC_CONFIG4 0x11091109
#define STNOR_GPMC_CONFIG5 0x01141F1F
#define STNOR_GPMC_CONFIG6 0x000004c4
#define SIBNOR_GPMC_CONFIG1 0x1200
#define SIBNOR_GPMC_CONFIG2 0x001f1f00
#define SIBNOR_GPMC_CONFIG3 0x00080802
#define SIBNOR_GPMC_CONFIG4 0x1C091C09
#define SIBNOR_GPMC_CONFIG5 0x01131F1F
#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
#define MPDB_GPMC_CONFIG1 0x00011000
#define MPDB_GPMC_CONFIG2 0x001f1f01
#define MPDB_GPMC_CONFIG3 0x00080803
#define MPDB_GPMC_CONFIG4 0x1c0b1c0a
#define MPDB_GPMC_CONFIG5 0x041f1F1F
#define MPDB_GPMC_CONFIG6 0x1F0F04C4
#define P2_GPMC_CONFIG1 0x0
#define P2_GPMC_CONFIG2 0x0
#define P2_GPMC_CONFIG3 0x0
#define P2_GPMC_CONFIG4 0x0
#define P2_GPMC_CONFIG5 0x0
#define P2_GPMC_CONFIG6 0x0
#define ONENAND_GPMC_CONFIG1 0x00001200
#define ONENAND_GPMC_CONFIG2 0x000F0F01
#define ONENAND_GPMC_CONFIG3 0x00030301
#define ONENAND_GPMC_CONFIG4 0x0F040F04
#define ONENAND_GPMC_CONFIG5 0x010F1010
#define ONENAND_GPMC_CONFIG6 0x1F060000
#define NET_GPMC_CONFIG1 0x00001000
#define NET_GPMC_CONFIG2 0x001e1e01
#define NET_GPMC_CONFIG3 0x00080300
#define NET_GPMC_CONFIG4 0x1c091c09
#define NET_GPMC_CONFIG5 0x04181f1f
#define NET_GPMC_CONFIG6 0x00000FCF
#define NET_GPMC_CONFIG7 0x00000f6c
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#define PISMO1_NOR 1
#define PISMO1_NAND 2
#define PISMO2_CS0 3
#define PISMO2_CS1 4
#define PISMO1_ONENAND 5
#define DBG_MPDB 6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
/* make it readable for the gpmc_init */
#define PISMO1_NOR_BASE FLASH_BASE
#define PISMO1_NAND_BASE NAND_BASE
#define PISMO2_CS0_BASE PISMO2_MAP1
#define PISMO1_ONEN_BASE ONENAND_MAP
#define DBG_MPDB_BASE DEBUG_BASE
#endif /* endif _MEM_H_ */

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/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MMC_H
#define MMC_H
#include "mmc_host_def.h"
/* Responses */
#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
/* All supported commands */
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
#define MMC_DSR_DEFAULT 0x0404
#define SD_CMD8_CHECK_PATTERN 0xAA
#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
/* Clock Configurations and Macros */
#define MMC_CLOCK_REFERENCE 96
#define MMC_RELATIVE_CARD_ADDRESS 0x1234
#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1)
#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF
#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F
#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16
#define MMC_CSD_C_SIZE_LSB_MASK 0x0003
#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF
#define MMC_CSD_C_SIZE_MSB_OFFSET 2
#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
typedef struct {
unsigned not_used:1;
unsigned crc:7;
unsigned ecc:2;
unsigned file_format:2;
unsigned tmp_write_protect:1;
unsigned perm_write_protect:1;
unsigned copy:1;
unsigned file_format_grp:1;
unsigned content_prot_app:1;
unsigned reserved_1:4;
unsigned write_bl_partial:1;
unsigned write_bl_len:4;
unsigned r2w_factor:3;
unsigned default_ecc:2;
unsigned wp_grp_enable:1;
unsigned wp_grp_size:5;
unsigned erase_grp_mult:5;
unsigned erase_grp_size:5;
unsigned c_size_mult:3;
unsigned vdd_w_curr_max:3;
unsigned vdd_w_curr_min:3;
unsigned vdd_r_curr_max:3;
unsigned vdd_r_curr_min:3;
unsigned c_size_lsb:2;
unsigned c_size_msb:10;
unsigned reserved_2:2;
unsigned dsr_imp:1;
unsigned read_blk_misalign:1;
unsigned write_blk_misalign:1;
unsigned read_bl_partial:1;
unsigned read_bl_len:4;
unsigned ccc:12;
unsigned tran_speed:8;
unsigned nsac:8;
unsigned taac:8;
unsigned reserved_3:2;
unsigned spec_vers:4;
unsigned csd_structure:2;
} mmc_csd_reg_t;
/* csd for sd2.0 */
typedef struct {
unsigned not_used:1;
unsigned crc:7;
unsigned reserved_1:2;
unsigned file_format:2;
unsigned tmp_write_protect:1;
unsigned perm_write_protect:1;
unsigned copy:1;
unsigned file_format_grp:1;
unsigned reserved_2:5;
unsigned write_bl_partial:1;
unsigned write_bl_len:4;
unsigned r2w_factor:3;
unsigned reserved_3:2;
unsigned wp_grp_enable:1;
unsigned wp_grp_size:7;
unsigned sector_size:7;
unsigned erase_blk_len:1;
unsigned reserved_4:1;
unsigned c_size_lsb:16;
unsigned c_size_msb:6;
unsigned reserved_5:6;
unsigned dsr_imp:1;
unsigned read_blk_misalign:1;
unsigned write_blk_misalign:1;
unsigned read_bl_partial:1;
unsigned read_bl_len:4;
unsigned ccc:12;
unsigned tran_speed:8;
unsigned nsac:8;
unsigned taac:8;
unsigned reserved_6:6;
unsigned csd_structure:2;
} mmc_sd2_csd_reg_t;
/* extended csd - 512 bytes long */
typedef struct {
unsigned char reserved_1[181];
unsigned char erasedmemorycontent;
unsigned char reserved_2;
unsigned char buswidthmode;
unsigned char reserved_3;
unsigned char highspeedinterfacetiming;
unsigned char reserved_4;
unsigned char powerclass;
unsigned char reserved_5;
unsigned char commandsetrevision;
unsigned char reserved_6;
unsigned char commandset;
unsigned char extendedcsdrevision;
unsigned char reserved_7;
unsigned char csdstructureversion;
unsigned char reserved_8;
unsigned char cardtype;
unsigned char reserved_9[3];
unsigned char powerclass_52mhz_1_95v;
unsigned char powerclass_26mhz_1_95v;
unsigned char powerclass_52mhz_3_6v;
unsigned char powerclass_26mhz_3_6v;
unsigned char reserved_10;
unsigned char minreadperf_4b_26mhz;
unsigned char minwriteperf_4b_26mhz;
unsigned char minreadperf_8b_26mhz_4b_52mhz;
unsigned char minwriteperf_8b_26mhz_4b_52mhz;
unsigned char minreadperf_8b_52mhz;
unsigned char minwriteperf_8b_52mhz;
unsigned char reserved_11;
unsigned int sectorcount;
unsigned char reserved_12[288];
unsigned char supportedcommandsets;
unsigned char reserved_13[7];
} mmc_extended_csd_reg_t;
/* mmc sd responce */
typedef struct {
unsigned int ocr;
} mmc_resp_r3;
typedef struct {
unsigned short cardstatus;
unsigned short newpublishedrca;
} mmc_resp_r6;
extern mmc_card_data mmc_dev;
unsigned char mmc_lowlevel_init(void);
unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
unsigned int *response);
unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
unsigned char mmc_set_opendrain(unsigned char state);
unsigned char mmc_read_data(unsigned int *output_buf);
#endif /* MMC_H */

166
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/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010)
#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014)
#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C)
#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104)
#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108)
#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C)
#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110)
#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114)
#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118)
#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C)
#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120)
#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124)
#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128)
#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C)
#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130)
#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134)
#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140)
/* T2 Register definitions */
#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274)
#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520)
/*
* OMAP HS MMC Bit definitions
*/
#define MMC_SOFTRESET (0x1 << 1)
#define RESETDONE (0x1 << 0)
#define NOOPENDRAIN (0x0 << 0)
#define OPENDRAIN (0x1 << 0)
#define OD (0x1 << 0)
#define INIT_NOINIT (0x0 << 1)
#define INIT_INITSTREAM (0x1 << 1)
#define HR_NOHOSTRESP (0x0 << 2)
#define STR_BLOCK (0x0 << 3)
#define MODE_FUNC (0x0 << 4)
#define DW8_1_4BITMODE (0x0 << 5)
#define MIT_CTO (0x0 << 6)
#define CDP_ACTIVEHIGH (0x0 << 7)
#define WPP_ACTIVEHIGH (0x0 << 8)
#define RESERVED_MASK (0x3 << 9)
#define CTPL_MMC_SD (0x0 << 11)
#define BLEN_512BYTESLEN (0x200 << 0)
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define RSP_TYPE_LGHT48 (0x2 << 16)
#define RSP_TYPE_LGHT48B (0x3 << 16)
#define CCCE_NOCHECK (0x0 << 19)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
#define DP_OFFSET (21)
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
#define INDEX_OFFSET (24)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
#define DATI_CMDDIS (0x1 << 1)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define SDVS_3V0 (0x6 << 9)
#define ICE_MASK (0x1 << 0)
#define ICE_STOP (0x0 << 0)
#define ICS_MASK (0x1 << 1)
#define ICS_NOTREADY (0x0 << 1)
#define ICE_OSCILLATE (0x1 << 0)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
#define CLKD_OFFSET (6)
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define SOFTRESETALL (0x1 << 24)
#define CC_MASK (0x1 << 0)
#define TC_MASK (0x1 << 1)
#define BWR_MASK (0x1 << 4)
#define BRR_MASK (0x1 << 5)
#define ERRI_MASK (0x1 << 15)
#define IE_CC (0x01 << 0)
#define IE_TC (0x01 << 1)
#define IE_BWR (0x01 << 4)
#define IE_BRR (0x01 << 5)
#define IE_CTO (0x01 << 16)
#define IE_CCRC (0x01 << 17)
#define IE_CEB (0x01 << 18)
#define IE_CIE (0x01 << 19)
#define IE_DTO (0x01 << 20)
#define IE_DCRC (0x01 << 21)
#define IE_DEB (0x01 << 22)
#define IE_CERR (0x01 << 28)
#define IE_BADA (0x01 << 29)
#define VS30_3V0SUP (1 << 25)
#define VS18_1V8SUP (1 << 26)
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#define MMC_CARD 0
#define SD_CARD 1
#define BYTE_MODE 0
#define SECTOR_MODE 1
#define CLK_INITSEQ 0
#define CLK_400KHZ 1
#define CLK_MISC 2
typedef struct {
unsigned int card_type;
unsigned int version;
unsigned int mode;
unsigned int size;
unsigned int RCA;
} mmc_card_data;
#define mmc_reg_out(addr, mask, val)\
(addr) = (((addr)) & (~(mask))) | ((val) & (mask));
#define mmc_reg_out(addr, mask, val)\
(addr) = (((addr)) & (~(mask))) | ((val) & (mask));
#endif /* MMC_HOST_DEF_H */

412
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/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MUX_H_
#define _MUX_H_
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
*/
#define IEN (1 << 8)
#define IDIS (0 << 8)
#define PTU (1 << 4)
#define PTD (0 << 4)
#define EN (1 << 3)
#define DIS (0 << 3)
#define M0 0
#define M1 1
#define M2 2
#define M3 3
#define M4 4
#define M5 5
#define M6 6
#define M7 7
/*
* To get the actual address the offset has to added
* with OMAP34XX_CTRL_BASE to get the actual address
*/
/*SDRC*/
#define CONTROL_PADCONF_SDRC_D0 0x0030
#define CONTROL_PADCONF_SDRC_D1 0x0032
#define CONTROL_PADCONF_SDRC_D2 0x0034
#define CONTROL_PADCONF_SDRC_D3 0x0036
#define CONTROL_PADCONF_SDRC_D4 0x0038
#define CONTROL_PADCONF_SDRC_D5 0x003A
#define CONTROL_PADCONF_SDRC_D6 0x003C
#define CONTROL_PADCONF_SDRC_D7 0x003E
#define CONTROL_PADCONF_SDRC_D8 0x0040
#define CONTROL_PADCONF_SDRC_D9 0x0042
#define CONTROL_PADCONF_SDRC_D10 0x0044
#define CONTROL_PADCONF_SDRC_D11 0x0046
#define CONTROL_PADCONF_SDRC_D12 0x0048
#define CONTROL_PADCONF_SDRC_D13 0x004A
#define CONTROL_PADCONF_SDRC_D14 0x004C
#define CONTROL_PADCONF_SDRC_D15 0x004E
#define CONTROL_PADCONF_SDRC_D16 0x0050
#define CONTROL_PADCONF_SDRC_D17 0x0052
#define CONTROL_PADCONF_SDRC_D18 0x0054
#define CONTROL_PADCONF_SDRC_D19 0x0056
#define CONTROL_PADCONF_SDRC_D20 0x0058
#define CONTROL_PADCONF_SDRC_D21 0x005A
#define CONTROL_PADCONF_SDRC_D22 0x005C
#define CONTROL_PADCONF_SDRC_D23 0x005E
#define CONTROL_PADCONF_SDRC_D24 0x0060
#define CONTROL_PADCONF_SDRC_D25 0x0062
#define CONTROL_PADCONF_SDRC_D26 0x0064
#define CONTROL_PADCONF_SDRC_D27 0x0066
#define CONTROL_PADCONF_SDRC_D28 0x0068
#define CONTROL_PADCONF_SDRC_D29 0x006A
#define CONTROL_PADCONF_SDRC_D30 0x006C
#define CONTROL_PADCONF_SDRC_D31 0x006E
#define CONTROL_PADCONF_SDRC_CLK 0x0070
#define CONTROL_PADCONF_SDRC_DQS0 0x0072
#define CONTROL_PADCONF_SDRC_DQS1 0x0074
#define CONTROL_PADCONF_SDRC_DQS2 0x0076
#define CONTROL_PADCONF_SDRC_DQS3 0x0078
/*GPMC*/
#define CONTROL_PADCONF_GPMC_A1 0x007A
#define CONTROL_PADCONF_GPMC_A2 0x007C
#define CONTROL_PADCONF_GPMC_A3 0x007E
#define CONTROL_PADCONF_GPMC_A4 0x0080
#define CONTROL_PADCONF_GPMC_A5 0x0082
#define CONTROL_PADCONF_GPMC_A6 0x0084
#define CONTROL_PADCONF_GPMC_A7 0x0086
#define CONTROL_PADCONF_GPMC_A8 0x0088
#define CONTROL_PADCONF_GPMC_A9 0x008A
#define CONTROL_PADCONF_GPMC_A10 0x008C
#define CONTROL_PADCONF_GPMC_D0 0x008E
#define CONTROL_PADCONF_GPMC_D1 0x0090
#define CONTROL_PADCONF_GPMC_D2 0x0092
#define CONTROL_PADCONF_GPMC_D3 0x0094
#define CONTROL_PADCONF_GPMC_D4 0x0096
#define CONTROL_PADCONF_GPMC_D5 0x0098
#define CONTROL_PADCONF_GPMC_D6 0x009A
#define CONTROL_PADCONF_GPMC_D7 0x009C
#define CONTROL_PADCONF_GPMC_D8 0x009E
#define CONTROL_PADCONF_GPMC_D9 0x00A0
#define CONTROL_PADCONF_GPMC_D10 0x00A2
#define CONTROL_PADCONF_GPMC_D11 0x00A4
#define CONTROL_PADCONF_GPMC_D12 0x00A6
#define CONTROL_PADCONF_GPMC_D13 0x00A8
#define CONTROL_PADCONF_GPMC_D14 0x00AA
#define CONTROL_PADCONF_GPMC_D15 0x00AC
#define CONTROL_PADCONF_GPMC_NCS0 0x00AE
#define CONTROL_PADCONF_GPMC_NCS1 0x00B0
#define CONTROL_PADCONF_GPMC_NCS2 0x00B2
#define CONTROL_PADCONF_GPMC_NCS3 0x00B4
#define CONTROL_PADCONF_GPMC_NCS4 0x00B6
#define CONTROL_PADCONF_GPMC_NCS5 0x00B8
#define CONTROL_PADCONF_GPMC_NCS6 0x00BA
#define CONTROL_PADCONF_GPMC_NCS7 0x00BC
#define CONTROL_PADCONF_GPMC_CLK 0x00BE
#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0
#define CONTROL_PADCONF_GPMC_NOE 0x00C2
#define CONTROL_PADCONF_GPMC_NWE 0x00C4
#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6
#define CONTROL_PADCONF_GPMC_NBE1 0x00C8
#define CONTROL_PADCONF_GPMC_NWP 0x00CA
#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC
#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE
#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0
#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2
/*DSS*/
#define CONTROL_PADCONF_DSS_PCLK 0x00D4
#define CONTROL_PADCONF_DSS_HSYNC 0x00D6
#define CONTROL_PADCONF_DSS_VSYNC 0x00D8
#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA
#define CONTROL_PADCONF_DSS_DATA0 0x00DC
#define CONTROL_PADCONF_DSS_DATA1 0x00DE
#define CONTROL_PADCONF_DSS_DATA2 0x00E0
#define CONTROL_PADCONF_DSS_DATA3 0x00E2
#define CONTROL_PADCONF_DSS_DATA4 0x00E4
#define CONTROL_PADCONF_DSS_DATA5 0x00E6
#define CONTROL_PADCONF_DSS_DATA6 0x00E8
#define CONTROL_PADCONF_DSS_DATA7 0x00EA
#define CONTROL_PADCONF_DSS_DATA8 0x00EC
#define CONTROL_PADCONF_DSS_DATA9 0x00EE
#define CONTROL_PADCONF_DSS_DATA10 0x00F0
#define CONTROL_PADCONF_DSS_DATA11 0x00F2
#define CONTROL_PADCONF_DSS_DATA12 0x00F4
#define CONTROL_PADCONF_DSS_DATA13 0x00F6
#define CONTROL_PADCONF_DSS_DATA14 0x00F8
#define CONTROL_PADCONF_DSS_DATA15 0x00FA
#define CONTROL_PADCONF_DSS_DATA16 0x00FC
#define CONTROL_PADCONF_DSS_DATA17 0x00FE
#define CONTROL_PADCONF_DSS_DATA18 0x0100
#define CONTROL_PADCONF_DSS_DATA19 0x0102
#define CONTROL_PADCONF_DSS_DATA20 0x0104
#define CONTROL_PADCONF_DSS_DATA21 0x0106
#define CONTROL_PADCONF_DSS_DATA22 0x0108
#define CONTROL_PADCONF_DSS_DATA23 0x010A
/*CAMERA*/
#define CONTROL_PADCONF_CAM_HS 0x010C
#define CONTROL_PADCONF_CAM_VS 0x010E
#define CONTROL_PADCONF_CAM_XCLKA 0x0110
#define CONTROL_PADCONF_CAM_PCLK 0x0112
#define CONTROL_PADCONF_CAM_FLD 0x0114
#define CONTROL_PADCONF_CAM_D0 0x0116
#define CONTROL_PADCONF_CAM_D1 0x0118
#define CONTROL_PADCONF_CAM_D2 0x011A
#define CONTROL_PADCONF_CAM_D3 0x011C
#define CONTROL_PADCONF_CAM_D4 0x011E
#define CONTROL_PADCONF_CAM_D5 0x0120
#define CONTROL_PADCONF_CAM_D6 0x0122
#define CONTROL_PADCONF_CAM_D7 0x0124
#define CONTROL_PADCONF_CAM_D8 0x0126
#define CONTROL_PADCONF_CAM_D9 0x0128
#define CONTROL_PADCONF_CAM_D10 0x012A
#define CONTROL_PADCONF_CAM_D11 0x012C
#define CONTROL_PADCONF_CAM_XCLKB 0x012E
#define CONTROL_PADCONF_CAM_WEN 0x0130
#define CONTROL_PADCONF_CAM_STROBE 0x0132
#define CONTROL_PADCONF_CSI2_DX0 0x0134
#define CONTROL_PADCONF_CSI2_DY0 0x0136
#define CONTROL_PADCONF_CSI2_DX1 0x0138
#define CONTROL_PADCONF_CSI2_DY1 0x013A
/*Audio Interface */
#define CONTROL_PADCONF_MCBSP2_FSX 0x013C
#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E
#define CONTROL_PADCONF_MCBSP2_DR 0x0140
#define CONTROL_PADCONF_MCBSP2_DX 0x0142
#define CONTROL_PADCONF_MMC1_CLK 0x0144
#define CONTROL_PADCONF_MMC1_CMD 0x0146
#define CONTROL_PADCONF_MMC1_DAT0 0x0148
#define CONTROL_PADCONF_MMC1_DAT1 0x014A
#define CONTROL_PADCONF_MMC1_DAT2 0x014C
#define CONTROL_PADCONF_MMC1_DAT3 0x014E
#define CONTROL_PADCONF_MMC1_DAT4 0x0150
#define CONTROL_PADCONF_MMC1_DAT5 0x0152
#define CONTROL_PADCONF_MMC1_DAT6 0x0154
#define CONTROL_PADCONF_MMC1_DAT7 0x0156
/*Wireless LAN */
#define CONTROL_PADCONF_MMC2_CLK 0x0158
#define CONTROL_PADCONF_MMC2_CMD 0x015A
#define CONTROL_PADCONF_MMC2_DAT0 0x015C
#define CONTROL_PADCONF_MMC2_DAT1 0x015E
#define CONTROL_PADCONF_MMC2_DAT2 0x0160
#define CONTROL_PADCONF_MMC2_DAT3 0x0162
#define CONTROL_PADCONF_MMC2_DAT4 0x0164
#define CONTROL_PADCONF_MMC2_DAT5 0x0166
#define CONTROL_PADCONF_MMC2_DAT6 0x0168
#define CONTROL_PADCONF_MMC2_DAT7 0x016A
/*Bluetooth*/
#define CONTROL_PADCONF_MCBSP3_DX 0x016C
#define CONTROL_PADCONF_MCBSP3_DR 0x016E
#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170
#define CONTROL_PADCONF_MCBSP3_FSX 0x0172
#define CONTROL_PADCONF_UART2_CTS 0x0174
#define CONTROL_PADCONF_UART2_RTS 0x0176
#define CONTROL_PADCONF_UART2_TX 0x0178
#define CONTROL_PADCONF_UART2_RX 0x017A
/*Modem Interface */
#define CONTROL_PADCONF_UART1_TX 0x017C
#define CONTROL_PADCONF_UART1_RTS 0x017E
#define CONTROL_PADCONF_UART1_CTS 0x0180
#define CONTROL_PADCONF_UART1_RX 0x0182
#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184
#define CONTROL_PADCONF_MCBSP4_DR 0x0186
#define CONTROL_PADCONF_MCBSP4_DX 0x0188
#define CONTROL_PADCONF_MCBSP4_FSX 0x018A
#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C
#define CONTROL_PADCONF_MCBSP1_FSR 0x018E
#define CONTROL_PADCONF_MCBSP1_DX 0x0190
#define CONTROL_PADCONF_MCBSP1_DR 0x0192
#define CONTROL_PADCONF_MCBSP_CLKS 0x0194
#define CONTROL_PADCONF_MCBSP1_FSX 0x0196
#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198
/*Serial Interface*/
#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A
#define CONTROL_PADCONF_UART3_RTS_SD 0x019C
#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E
#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0
#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2
#define CONTROL_PADCONF_HSUSB0_STP 0x01A4
#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6
#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8
#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA
#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC
#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE
#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0
#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2
#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4
#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6
#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8
#define CONTROL_PADCONF_I2C1_SCL 0x01BA
#define CONTROL_PADCONF_I2C1_SDA 0x01BC
#define CONTROL_PADCONF_I2C2_SCL 0x01BE
#define CONTROL_PADCONF_I2C2_SDA 0x01C0
#define CONTROL_PADCONF_I2C3_SCL 0x01C2
#define CONTROL_PADCONF_I2C3_SDA 0x01C4
#define CONTROL_PADCONF_I2C4_SCL 0x0A00
#define CONTROL_PADCONF_I2C4_SDA 0x0A02
#define CONTROL_PADCONF_HDQ_SIO 0x01C6
#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8
#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA
#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC
#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE
#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0
#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2
#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4
#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6
#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8
#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA
#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC
#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE
/*Control and debug */
#define CONTROL_PADCONF_SYS_32K 0x0A04
#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06
#define CONTROL_PADCONF_SYS_NIRQ 0x01E0
#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A
#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C
#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E
#define CONTROL_PADCONF_SYS_BOOT3 0x0A10
#define CONTROL_PADCONF_SYS_BOOT4 0x0A12
#define CONTROL_PADCONF_SYS_BOOT5 0x0A14
#define CONTROL_PADCONF_SYS_BOOT6 0x0A16
#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
#define CONTROL_PADCONF_JTAG_TMS 0x0A20
#define CONTROL_PADCONF_JTAG_TDI 0x0A22
#define CONTROL_PADCONF_JTAG_EMU0 0x0A24
#define CONTROL_PADCONF_JTAG_EMU1 0x0A26
#define CONTROL_PADCONF_ETK_CLK 0x0A28
#define CONTROL_PADCONF_ETK_CTL 0x0A2A
#define CONTROL_PADCONF_ETK_D0 0x0A2C
#define CONTROL_PADCONF_ETK_D1 0x0A2E
#define CONTROL_PADCONF_ETK_D2 0x0A30
#define CONTROL_PADCONF_ETK_D3 0x0A32
#define CONTROL_PADCONF_ETK_D4 0x0A34
#define CONTROL_PADCONF_ETK_D5 0x0A36
#define CONTROL_PADCONF_ETK_D6 0x0A38
#define CONTROL_PADCONF_ETK_D7 0x0A3A
#define CONTROL_PADCONF_ETK_D8 0x0A3C
#define CONTROL_PADCONF_ETK_D9 0x0A3E
#define CONTROL_PADCONF_ETK_D10 0x0A40
#define CONTROL_PADCONF_ETK_D11 0x0A42
#define CONTROL_PADCONF_ETK_D12 0x0A44
#define CONTROL_PADCONF_ETK_D13 0x0A46
#define CONTROL_PADCONF_ETK_D14 0x0A48
#define CONTROL_PADCONF_ETK_D15 0x0A4A
#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8
#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA
#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC
#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE
#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0
#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2
#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4
#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6
#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8
#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA
#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC
#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE
#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0
#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2
#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4
#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
/*Die to Die */
#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
#define CONTROL_PADCONF_D2D_MCAD2 0x01E8
#define CONTROL_PADCONF_D2D_MCAD3 0x01EA
#define CONTROL_PADCONF_D2D_MCAD4 0x01EC
#define CONTROL_PADCONF_D2D_MCAD5 0x01EE
#define CONTROL_PADCONF_D2D_MCAD6 0x01F0
#define CONTROL_PADCONF_D2D_MCAD7 0x01F2
#define CONTROL_PADCONF_D2D_MCAD8 0x01F4
#define CONTROL_PADCONF_D2D_MCAD9 0x01F6
#define CONTROL_PADCONF_D2D_MCAD10 0x01F8
#define CONTROL_PADCONF_D2D_MCAD11 0x01FA
#define CONTROL_PADCONF_D2D_MCAD12 0x01FC
#define CONTROL_PADCONF_D2D_MCAD13 0x01FE
#define CONTROL_PADCONF_D2D_MCAD14 0x0200
#define CONTROL_PADCONF_D2D_MCAD15 0x0202
#define CONTROL_PADCONF_D2D_MCAD16 0x0204
#define CONTROL_PADCONF_D2D_MCAD17 0x0206
#define CONTROL_PADCONF_D2D_MCAD18 0x0208
#define CONTROL_PADCONF_D2D_MCAD19 0x020A
#define CONTROL_PADCONF_D2D_MCAD20 0x020C
#define CONTROL_PADCONF_D2D_MCAD21 0x020E
#define CONTROL_PADCONF_D2D_MCAD22 0x0210
#define CONTROL_PADCONF_D2D_MCAD23 0x0212
#define CONTROL_PADCONF_D2D_MCAD24 0x0214
#define CONTROL_PADCONF_D2D_MCAD25 0x0216
#define CONTROL_PADCONF_D2D_MCAD26 0x0218
#define CONTROL_PADCONF_D2D_MCAD27 0x021A
#define CONTROL_PADCONF_D2D_MCAD28 0x021C
#define CONTROL_PADCONF_D2D_MCAD29 0x021E
#define CONTROL_PADCONF_D2D_MCAD30 0x0220
#define CONTROL_PADCONF_D2D_MCAD31 0x0222
#define CONTROL_PADCONF_D2D_MCAD32 0x0224
#define CONTROL_PADCONF_D2D_MCAD33 0x0226
#define CONTROL_PADCONF_D2D_MCAD34 0x0228
#define CONTROL_PADCONF_D2D_MCAD35 0x022A
#define CONTROL_PADCONF_D2D_MCAD36 0x022C
#define CONTROL_PADCONF_D2D_CLK26MI 0x022E
#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230
#define CONTROL_PADCONF_D2D_NRESWARM 0x0232
#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234
#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236
#define CONTROL_PADCONF_D2D_SPINT 0x0238
#define CONTROL_PADCONF_D2D_FRINT 0x023A
#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C
#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E
#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240
#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242
#define CONTROL_PADCONF_D2D_N3GTRST 0x0244
#define CONTROL_PADCONF_D2D_N3GTDI 0x0246
#define CONTROL_PADCONF_D2D_N3GTDO 0x0248
#define CONTROL_PADCONF_D2D_N3GTMS 0x024A
#define CONTROL_PADCONF_D2D_N3GTCK 0x024C
#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E
#define CONTROL_PADCONF_D2D_MSTDBY 0x0250
#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C
#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252
#define CONTROL_PADCONF_D2D_IDLEACK 0x0254
#define CONTROL_PADCONF_D2D_MWRITE 0x0256
#define CONTROL_PADCONF_D2D_SWRITE 0x0258
#define CONTROL_PADCONF_D2D_MREAD 0x025A
#define CONTROL_PADCONF_D2D_SREAD 0x025C
#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E
#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
#define CONTROL_PADCONF_SDRC_CKE0 0x0262
#define CONTROL_PADCONF_SDRC_CKE1 0x0264
#define MUX_VAL(OFFSET,VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
#define CP(x) (CONTROL_PADCONF_##x)
#endif

218
include/asm-arm/arch-omap3/omap3.h Normal file
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@@ -0,0 +1,218 @@
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _OMAP3_H_
#define _OMAP3_H_
/* Stuff on L3 Interconnect */
#define SMX_APE_BASE 0x68000000
/* GPMC */
#define OMAP34XX_GPMC_BASE 0x6E000000
/* SMS */
#define OMAP34XX_SMS_BASE 0x6C000000
/* SDRC */
#define OMAP34XX_SDRC_BASE 0x6D000000
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
#define OMAP34XX_L4_PER 0x49000000
#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
/* CONTROL */
#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
/* UART */
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
/* General Purpose Timers */
#define OMAP34XX_GPT1 0x48318000
#define OMAP34XX_GPT2 0x49032000
#define OMAP34XX_GPT3 0x49034000
#define OMAP34XX_GPT4 0x49036000
#define OMAP34XX_GPT5 0x49038000
#define OMAP34XX_GPT6 0x4903A000
#define OMAP34XX_GPT7 0x4903C000
#define OMAP34XX_GPT8 0x4903E000
#define OMAP34XX_GPT9 0x49040000
#define OMAP34XX_GPT10 0x48086000
#define OMAP34XX_GPT11 0x48088000
#define OMAP34XX_GPT12 0x48304000
/* WatchDog Timers (1 secure, 3 GP) */
#define WD1_BASE 0x4830C000
#define WD2_BASE 0x48314000
#define WD3_BASE 0x49030000
/* 32KTIMER */
#define SYNC_32KTIMER_BASE 0x48320000
#ifndef __ASSEMBLY__
typedef struct s32ktimer {
unsigned char res[0x10];
unsigned int s32k_cr; /* 0x10 */
} s32ktimer_t;
#endif /* __ASSEMBLY__ */
/* OMAP3 GPIO registers */
#define OMAP34XX_GPIO1_BASE 0x48310000
#define OMAP34XX_GPIO2_BASE 0x49050000
#define OMAP34XX_GPIO3_BASE 0x49052000
#define OMAP34XX_GPIO4_BASE 0x49054000
#define OMAP34XX_GPIO5_BASE 0x49056000
#define OMAP34XX_GPIO6_BASE 0x49058000
#ifndef __ASSEMBLY__
typedef struct gpio {
unsigned char res1[0x34];
unsigned int oe; /* 0x34 */
unsigned char res2[0x58];
unsigned int cleardataout; /* 0x90 */
unsigned int setdataout; /* 0x94 */
} gpio_t;
#endif /* __ASSEMBLY__ */
#define GPIO0 (0x1 << 0)
#define GPIO1 (0x1 << 1)
#define GPIO2 (0x1 << 2)
#define GPIO3 (0x1 << 3)
#define GPIO4 (0x1 << 4)
#define GPIO5 (0x1 << 5)
#define GPIO6 (0x1 << 6)
#define GPIO7 (0x1 << 7)
#define GPIO8 (0x1 << 8)
#define GPIO9 (0x1 << 9)
#define GPIO10 (0x1 << 10)
#define GPIO11 (0x1 << 11)
#define GPIO12 (0x1 << 12)
#define GPIO13 (0x1 << 13)
#define GPIO14 (0x1 << 14)
#define GPIO15 (0x1 << 15)
#define GPIO16 (0x1 << 16)
#define GPIO17 (0x1 << 17)
#define GPIO18 (0x1 << 18)
#define GPIO19 (0x1 << 19)
#define GPIO20 (0x1 << 20)
#define GPIO21 (0x1 << 21)
#define GPIO22 (0x1 << 22)
#define GPIO23 (0x1 << 23)
#define GPIO24 (0x1 << 24)
#define GPIO25 (0x1 << 25)
#define GPIO26 (0x1 << 26)
#define GPIO27 (0x1 << 27)
#define GPIO28 (0x1 << 28)
#define GPIO29 (0x1 << 29)
#define GPIO30 (0x1 << 30)
#define GPIO31 (0x1 << 31)
/* base address for indirect vectors (internal boot mode) */
#define SRAM_OFFSET0 0x40000000
#define SRAM_OFFSET1 0x00200000
#define SRAM_OFFSET2 0x0000F800
#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
SRAM_OFFSET2)
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
#define DEBUG_LED1 149 /* gpio */
#define DEBUG_LED2 150 /* gpio */
#define XDR_POP 5 /* package on package part */
#define SDR_DISCRETE 4 /* 128M memory SDR module */
#define DDR_STACKED 3 /* stacked part on 2422 */
#define DDR_COMBO 2 /* combo part on cpu daughter card */
#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
#define DDR_100 100 /* type found on most mem d-boards */
#define DDR_111 111 /* some combo parts */
#define DDR_133 133 /* most combo, some mem d-boards */
#define DDR_165 165 /* future parts */
#define CPU_3430 0x3430
/*
* 343x real hardware:
* ES1 = rev 0
*
* 343x code defines:
* ES1 = 0+1 = 1
* ES1 = 1+1 = 1
*/
#define CPU_3430_ES1 1
#define CPU_3430_ES2 2
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
/* SDP definitions according to FPGA Rev. Is this OK?? */
#define SDP_3430_V1 0x1
#define SDP_3430_V2 0x2
/* EVM definitions */
#define OMAP3EVM_V1 0x1
#define OMAP3EVM_V2 0x2
/* I2C power management companion definitions */
#define PWRMGT_ADDR_ID1 0x48
#define PWRMGT_ADDR_ID2 0x49
#define PWRMGT_ADDR_ID3 0x4A
#define PWRMGT_ADDR_ID4 0x4B
/* I2C ID3 (slave3) register */
#define LEDEN 0xEE
#define LEDAON (0x1 << 0)
#define LEDBON (0x1 << 1)
#define LEDAPWM (0x1 << 4)
#define LEDBPWM (0x1 << 5)
/* I2C ID4 (slave4) register */
#define VAUX2_DEV_GRP 0x76
#define VAUX2_DEDICATED 0x79
#define VAUX3_DEV_GRP 0x7A
#define VAUX3_DEDICATED 0x7D
#define VPLL2_DEV_GRP 0x8E
#define VPLL2_DEDICATED 0x91
#define VDAC_DEV_GRP 0x96
#define VDAC_DEDICATED 0x99
#define DEV_GRP_P1 0x20
#define DEV_GRP_ALL 0xE0
#define VAUX2_VSEL_28 0x09
#define VAUX3_VSEL_28 0x03
#define VPLL2_VSEL_18 0x05
#define VDAC_VSEL_18 0x03
#endif

84
include/asm-arm/arch-omap3/omap_gpmc.h Normal file
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@@ -0,0 +1,84 @@
/*
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
* Rohit Choraria <rohitkc@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
#define ECCCLEAR (0x1 << 8)
#define ECCRESULTREG1 (0x1 << 0)
#define ECCSIZE512BYTE 0xFF
#define ECCSIZE1 (ECCSIZE512BYTE << 22)
#define ECCSIZE0 (ECCSIZE512BYTE << 12)
#define ECCSIZE0SEL (0x000 << 0)
/* Generic ECC Layouts */
/* Large Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
9, 10, 11, 12},\
.oobfree = {\
{.offset = 13,\
.length = 51 } } \
}
#endif
/* Large Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13},\
.oobfree = {\
{.offset = 14,\
.length = 50 } } \
}
#endif
/* Small Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {1, 2, 3},\
.oobfree = {\
{.offset = 4,\
.length = 12 } } \
}
#endif
/* Small Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {2, 3, 4},\
.oobfree = {\
{.offset = 5,\
.length = 11 } } \
}
#endif
#endif /* __ASM_ARCH_OMAP_GPMC_H */

71
include/asm-arm/arch-omap3/sys_proto.h Normal file
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@@ -0,0 +1,71 @@
/*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
typedef struct {
u32 board_type_v1;
u32 board_type_v2;
u32 mtype;
char *cpu_string;
char *board_string;
char *nand_string;
} omap3_sysinfo;
void prcm_init(void);
void per_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
void gpmc_init(void);
void watchdog_init(void);
void set_muxconf_regs(void);
u32 get_cpu_rev(void);
u32 get_mem_type(void);
u32 get_sysboot_value(void);
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);
u32 get_gpmc0_width(void);
u32 get_board_type(void);
void display_board_info(u32);
u32 get_sdr_cs_size(u32);
u32 get_sdr_cs_offset(u32);
u32 is_running_in_sdram(void);
u32 is_running_in_sram(void);
u32 is_running_in_flash(void);
u32 get_device_type(void);
void l2cache_enable(void);
void secureworld_exit(void);
void setup_auxcr(void);
void try_unlock_memory(void);
u32 get_boot_type(void);
void v7_flush_dcache_all(u32);
void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(int);
void power_init_r(void);
#endif

12
include/configs/SX1.h
View File

@@ -116,7 +116,9 @@
#include <configs/omap1510.h>
#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw"
#ifdef CONFIG_STDOUT_USBTTY
#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty"
#endif
/*
* Miscellaneous configurable options
@@ -167,15 +169,19 @@
/*-----------------------------------------------------------------------
* FLASH and environment organization
* V1
* PHYS_FLASH_SIZE_1 (16 << 10) 16 MB
* PHYS_FLASH_SIZE_2 (8 << 10) 8 MB
* V2 only 1 flash
* PHYS_FLASH_SIZE_1 (32 << 10) 32 MB
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define PHYS_FLASH_SIZE (16 << 10) /* 16 MB */
#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE }
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 }
/*-----------------------------------------------------------------------
* FLASH driver setup

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/*
* (C) Copyright 2005
* STMicroelectronics.
* Configuration settings for the STn8815 nomadik board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_ARM926EJS
#define CONFIG_NOMADIK
#define CONFIG_NOMADIK_8815
#define CONFIG_NOMADIK_NDK15
#define CONFIG_NOMADIK_NHK15
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
/* commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
/* At this point there is no flash driver, so remove some commands */
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
/* user interface */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Nomadik> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */
#define CONFIG_SYS_LOADS_BAUD_CHANGE
/* boot config */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"
#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \
" fsload 0x800000 initrd.gz.uimg;" \
" bootm 0x100000 0x800000"
/* memory-related information */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/
#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
# define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
# define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
#endif
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
/* timing informazion */
#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */
#define CONFIG_SYS_TIMERBASE 0x101E2000
#undef CONFIG_SYS_CLKS_IN_HZ
/* serial port (PL011) configuration */
#define CONFIG_PL011_SERIAL
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x101FD000
#define CFG_SERIAL1 0x101FB000
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_PL011_CLOCK 48000000
/* Ethernet */
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_IO_VADDR 0xee000000
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/
#define CONFIG_SMC91111_BASE 0x34000300
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_BOOTFILE "uImage"
/* flash memory and filesystem information */
#define CONFIG_DOS_PARTITION
#define CONFIG_MTD_ONENAND_VERIFY_WRITE
#define CONFIG_SYS_ONENAND_BASE 0x30000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_BOOT_ONENAND
# undef CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */
/* Partition Size Start
* XloaderTOC + X-Loader 256KB 0x00000000
* Memory init function 256KB 0x00040000
* U-Boot 2MB 0x00080000
* Sysimage (kernel + ramdisk) 4MB 0x00280000
* JFFS2 Root filesystem 22MB 0x00680000
* JFFS2 User Data 227.5MB 0x01C80000
*/
# define CONFIG_JFFS2_PART_SIZE 0x400000
# define CONFIG_JFFS2_PART_OFFSET 0x280000
# define CONFIG_ENV_IS_IN_ONENAND
# define CONFIG_ENV_SIZE (256 * 1024)
# define CONFIG_ENV_ADDR 0x30300000
#else /* ! CONFIG_BOOT_ONENAND */
# undef CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */
# define CONFIG_JFFS2_DEV "nand0"
# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/
# define CONFIG_JFFS2_PART_SIZE 0x00300000
# define CONFIG_JFFS2_PART_OFFSET 0x00280000
# define CONFIG_ENV_IS_IN_NAND
# define CONFIG_ENV_SIZE 0x20000 /*128 Kb*/
# define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE)
#endif /* CONFIG_BOOT_ONENAND */
/* Temporarily, until we have no driver, env is not in nand */
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_NOWHERE
/* this is needed to make hello_world.c and other stuff happy */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* base addresses of our peripherals */
#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */
#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */
#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */
#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */
#define NOMADIK_1NAND_BASE 0x30000000
#define NOMADIK_GPIO0_BASE 0x101E4000
#define NOMADIK_GPIO1_BASE 0x101E5000
#define NOMADIK_GPIO2_BASE 0x101E6000
#define NOMADIK_GPIO3_BASE 0x101E7000
#define NOMADIK_CPLD_BASE 0x36000000
#define NOMADIK_UART0_BASE 0x101FD000
#define NOMADIK_UART1_BASE 0x101FB000
#define NOMADIK_UART2_BASE 0x101F2000
#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */
#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */
#define NOMADIK_RTC_BASE 0x101E8000
#define NOMADIK_ETH0_BASE 0x36800300
#define NOMADIK_CPLD_UART_BASE 0x36480000
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2006-2008
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
* Configuration settings for the TI OMAP3530 Beagle board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_MMC 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512
#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS2,115200n8\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"mmcargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define V_PROMPT "OMAP3 beagleboard.org # "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
/*
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define V_PVT 7
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2006-2008
* Texas Instruments.
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* Manikandan Pillai <mani.pillai@ti.com>
*
* Configuration settings for the TI OMAP3 EVM board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_EVM 1 /* working with EVM */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_MMC 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_ONENAND /* ONENAND support */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access */
/* nand at CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define SECTORSIZE 512
#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS2,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"onenand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define V_PROMPT "OMAP3_EVM # "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */
/* in Hz */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
/*
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define V_PVT 7
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_ONENAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR boot_flash_env_addr
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)
/*----------------------------------------------------------------------------
* SMSC9115 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_SMC911X
#define CONFIG_DRIVER_SMC911X_32_BIT
#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
/*
* BOOTP fields
*/
#define CONFIG_BOOTP_SUBNETMASK 0x00000001
#define CONFIG_BOOTP_GATEWAY 0x00000002
#define CONFIG_BOOTP_HOSTNAME 0x00000004
#define CONFIG_BOOTP_BOOTPATH 0x00000010
#endif /* __CONFIG_H */

318
include/configs/omap3_overo.h Normal file
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/*
* Configuration settings for the Gumstix Overo board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_OVERO 1 /* working with overo */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
#define CONFIG_MMC 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512
#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 5
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS2,115200n8\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"mmcargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define V_PROMPT "Overo # "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */
/* in Hz */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
/*
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define V_PVT 7
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)
#endif /* __CONFIG_H */

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include/configs/omap3_pandora.h Normal file
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/*
* (C) Copyright 2008
* Grazvydas Ignotas <notasas@gmail.com>
*
* Configuration settings for the OMAP3 Pandora.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
#define CONFIG_MMC 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512
#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS0,115200n8\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"mmcargs=setenv bootargs console=${console} " \
"video=${videospec} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"video=${videospec} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define V_PROMPT "Pandora # "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */
/* in Hz */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
/*
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define V_PVT 7
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2006-2008
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
* Nishanth Menon <nm@ti.com>
*
* Configuration settings for the TI OMAP3430 Zoom MDK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_MMC 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512
#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS2,115200n8\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"mmcargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define V_PROMPT "OMAP3 Zoom1# "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
/*
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define V_PVT 7
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE boot_flash_base
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
#define CONFIG_ENV_OFFSET boot_flash_off
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)
#endif /* __CONFIG_H */