The patch adds new POST tests for the Lwmon5 board.
These are: * External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
This commit is contained in:
Yuri Tikhonov
committed by
Wolfgang Denk
Wolfgang Denk
parent
8dc3b2303d
commit
65b20dcefc
@@ -86,6 +86,15 @@
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#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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/* unused GPT0 COMP reg */
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/* Additional registers for watchdog timer post test */
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#define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5)
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#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP4)
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#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5)
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#define CFG_WATCHDOG_MAGIC 0x12480000
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#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
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#define CFG_DSPIC_TEST_MASK 0x00000001
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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@@ -156,7 +165,81 @@
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CFG_POST_MEMORY | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_UART)
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CFG_POST_UART | \
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CFG_POST_SYSMON | \
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CFG_POST_WATCHDOG | \
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CFG_POST_DSP | \
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CFG_POST_BSPEC1 | \
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CFG_POST_BSPEC2 | \
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CFG_POST_BSPEC3 | \
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CFG_POST_BSPEC4 | \
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CFG_POST_BSPEC5)
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#define CONFIG_POST_WATCHDOG {\
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"Watchdog timer test", \
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"watchdog", \
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"This test checks the watchdog timer.", \
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POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
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&lwmon5_watchdog_post_test, \
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NULL, \
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NULL, \
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CFG_POST_WATCHDOG \
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}
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#define CONFIG_POST_BSPEC1 {\
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"dsPIC init test", \
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"dspic_init", \
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"This test returns result of dsPIC READY test run earlier.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_init_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC1 \
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}
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#define CONFIG_POST_BSPEC2 {\
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"dsPIC test", \
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"dspic", \
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"This test gets result of dsPIC POST and dsPIC version.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC2 \
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}
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#define CONFIG_POST_BSPEC3 {\
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"FPGA test", \
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"fpga", \
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"This test checks FPGA registers and memory.", \
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POST_RAM | POST_ALWAYS, \
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&fpga_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC3 \
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}
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#define CONFIG_POST_BSPEC4 {\
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"GDC test", \
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"gdc", \
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"This test checks GDC registers and memory.", \
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POST_RAM | POST_ALWAYS, \
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&gdc_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC4 \
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}
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#define CONFIG_POST_BSPEC5 {\
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"SYSMON1 test", \
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"sysmon1", \
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"This test checks GPIO_62_EPX pin indicating power failure.", \
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POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
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&sysmon1_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC5 \
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}
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#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
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#define CONFIG_LOGBUFFER
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@@ -181,6 +264,7 @@
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#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
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#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
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#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
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#define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
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#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
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#if 0
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@@ -366,9 +450,6 @@
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* ToDo: Watchdog is not test fully, so exclude it for now
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*/
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#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
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#define CONFIG_WD_PERIOD 40000 /* in usec */
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@@ -431,10 +512,13 @@
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#define CFG_GPIO_PHY1_RST 12
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#define CFG_GPIO_FLASH_WP 14
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#define CFG_GPIO_PHY0_RST 22
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#define CFG_GPIO_DSPIC_READY 51
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#define CFG_GPIO_EEPROM_EXT_WP 55
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#define CFG_GPIO_HIGHSIDE 56
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#define CFG_GPIO_EEPROM_INT_WP 57
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#define CFG_GPIO_LIME_S 59
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#define CFG_GPIO_LIME_RST 60
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#define CFG_GPIO_SYSMON_STATUS 62
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#define CFG_GPIO_WATCHDOG 63
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/*-----------------------------------------------------------------------
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@@ -93,6 +93,11 @@ extern int post_hotkeys_pressed(void);
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#define CFG_POST_CODEC 0x00002000
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#define CFG_POST_FPU 0x00004000
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#define CFG_POST_ECC 0x00008000
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#define CFG_POST_BSPEC1 0x00010000
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#define CFG_POST_BSPEC2 0x00020000
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#define CFG_POST_BSPEC3 0x00040000
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#define CFG_POST_BSPEC4 0x00080000
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#define CFG_POST_BSPEC5 0x00100000
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#endif /* CONFIG_POST */
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@@ -1431,6 +1431,9 @@
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#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
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#define GPT0_COMP6 0x00000098
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#define GPT0_COMP5 0x00000094
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#define GPT0_COMP4 0x00000090
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#define GPT0_COMP3 0x0000008C
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_USB2D0CR 0x0320
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