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Merge with /home/stefan/git/u-boot/denx

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This commit is contained in:
Stefan Roese
2006-09-18 10:48:03 +02:00
parent 899620c2d6 854bc8da75
commit 64cd52efd1
476 changed files with 11273 additions and 7529 deletions
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2
include/405_mal.h
View File

@@ -92,7 +92,7 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
#ifdef CONFIG_440SPE
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020

3
include/440_i2c.h
View File

@@ -1,7 +1,8 @@
#ifndef _440_i2c_h_
#define _440_i2c_h_
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)

3
include/_exports.h
View File

@@ -12,6 +12,9 @@ EXPORT_FUNC(udelay)
EXPORT_FUNC(get_timer)
EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
EXPORT_FUNC(getenv)
EXPORT_FUNC(setenv)
EXPORT_FUNC(simple_strtoul)
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)

4
include/asm-ppc/processor.h
View File

@@ -728,6 +728,10 @@
#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
#define PVR_440GRX1_RA 0x216218D8 /* 440GRX rev A with Security / Kasumi */
#define PVR_440GRX2_RA 0x216218DC /* 440GRX rev A without Security / Kasumi */
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892

3
include/asm-ppc/u-boot.h
View File

@@ -108,7 +108,8 @@ typedef struct bd_info {
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif

8
include/common.h
View File

@@ -109,6 +109,12 @@ typedef volatile unsigned char vu_char;
#define debugX(level,fmt,args...)
#endif /* DEBUG */
#define BUG() do { \
printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
panic("BUG!"); \
} while (0)
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
typedef void (interrupt_handler_t)(void *);
#include <asm/u-boot.h> /* boot information for Linux kernel */
@@ -603,7 +609,7 @@ void show_boot_progress (int status);
#endif
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is depracted!
#error CONFIG_INIT_CRITICAL is deprecated!
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif

3
include/configs/CPCI440.h
View File

@@ -31,7 +31,8 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_EBONY 1 /* Board is ebony */
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */

2
include/configs/CPU87.h
View File

@@ -527,7 +527,7 @@
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
/*
* Init Memory Controller:
*

55
include/configs/TQM5200.h
View File

@@ -37,7 +37,8 @@
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
/* On a Cameron or on a FO300 board or ... */
#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
#endif
@@ -58,6 +59,20 @@
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_FO300
#define CFG_DEVICE_NULLDEV 1 /* enable null device */
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
#if 0
#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
/* switch is closed */
#endif
#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
/* switch is open */
#endif /* CONFIG_FO300 */
#ifdef CONFIG_STK52XX
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
@@ -105,12 +120,18 @@
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#ifndef CONFIG_FO300
#define CONFIG_CONSOLE_EXTRA_INFO
#else
#define CONFIG_VIDEO_BMP_LOGO
#endif
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
#endif
#endif /* #ifndef CONFIG_TQM5200S */
#ifdef CONFIG_VIDEO
#define ADD_BMP_CMD CFG_CMD_BMP
@@ -124,7 +145,7 @@
#define CONFIG_ISO_PARTITION
/* USB */
#ifdef CONFIG_STK52XX
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
@@ -148,7 +169,7 @@
#endif
/* IDE */
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
#else
#define ADD_IDE_CMD 0
@@ -224,6 +245,12 @@
"erase FC000000 FC03FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC03FFFF\0"
#elif defined (CONFIG_FO300)
# define ENV_UPDT \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0"
#else
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
@@ -378,6 +405,13 @@
"2m(initrd)," \
"8m(misc)," \
"16m(big-fs)"
#elif defined (CONFIG_FO300)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"8m(misc)," \
"16m(big-fs)"
#else
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
@@ -450,15 +484,18 @@
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
* Use for REV200 STK52XX boards. Do not use with REV100 modules
* (because, there I2C1 is used as I2C bus)
* Use for REV200 STK52XX boards and FO300 boards. Do not use
* with REV100 modules (because, there I2C1 is used as I2C bus)
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
* 000 -> All PSC2 pins are GIOPs
* 001 -> CAN1/2 on PSC2 pins
* Use for REV100 STK52xx boards
* 01x -> Use AC97
* use PSC3: Bits 20-23 (mask: 0x00000f00)
* 1100 -> UART/SPI (on FO300 board)
* use PSC6:
* on STK52xx:
* on STK52xx and FO300:
* use as UART. Pins PSC6_0 to PSC6_3 are used.
* Bits 9:11 (mask: 0x00700000):
* 101 -> PSC6 : Extended POST test is not available
@@ -480,6 +517,8 @@
# define CFG_GPS_PORT_CONFIG 0x91500004
# endif
# endif
#elif defined (CONFIG_FO300)
# define CFG_GPS_PORT_CONFIG 0x91502c24
#else /* TMQ5200 Inbetriebnahme-Board */
# define CFG_GPS_PORT_CONFIG 0x81000004
#endif

19
include/configs/TQM834x.h
View File

@@ -422,9 +422,9 @@ extern int tqm834x_num_flash_banks;
#define CFG_SICRL SICRL_LDP_A
/* i-cache and d-cache disabled */
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 0x000000000
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
/* DDR 0 - 512M */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -437,12 +437,21 @@ extern int tqm834x_num_flash_banks;
#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
/* PCI */
#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#ifdef CONFIG_PCI
#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
#else
#define CFG_IBAT3L (0)
#define CFG_IBAT3U (0)
#define CFG_IBAT4L (0)
#define CFG_IBAT4U (0)
#define CFG_IBAT5L (0)
#define CFG_IBAT5U (0)
#endif
/* IMMRBAR */
#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)

1
include/configs/bamboo.h
View File

@@ -73,6 +73,7 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */

125
include/configs/mcc200.h
View File

@@ -37,12 +37,12 @@
#define CONFIG_MISC_INIT_R
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
@@ -51,16 +51,36 @@
* To select console on the one of 8 external UARTs,
* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
* or as 5, 6, 7, or 8 for the second Quad UART.
* COM11, COM12, COM13, COM14 are located on the second Quad UART.
*
* CONFIG_PSC_CONSOLE must be undefined in this case.
*/
/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#ifdef CONFIG_CONSOLE_COM12
#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
#else
#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
#endif
#else
/* PRS200 configuration: */
#undef CONFIG_QUART_CONSOLE
#endif /* CONFIG_PRS200 */
/*
* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
* and undefine CONFIG_QUART_CONSOLE.
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#endif
#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
!defined(CONFIG_SERIAL_MULTI)
#error "Select only one console device!"
#endif
#define CONFIG_BAUDRATE 115200
@@ -72,7 +92,7 @@
/* USB */
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/*
@@ -98,33 +118,46 @@
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
#ifdef CONFIG_PRS200
# define CFG__BOARDNAME "prs200"
# define CFG__LINUX_CONSOLE "ttyS0"
#else
# define CFG__BOARDNAME "mcc200"
# define CFG__LINUX_CONSOLE "ttyEU7"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=mcc200\0" \
"hostname=" CFG__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console},${baudrate}\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"net_nfs=tftp 200000 ${bootfile};" \
"run nfsargs addip addcons;bootm\0" \
"console=" CFG__LINUX_CONSOLE "\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/mcc200/uImage\0" \
"baudrate=115200\0" \
"load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \
"update=protect off FFF00000 +${filesize};" \
"era FFF00000 +${filesize};" \
"cp.b 200000 FFF00000 ${filesize}\0" \
"serverip=192.168.1.1\0" \
"ipaddr=192.168.133.144\0" \
"netmask=255.255.0.0\0" \
"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
"text_base=" MK_STR(TEXT_BASE) "\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
"cp.b 200000 ${text_base} ${filesize}\0" \
"unlock=yes\0" \
"ethaddr=00:02:44:7D:73:3B\0" \
""
#undef MK_STR
#undef XMK_STR
#define CONFIG_BOOTCOMMAND "run flash_self"
@@ -134,7 +167,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
/*
* I2C configuration
@@ -150,9 +183,9 @@
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
* 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
* 0xFE000000 for 32 MB
* 0xFF000000 for 16 MB
* 0xFF800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfc000000
#define CFG_FLASH_SIZE 0x04000000
@@ -174,9 +207,9 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -206,7 +239,7 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
@@ -225,28 +258,46 @@
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 1
/*
* LCD Splash Screen
*/
#if !defined(CONFIG_PRS200)
#define CONFIG_LCD 1
#endif
#if defined(CONFIG_LCD)
#define CONFIG_SPLASH_SCREEN 1
#define CFG_CONSOLE_IS_IN_ENV 1
#define LCD_BPP LCD_MONOCHROME
#endif
/*
* GPIO configuration
*/
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
#if defined(CONFIG_LCD)
/* set PSC2 in UART mode */
#define CFG_GPS_PORT_CONFIG 0x00000044
#else
#define CFG_GPS_PORT_CONFIG 0x00000004
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
@@ -309,7 +360,7 @@
* One of four SC16C554 UARTs is selected with
* A3-A4 (DA5-DA6) lines.
*/
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)

1
include/configs/pcs440ep.h
View File

@@ -63,6 +63,7 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/

429
include/configs/sequoia.h Normal file
View File

@@ -0,0 +1,429 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* sequoia.h - configuration for Sequoia board (PowerPC440EPx)
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
#ifndef CONFIG_RAINIER
#define CONFIG_SEQUOIA 1 /* Board is Sequoia */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#else
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_USB2D0_BASE 0xe0000100
#define CFG_USB_DEVICE 0xe0000000
#define CFG_USB_HOST 0xe0000400
#define CFG_BCSR_BASE 0xc0000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE CFG_NAND_ADDR
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#ifdef CFG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=sequoia\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/sequoia/uImage\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE180000\0" \
"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 1
/* USB */
#ifdef CONFIG_440EPX
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
#define CMD_USB CFG_CMD_USB
#else
#define CMD_USB 0 /* no USB on 440GRx */
#endif /* CONFIG_440EPX */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DTT | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CMD_USB)
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_NAND 0xD0000000
#define CFG_CPLD 0xC0000000
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
#else
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 3 (NOR-FLASH) initialization */
#define CFG_EBC_PB3AP 0x03017300
#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000)
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CFG_EBC_PB0AP 0x018003c0
#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000)
#endif
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x24814580
#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000)
/*-----------------------------------------------------------------------
* Cache Configuration
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

1
include/configs/sorcery.h
View File

@@ -261,6 +261,7 @@
#define CONFIG_MPC8220_FEC 1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR 0x1F
#define CONFIG_MII 1
/*
* Miscellaneous configurable options

3
include/configs/yellowstone.h
View File

@@ -65,6 +65,7 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
@@ -109,6 +110,8 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH

1
include/configs/yosemite.h
View File

@@ -65,6 +65,7 @@
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/

3
include/configs/yucca.h
View File

@@ -31,9 +31,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#undef DEBUG
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/

4
include/environment.h
View File

@@ -79,6 +79,10 @@
# ifdef CFG_ENV_OFFSET_REDUND
# define CFG_REDUNDAND_ENVIRONMENT
# endif
# if defined(CONFIG_NAND_U_BOOT)
/* Use embedded environment in NAND boot versions */
# define ENV_IS_EMBEDDED 1
# endif
#endif /* CFG_ENV_IS_IN_NAND */

5
include/exports.h
View File

@@ -20,6 +20,9 @@ void udelay(unsigned long);
unsigned long get_timer(unsigned long);
void vprintf(const char *, va_list);
void do_reset (void);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
char *getenv (char *name);
void setenv (char *varname, char *varvalue);
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
@@ -37,7 +40,7 @@ enum {
XF_MAX
};
#define XF_VERSION 2
#define XF_VERSION 3
#if defined(CONFIG_I386)
extern gd_t *global_data;

8
include/fat.h
View File

@@ -175,15 +175,19 @@ typedef struct dir_slot {
__u8 name11_12[4]; /* Last 2 characters in name */
} dir_slot;
/* Private filesystem parameters */
/* Private filesystem parameters
*
* Note: FAT buffer has to be 32 bit aligned
* (see FAT32 accesses)
*/
typedef struct {
__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatsize; /* Size of FAT in bits */
__u16 fatlength; /* Length of FAT in sectors */
__u16 fat_sect; /* Starting sector of the FAT */
__u16 rootdir_sect; /* Start sector of root directory */
__u16 clust_size; /* Size of clusters in sectors */
short data_begin; /* The sector of the first cluster, can be negative */
__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatbufnum; /* Used by get_fatent, init to -1 */
} fsdata;

9
include/lcd.h
View File

@@ -148,7 +148,14 @@ typedef struct vidinfo {
extern vidinfo_t panel_info;
#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
#elif defined(CONFIG_MCC200)
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 160) */
ushort vl_row; /* Number of rows (i.e. 100) */
u_char vl_bpix; /* Bits per pixel, 0 = 1 */
} vidinfo_t;
#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
/* Video functions */

2
include/linux/mtd/compat.h
View File

@@ -31,11 +31,13 @@
#define max_t(type,x,y) \
({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
#ifndef BUG
#define BUG() do { \
printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
} while (0)
#define BUG_ON(condition) do { if (condition) BUG(); } while(0)
#endif /* BUG */
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)

67
include/linux/mtd/ndfc.h Normal file
View File

@@ -0,0 +1,67 @@
/*
* linux/include/linux/mtd/ndfc.h
*
* Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Info:
* Contains defines, datastructures for ndfc nand controller
*
*/
#ifndef __LINUX_MTD_NDFC_H
#define __LINUX_MTD_NDFC_H
/* NDFC Register definitions */
#define NDFC_CMD 0x00
#define NDFC_ALE 0x04
#define NDFC_DATA 0x08
#define NDFC_ECC 0x10
#define NDFC_BCFG0 0x30
#define NDFC_BCFG1 0x34
#define NDFC_BCFG2 0x38
#define NDFC_BCFG3 0x3c
#define NDFC_CCR 0x40
#define NDFC_STAT 0x44
#define NDFC_HWCTL 0x48
#define NDFC_REVID 0x50
#define NDFC_STAT_IS_READY 0x01000000
#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
#define NDFC_MAX_BANKS 4
struct ndfc_controller_settings {
uint32_t ccr_settings;
uint64_t ndfc_erpn;
};
struct ndfc_chip_settings {
uint32_t bank_settings;
};
#endif

69
include/mpc5xxx.h
View File

@@ -232,23 +232,92 @@
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
#define NR_IRQS 64
/* IRQ mapping - these are our logical IRQ numbers */
#define MPC5XXX_CRIT_IRQ_NUM 4
#define MPC5XXX_MAIN_IRQ_NUM 17
#define MPC5XXX_SDMA_IRQ_NUM 17
#define MPC5XXX_PERP_IRQ_NUM 23
#define MPC5XXX_CRIT_IRQ_BASE 1
#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
/* General Purpose Timers registers */
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)

609
include/ppc440.h
View File

@@ -82,7 +82,10 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@@ -151,7 +154,18 @@
#define sdr_ecid1 0x0081
#define sdr_ecid2 0x0082
#define sdr_jtag 0x00c0
#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
#define sdr_ddrdl 0x00e0
#else
#define sdr_cfg 0x00e0
#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
#define SDR_CFG_32BITS 0x00000000 /* 32 bits */
#define SDR_CFG_64BITS 0x01000000 /* 64 bits */
#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
#define sdr_ebc 0x0100
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
@@ -180,6 +194,54 @@
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
#define DDR0_00 0x00
#define DDR0_01 0x01
#define DDR0_02 0x02
#define DDR0_03 0x03
#define DDR0_04 0x04
#define DDR0_05 0x05
#define DDR0_06 0x06
#define DDR0_07 0x07
#define DDR0_08 0x08
#define DDR0_09 0x09
#define DDR0_10 0x0A
#define DDR0_11 0x0B
#define DDR0_12 0x0C
#define DDR0_13 0x0D
#define DDR0_14 0x0E
#define DDR0_15 0x0F
#define DDR0_16 0x10
#define DDR0_17 0x11
#define DDR0_18 0x12
#define DDR0_19 0x13
#define DDR0_20 0x14
#define DDR0_21 0x15
#define DDR0_22 0x16
#define DDR0_23 0x17
#define DDR0_24 0x18
#define DDR0_25 0x19
#define DDR0_26 0x1A
#define DDR0_27 0x1B
#define DDR0_28 0x1C
#define DDR0_29 0x1D
#define DDR0_30 0x1E
#define DDR0_31 0x1F
#define DDR0_32 0x20
#define DDR0_33 0x21
#define DDR0_34 0x22
#define DDR0_35 0x23
#define DDR0_36 0x24
#define DDR0_37 0x25
#define DDR0_38 0x26
#define DDR0_39 0x27
#define DDR0_40 0x28
#define DDR0_41 0x29
#define DDR0_42 0x2A
#define DDR0_43 0x2B
#define DDR0_44 0x2C
#endif /*CONFIG_440EPX*/
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
@@ -787,7 +849,8 @@
#define xbcfg 0x23 /* external bus configuration reg */
#define xbcid 0x24 /* external bus core id reg */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* PLB4 to PLB3 Bridge OUT */
#define P4P3_DCR_BASE 0x020
@@ -877,6 +940,7 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
@@ -918,6 +982,178 @@
#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
/* Miscealleneaous Function Reg. */
#define SDR0_MFR 0x4300
#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
#define SDR0_MFR_ERRATA3_EN0 0x00800000
#define SDR0_MFR_ERRATA3_EN1 0x00400000
#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR_USB2D0CR 0x0320
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
/* USB2 Host Control Register */
#define SDR0_USB2H0CR 0x0340
#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
/* Ethernet PLL Configuration Register */
#define SDR0_PFC2 0x4102
#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
/* USB2PHY0 Control Register */
#define SDR0_USB2PHY0CR 0x4103
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
/* Miscealleneaous Function Reg. */
#define SDR0_MFR 0x4300
#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
#define SDR0_MFR_ERRATA3_EN0 0x00800000
#define SDR0_MFR_ERRATA3_EN1 0x00400000
#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
/* CUST0 Customer Configuration Register0 */
#define SDR0_CUST0 0x4000
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
@@ -1007,27 +1243,18 @@
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
/* Miscealleneaous Function Reg. */
#define SDR0_MFR 0x4300
#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
#define SDR0_MFR_ERRATA3_EN0 0x00800000
#define SDR0_MFR_ERRATA3_EN1 0x00400000
#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
/*-----------------------------------------------------------------------------
| Internal SRAM
+----------------------------------------------------------------------------*/
#define ISRAM0_DCR_BASE 0x380
#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
#else
@@ -1121,7 +1348,7 @@
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#if defined(CONFIG_440SPE)
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC2_DCR_BASE 0xe0
#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
@@ -1423,6 +1650,46 @@
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_KRD 0x10000000 /* Kasumi Ready for data */
#define UIC_KDA 0x08000000 /* Kasumi Data Available */
#define UIC_PCRW 0x04000000 /* PCI command register write */
#define UIC_PPM 0x02000000 /* PCI power management */
#define UIC_IIC1 0x01000000 /* IIC */
#define UIC_SPI 0x00800000 /* SPI */
#define UIC_EPCISER 0x00400000 /* External PCI SERR */
#define UIC_MTE 0x00200000 /* MAL TXEOB */
#define UIC_MRE 0x00100000 /* MAL RXEOB */
#define UIC_D0 0x00080000 /* DMA channel 0 */
#define UIC_D1 0x00040000 /* DMA channel 1 */
#define UIC_D2 0x00020000 /* DMA channel 2 */
#define UIC_D3 0x00010000 /* DMA channel 3 */
#define UIC_UD0 0x00008000 /* UDMA irq 0 */
#define UIC_UD1 0x00004000 /* UDMA irq 1 */
#define UIC_UD2 0x00002000 /* UDMA irq 2 */
#define UIC_UD3 0x00001000 /* UDMA irq 3 */
#define UIC_HSB2D 0x00000800 /* USB2.0 Device */
#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
#define UIC_EIP94 0x00000100 /* Security EIP94 */
#define UIC_ETH0 0x00000080 /* Emac 0 */
#define UIC_ETH1 0x00000040 /* Emac 1 */
#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
#define UIC_EIR4 0x00000010 /* External interrupt 4 */
#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
#define UIC_MAL_RXEOB UIC_MRE
#elif !defined(CONFIG_440SPE)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
@@ -1531,6 +1798,48 @@
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_U2 0x10000000 /* UART 2 */
#define UIC_U3 0x08000000 /* UART 3 */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_NDFC 0x02000000 /* NDFC */
#define UIC_KSLE 0x01000000 /* KASUMI slave error */
#define UIC_CT5 0x00800000 /* GPT compare timer 5 */
#define UIC_CT6 0x00400000 /* GPT compare timer 6 */
#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
#define UIC_CT0 0x00008000 /* GPT compare timer 0 */
#define UIC_CT1 0x00004000 /* GPT compare timer 1 */
#define UIC_EIR7 0x00002000 /* External interrupt 7 */
#define UIC_EIR8 0x00001000 /* External interrupt 8 */
#define UIC_EIR9 0x00000800 /* External interrupt 9 */
#define UIC_CT2 0x00000400 /* GPT compare timer 2 */
#define UIC_CT3 0x00000200 /* GPT compare timer 3 */
#define UIC_CT4 0x00000100 /* GPT compare timer 4 */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
#define UIC_RSVD0 0x00000020 /* Reserved */
#define UIC_EPCIPER 0x00000010 /* External PCI PERR */
#define UIC_EIR0 0x00000008 /* External interrupt 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_EIR1 0x00000002 /* External interrupt 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
/* For compatibility with 405 code */
#define UIC_MAL_SERR UIC_MS
#define UIC_MAL_TXDE UIC_MTDE
#define UIC_MAL_RXDE UIC_MRDE
#define UIC_ENET UIC_ETH0
#elif !defined(CONFIG_440SPE)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
@@ -1608,6 +1917,20 @@
#define UIC_RSVD29 0x00000004 /* Reserved */
#define UIC_RSVD30 0x00000002 /* Reserved */
#define UIC_RSVD31 0x00000001 /* Reserved */
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
#define UIC_EIR5 0x80000000 /* External interrupt 5 */
#define UIC_EIR6 0x40000000 /* External interrupt 6 */
#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
#define UIC_EIR2 0x10000000 /* External interrupt 2 */
#define UIC_EIR3 0x08000000 /* External interrupt 3 */
#define UIC_DDR2 0x04000000 /* DDR2 sdram */
#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
@@ -1623,6 +1946,17 @@
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */
#define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */
#define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */
#define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
UICB0_UIC1CI | UICB0_UIC2NCI)
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller interrupts
@@ -2262,7 +2596,8 @@
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
@@ -2390,11 +2725,81 @@
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
#define SDR0_MFR_ERRATA3_EN0 0x00800000
#define SDR0_MFR_ERRATA3_EN1 0x00400000
#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
#endif
#define SDR0_MFR_ECS_MASK 0x10000000
#define SDR0_MFR_ECS_INTERNAL 0x10000000
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_SRST0 0x200
#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
#define SDR0_SRST0_PCI 0x00100000 /* PCI */
#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
#define SDR0_SRST1 0x201
#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
#else
#define SDR0_SRST_BGO 0x80000000
#define SDR0_SRST_PLB 0x40000000
@@ -2427,10 +2832,15 @@
#define SDR0_SRST_EMAC3 0x00000008
#define SDR0_SRST_RGMII 0x00000001
#endif
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#if !defined (CONFIG_440GX) && \
!defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
@@ -2498,6 +2908,120 @@
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
#endif /* CONFIG_440GX */
#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
/*--------------------------------------*/
#define CPR0_PLLC 0x40
#define CPR0_PLLC_RST_MASK 0x80000000
#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
#define CPR0_PLLC_RST_PLLRESET 0x80000000
#define CPR0_PLLC_ENG_MASK 0x40000000
#define CPR0_PLLC_ENG_DISABLE 0x00000000
#define CPR0_PLLC_ENG_ENABLE 0x40000000
#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
#define CPR0_PLLC_SRC_MASK 0x20000000
#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
#define CPR0_PLLC_SEL_MASK 0x07000000
#define CPR0_PLLC_SEL_PLL 0x00000000
#define CPR0_PLLC_SEL_CPU 0x01000000
#define CPR0_PLLC_SEL_PER 0x05000000
#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
#define CPR0_PLLC_TUNE_MASK 0x000003FF
#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
/*--------------------------------------*/
#define CPR0_PLLD 0x60
#define CPR0_PLLD_FBDV_MASK 0x1F000000
#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
#define CPR0_PLLD_FWDVA_MASK 0x000F0000
#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
#define CPR0_PLLD_FWDVB_MASK 0x00000700
#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
#define CPR0_PLLD_LFBDV_MASK 0x0000003F
#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
/*--------------------------------------*/
#define CPR0_PRIMAD 0x80
#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
/*--------------------------------------*/
#define CPR0_PRIMBD 0xA0
#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
/*--------------------------------------*/
#if 0
#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
#endif
/*--------------------------------------*/
#define CPR0_OPBD 0xC0
#define CPR0_OPBD_OPBDV0_MASK 0x03000000
#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
/*--------------------------------------*/
#define CPR0_PERD 0xE0
#define CPR0_PERD_PERDV0_MASK 0x07000000
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
/*--------------------------------------*/
#define CPR0_MALD 0x100
#define CPR0_MALD_MALDV0_MASK 0x03000000
#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
/*--------------------------------------*/
#define CPR0_SPCID 0x120
#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
/*--------------------------------------*/
#define CPR0_ICFG 0x140
#define CPR0_ICFG_RLI_MASK 0x80000000
#define CPR0_ICFG_RLI_RESETCPR 0x00000000
#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
#define CPR0_ICFG_ICS_MASK 0x00000007
#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
'----------------------------------------------------------------------------*/
@@ -2539,7 +3063,8 @@
#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* PCI Local Configuration Registers
--------------------------------- */
@@ -2625,6 +3150,33 @@
#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* USB2.0 Device */
#define USB2D0_BASE CFG_USB2D0_BASE
#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
#endif
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
@@ -2640,7 +3192,8 @@
#define GPIO0_IR (GPIO0_BASE+0x1C)
#endif /* CONFIG_440GP */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)

22
include/ppc4xx_enet.h
View File

@@ -145,12 +145,14 @@ typedef struct emac_4xx_hw_st {
#define EMAC_STACR_OC_MASK (0x00000000)
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
@@ -163,6 +165,7 @@ typedef struct emac_4xx_hw_st {
#define ZMII_MDI0 0x80000000
/* ZMII FER Register Bit Definitions */
#define ZMII_FER_DIS (0x0)
#define ZMII_FER_MDI (0x8)
#define ZMII_FER_SMII (0x4)
#define ZMII_FER_RMII (0x2)
@@ -197,7 +200,11 @@ typedef struct emac_4xx_hw_st {
#define ZMII_SMIISR_V(__x) ((3 - __x) * 8)
/* RGMII Register Addresses */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
#else
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
#endif
#define RGMII_FER (RGMII_BASE + 0x00)
#define RGMII_SSR (RGMII_BASE + 0x04)
@@ -216,7 +223,11 @@ typedef struct emac_4xx_hw_st {
#define RGMII_SSR_SP_100MBPS (0x02)
#define RGMII_SSR_SP_1000MBPS (0x04)
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define RGMII_SSR_V(__x) ((__x) * 8)
#else
#define RGMII_SSR_V(__x) ((__x -2) * 8)
#endif
/*---------------------------------------------------------------------------+
@@ -286,7 +297,8 @@ typedef struct emac_4xx_hw_st {
/* Ethernet MAC Regsiter Addresses */
#if defined(CONFIG_440)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
@@ -332,7 +344,9 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)

2
include/ppc_asm.tmpl
View File

@@ -312,7 +312,7 @@ label: \
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
li r20,MSR_KERNEL; \
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
rlwimi r20,r23,0,25,25; \
blrl ; \
.L_ ## label : \

7
include/serial.h
View File

@@ -26,6 +26,13 @@ extern struct serial_device * default_serial_console (void);
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CFG_NS16550_SERIAL)
extern struct serial_device eserial1_device;
extern struct serial_device eserial2_device;
extern struct serial_device eserial3_device;
extern struct serial_device eserial4_device;
#endif /* CFG_NS16550_SERIAL */
#endif