From 1be0c66c792d0d51debf45de3bc4eb5cafc6271d Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Mon, 22 Apr 2019 06:31:42 +0000 Subject: [PATCH 01/29] board/fsl/layerscape: Modify the aliases names when compiling dts file using DTC_FLAG='-@', the device tree compiler reports these warnings: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-' Fixed the node aliases to silence these warnings. Signed-off-by: Pankaj Bansal Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1043aqds/eth.c | 33 ++++++++++++++++---------------- board/freescale/ls1046aqds/eth.c | 26 ++++++++++++------------- 2 files changed, 30 insertions(+), 29 deletions(-) diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 8763913e31..e1919d2988 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include @@ -161,16 +162,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { if (port == FM1_DTSEC9) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s1_p1"); + "sgmii-riser-s1-p1"); } else if (port == FM1_DTSEC2) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s2_p1"); + "sgmii-riser-s2-p1"); } else if (port == FM1_DTSEC5) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s3_p1"); + "sgmii-riser-s3-p1"); } else if (port == FM1_DTSEC6) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s4_p1"); + "sgmii-riser-s4-p1"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { @@ -191,19 +192,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p1"); + "qsgmii-s1-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p2"); + "qsgmii-s1-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p3"); + "qsgmii-s1-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p4"); + "qsgmii-s1-p4"); break; default: break; @@ -213,19 +214,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p1"); + "qsgmii-s2-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p2"); + "qsgmii-s2-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p3"); + "qsgmii-s2-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p4"); + "qsgmii-s2-p4"); break; default: break; @@ -268,16 +269,16 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); + fdt_status_okay_by_alias(fdt, "emi1-slot3"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index abe8ee95d4..1eb40677b5 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include @@ -161,19 +161,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); break; case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); break; default: break; @@ -193,16 +193,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); break; default: break; @@ -246,13 +246,13 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; From 3458a4198cca572f6c82d38810e4f3c80dc8849d Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Tue, 14 May 2019 17:34:56 +0800 Subject: [PATCH 02/29] armv8: ls1028a: enable workaround for USB erratum A-008997 Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a843c1eb65..3f6c983aaf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -48,6 +48,7 @@ config ARCH_LS1028A select SYS_I2C_MXC_I2C6 select SYS_I2C_MXC_I2C7 select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06f3edb302..f2392f0ebf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -126,6 +126,10 @@ static void erratum_a008997(void) set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); #endif +#elif defined(CONFIG_ARCH_LS1028A) + clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1, + 0x7F << 11, + DCSR_USB_PCSTXSWINGFULL << 11); #endif #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 24c1b0e482..2b12e9f81a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -226,6 +226,8 @@ #define USB_PHY_RX_EQ_VAL_2 0x0080 #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 +#define DCSR_USB_IOCR1 0x108004 +#define DCSR_USB_PCSTXSWINGFULL 0x71 #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ From 123fbbbe84e06f3ff0a8e263275a55ad1e83e380 Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Tue, 14 May 2019 17:34:57 +0800 Subject: [PATCH 03/29] armv8: ls1028a: enable workaround for USB errarum A-009007 Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. So program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu Signed-off-by: Ran Wang Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f2392f0ebf..af2d86bb9d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -143,7 +143,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -167,7 +168,8 @@ static void erratum_a009007(void) usb_phy = (void __iomem *)SCFG_USB_PHY3; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); #endif -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); From 36f50b75238ee5a2589763797bc5b5551e4e8ec2 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Tue, 21 May 2019 18:28:31 +0800 Subject: [PATCH 04/29] armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 13 +++++++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 12 ++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index ef598c4cba..5835a3a69e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -22,6 +22,19 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} }, {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} }, {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} }, + {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} }, + {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} }, + {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} }, + {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} }, + {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} }, + {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} }, + {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} }, + {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} }, + {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} }, + {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, + {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, + {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, {} }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 68354ff546..8f43651756 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -64,6 +64,18 @@ enum srds_prtcl { QSGMII_B, QSGMII_C, QSGMII_D, + SGMII_T1, + SGMII_T2, + SGMII_T3, + SGMII_T4, + SXGMII1, + SXGMII2, + SXGMII3, + SXGMII4, + QXGMII1, + QXGMII2, + QXGMII3, + QXGMII4, _25GE1, _25GE2, _25GE3, From d17eb57dcf4cc6b2624327563d85fb8e99a0ae4f Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Wed, 22 May 2019 02:43:22 +0000 Subject: [PATCH 05/29] armv8: lx2160aqds: Enable sata Change sata node status to enable sata. Signed-off-by: Peng Ma Reviewed-by: Prabhakar Kushwaha --- arch/arm/dts/fsl-lx2160a-qds.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 6192156fc3..77cf2cef9a 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -15,3 +15,18 @@ compatible = "fsl,lx2160aqds", "fsl,lx2160a"; }; +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; From 087bfe67ac2555c37b257335424b7c193d7f6afd Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 23 May 2019 11:05:45 +0800 Subject: [PATCH 06/29] armv8: fsl-lsch3: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 2 ++ arch/arm/include/asm/arch-fsl-layerscape/clock.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index bc268e207c..a5540f2b9d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015, Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors * * Derived from arch/power/cpu/mpc85xx/speed.c */ @@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..b37a08d265 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors * */ @@ -14,6 +15,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; From 66fa035b55463d21bab2196289a6090431c5e45f Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 23 May 2019 11:05:46 +0800 Subject: [PATCH 07/29] mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled u-boot is trying to make CONFIG_BLK as a hard requirement for DM_MMC. But now it's still not. config BLK bool "Support block devices" depends on DM default y if DM_MMC When fsl_esdhc driver was reworked for DM_MMC support, DM_MMC without CONFIG_BLK enabled wasn't considered. This patch is to fix probe issue without CONFIG_BLK enabled. Signed-off-by: Yangbo Lu Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha --- drivers/mmc/fsl_esdhc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 672691fa6a..6a191a1765 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc + * Copyright 2019 NXP Semiconductors * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -25,6 +26,10 @@ #include #include +#if !CONFIG_IS_ENABLED(BLK) +#include "mmc_private.h" +#endif + DECLARE_GLOBAL_DATA_PTR; #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ @@ -34,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ IRQSTATEN_DINT) #define MAX_TUNING_LOOP 40 +#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ @@ -1457,6 +1463,9 @@ static int fsl_esdhc_probe(struct udevice *dev) fdt_addr_t addr; unsigned int val; struct mmc *mmc; +#if !CONFIG_IS_ENABLED(BLK) + struct blk_desc *bdesc; +#endif int ret; addr = dev_read_addr(dev); @@ -1593,6 +1602,26 @@ static int fsl_esdhc_probe(struct udevice *dev) mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev; +#if !CONFIG_IS_ENABLED(BLK) + mmc->priv = priv; + + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = ESDHC_DRIVER_STAGE_VALUE; + /* Setup the universal parts of the block interface just once */ + bdesc = mmc_get_blk_desc(mmc); + bdesc->if_type = IF_TYPE_MMC; + bdesc->removable = 1; + bdesc->devnum = mmc_get_next_devnum(); + bdesc->block_read = mmc_bread; + bdesc->block_write = mmc_bwrite; + bdesc->block_erase = mmc_berase; + + /* setup initial part type */ + bdesc->part_type = mmc->cfg->part_type; + mmc_list_add(mmc); +#endif + upriv->mmc = mmc; return esdhc_init_common(priv, mmc); From 91f54e7c61241ef31dbccf04fd269b5757882897 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 23 May 2019 04:06:48 +0000 Subject: [PATCH 08/29] armv8: ls1028a: Add ecc address node for sata. Move the ecc addr from driver to dts Signed-off-by: Peng Ma Reviewed-by: Prabhakar Kushwaha --- arch/arm/dts/fsl-ls1028a.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index e6a443aa77..29a0858cea 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -272,9 +272,10 @@ sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 133 4>; - clocks = <&clockgen 4 1>; status = "disabled"; }; From de0f9ad1dee7eb39c0c7b38ea99918823b4f1204 Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Thu, 23 May 2019 10:57:33 +0200 Subject: [PATCH 09/29] board: lx2160a: fix fsl-mc status in fdt with bootefi fsl-mc lazyapply command applies dpl from efi_exit_boot_services(). Status of fsl-mc node in working fdt is updated at this stage. However, an efi application like grub may already have copied the fdt. So the updates to fdt done at efi_exit_boot_services() may not be visible to the OS. Fix it by updating fdt earlier if fsl-mc lazyapply command is used. Signed-off-by: Mian Yousaf Kaukab Reviewed-by: Prabhakar Kushwaha --- board/freescale/lx2160a/lx2160a.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 6109b280c6..3b4cb86692 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -509,7 +509,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) { + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); fdt_fixup_board_phy(fdt); } else { From 9029fa115ab00e9f824ed1b1ce1567aeb39c9ffd Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Thu, 23 May 2019 10:57:34 +0200 Subject: [PATCH 10/29] board: lx2160a: use default scan_dev_for_boot Default environment variable is more complete. Also scans for efi binaries for example. Signed-off-by: Mian Yousaf Kaukab Reviewed-by: Prabhakar Kushwaha --- include/configs/lx2160a_common.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index eb0b1766aa..711b434baf 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -246,12 +246,6 @@ unsigned long get_board_ddr_clk(void); "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ From a1e126bf8d44f898c4dc23569245b12b9ee4c667 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Fri, 24 May 2019 14:36:27 +0800 Subject: [PATCH 11/29] armv8: ls1028a: Add secure boot defconfig Add secure boot defconfig for ls1028aqds and ls1028ardb boards. Signed-off-by: Yuantian Tang Reviewed-by: Prabhakar Kushwaha --- board/freescale/ls1028a/MAINTAINERS | 10 ++++ configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 62 ++++++++++++++++++++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 62 ++++++++++++++++++++ include/configs/ls1028a_common.h | 4 ++ 4 files changed, 138 insertions(+) create mode 100644 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS index 6f1a95ea3b..2c28825698 100644 --- a/board/freescale/ls1028a/MAINTAINERS +++ b/board/freescale/ls1028a/MAINTAINERS @@ -19,3 +19,13 @@ F: board/freescale/ls1028a/ F: include/configs/ls1028a_common.h F: include/configs/ls1028ardb.h F: configs/ls1028ardb_tfa_defconfig + +LS1028AQDS_SECURE_BOOT BOARD +M: Tang Yuantian +S: Maintained +F: configs/ls1028aqds_tfa_SECURE_BOOT_defconfig + +LS1028ARDB_SECURE_BOOT BOARD +M: Tang Yuantian +S: Maintained +F: configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..7cd2f59d7b --- /dev/null +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028AQDS=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_RSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..3432f90087 --- /dev/null +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028ARDB=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_RSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 0db86396e9..d3d787f14d 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -197,4 +197,8 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#ifdef CONFIG_SECURE_BOOT +#include +#endif + #endif /* __L1028A_COMMON_H */ From 85e5e21981115fdb64fd39723dd8856bef5c66e9 Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Mon, 27 May 2019 12:17:18 +0800 Subject: [PATCH 12/29] armv8: lx2160aqds: Enable eSDHC controllers This patch is to enable esdhc controllers for lx2160aqds Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha --- arch/arm/dts/fsl-lx2160a-qds.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 77cf2cef9a..99836c4ccb 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -15,6 +15,14 @@ compatible = "fsl,lx2160aqds", "fsl,lx2160a"; }; +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + &sata0 { status = "okay"; }; From 1dff14c87d07fc535aaf9e2d3012fd966ed9af89 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Tue, 28 May 2019 21:37:58 +0530 Subject: [PATCH 13/29] armv8/fsl-layerscape: Add loop to check L3 dcache status Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar Signed-off-by: Meenakshi Aggarwal Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 30 ++++++-------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6721a579ea..711ab87556 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP * * Extracted from armv8/start.S */ @@ -356,31 +357,22 @@ get_svr: #if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: - /* x0 has the desired status, return 0 for success, 1 for timeout - * clobber x1, x2, x3, x4, x6, x7 + /* x0 has the desired status, return only if operation succeed + * clobber x1, x2, x6 */ mov x1, x0 - mov x7, #0 /* flag for timeout */ - mrs x3, cntpct_el0 /* read timer */ - add x3, x3, #1200 /* timeout after 100 microseconds */ + mov w6, #8 /* HN-F node count */ mov x0, #0x18 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ - mov w6, #8 /* HN-F node count */ 1: ldr x2, [x0] cmp x2, x1 /* check status */ b.eq 2f - mrs x4, cntpct_el0 - cmp x4, x3 - b.ls 1b - mov x7, #1 /* timeout */ - b 3f + b 1b 2: add x0, x0, #0x10000 /* move to next node */ subs w6, w6, #1 cbnz w6, 1b -3: - mov x0, x7 ret hnf_set_pstate: @@ -405,10 +397,8 @@ ENTRY(__asm_flush_l3_dcache) /* * Return status in x0 * success 0 - * timeout 1 for setting SFONLY, 2 for FAM, 3 for both */ mov x29, lr - mov x8, #0 dsb sy mov x0, #0x1 /* HNFPSTAT_SFONLY */ @@ -416,19 +406,15 @@ ENTRY(__asm_flush_l3_dcache) mov x0, #0x4 /* SFONLY status */ bl hnf_pstate_poll - cbz x0, 1f - mov x8, #1 /* timeout */ -1: + dsb sy mov x0, #0x3 /* HNFPSTAT_FAM */ bl hnf_set_pstate mov x0, #0xc /* FAM status */ bl hnf_pstate_poll - cbz x0, 1f - add x8, x8, #0x2 -1: - mov x0, x8 + + mov x0, #0 mov lr, x29 ret ENDPROC(__asm_flush_l3_dcache) From f68ce9e9ac13d8faff335ff860dc92d75f39a356 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Wed, 29 May 2019 02:40:47 +0000 Subject: [PATCH 14/29] ARM: dts: ls1021a: Fixed reg for sata node This patch is to fixed the reg read to "0" for armv7 architecture. Signed-off-by: Peng Ma Reviewed-by: Prabhakar Kushwaha --- arch/arm/dts/ls1021a.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 8a0f473e25..7fb24ab687 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -406,8 +406,7 @@ sata: sata@3200000 { compatible = "fsl,ls1021a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x0 0x20220520 0x0 0x4>; /* ecc sata addr*/ + reg = <0x3200000 0x10000 0x20220520 0x4>; reg-names = "sata-base", "ecc-addr"; interrupts = <0 101 4>; status = "disabled"; From 293d75c0b1dc0678741841c639f52fa4875929a5 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Wed, 29 May 2019 12:12:36 +0000 Subject: [PATCH 15/29] armv8: fsl-layerscape: Update qspi clk cfg Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index af2d86bb9d..c53131f74a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -599,6 +599,9 @@ void fsl_lsch2_early_init_f(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; +#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) + enum boot_src src; +#endif #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); @@ -608,8 +611,14 @@ void fsl_lsch2_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ #endif +#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) + src = get_boot_src(); + if (src != BOOT_SOURCE_QSPI_NOR) + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#else #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif #endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | From 4514ccef91f6538a203baf554109db0b0643a7b1 Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Thu, 30 May 2019 12:04:14 +0000 Subject: [PATCH 16/29] ls1046ardb: Add CONFIG_ENV_ADDR to init env in qspi boot Signed-off-by: Pankit Garg Reviewed-by: Prabhakar Kushwaha --- include/configs/ls1046ardb.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 831767235e..2d20f15683 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046ARDB_H__ @@ -162,6 +163,8 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET #else #if defined(CONFIG_SD_BOOT) #define CONFIG_SYS_MMC_ENV_DEV 0 From ab748801ef2f15679a618efbc6e8894b67658bad Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Thu, 30 May 2019 12:04:15 +0000 Subject: [PATCH 17/29] armv8: fsl-layerscape: Change bootcmd update logic Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c53131f74a..7414215208 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP */ #include @@ -823,7 +824,11 @@ int board_late_init(void) * check if gd->env_addr is default_environment; then setenv bootcmd * and mcinitcmd. */ +#if !defined(CONFIG_ENV_ADDR) || defined(ENV_IS_EMBEDDED) + if (gd->env_addr == (ulong)&default_environment[0]) { +#else if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { +#endif fsl_setenv_bootcmd(); fsl_setenv_mcinitcmd(); } From 4da0e52c9dc04b74d230e32d1bda5d751cc6f41f Mon Sep 17 00:00:00 2001 From: Alex Marginean Date: Thu, 30 May 2019 19:28:31 +0300 Subject: [PATCH 18/29] armv8: fsl-layerscape: fix config dependency for layerscape pci code Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 11117657fe..fabe0f0359 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -435,7 +435,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); -#ifdef CONFIG_PCI +#ifdef CONFIG_PCI_LAYERSCAPE ft_pci_setup(blob, bd); #endif From 749423270082e4850687de76c1742d34da1af607 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Fri, 31 May 2019 16:03:28 +0530 Subject: [PATCH 19/29] configs: Unset CONFIG_SPI_FLASH_BAR, move CONFIG_FSL_QSPI to defconfig Signed-off-by: Ashish Kumar Reviewed-by: Prabhakar Kushwaha --- configs/ls1012a2g5rdb_qspi_defconfig | 2 ++ configs/ls1012a2g5rdb_tfa_defconfig | 2 ++ configs/ls1012afrdm_qspi_defconfig | 2 ++ configs/ls1012afrdm_tfa_defconfig | 2 ++ configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012afrwy_tfa_defconfig | 2 ++ configs/ls1012aqds_qspi_defconfig | 2 ++ configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012aqds_tfa_defconfig | 2 ++ configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_qspi_defconfig | 2 ++ configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1012ardb_tfa_defconfig | 2 ++ include/configs/ls1012a_common.h | 1 - 15 files changed, 28 insertions(+), 1 deletion(-) diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index eaa16d3680..1ef92b445a 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -36,6 +36,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index cef646b115..5428357030 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -36,6 +36,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index d521979e72..2b83e4ad17 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_DM=y # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index a41f97cf8f..3de0a982db 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -32,6 +32,7 @@ CONFIG_DM=y # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index bf98466576..a4ae87b9a7 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -33,6 +33,7 @@ CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -45,6 +46,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index b0fdad6dd0..827d4ec2c0 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -33,6 +33,7 @@ CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -45,6 +46,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 6a70f5881b..cbeb9cabcf 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -34,6 +34,7 @@ CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -46,6 +47,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 7194182ce2..90b30a6172 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -67,6 +68,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 6de203b1ec..ebd3eeaa12 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -59,6 +60,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 44b4e121c0..3a99037883 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -67,6 +68,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 54b050e029..533e251341 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_PCI=y @@ -49,6 +50,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 78b4186782..f9ea2097fb 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -50,6 +51,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index b612587897..8e2ff1fe7b 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_PCI=y @@ -49,6 +50,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 2f96abc1bf..8acc07d3c8 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -50,6 +51,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5581cfd1c9..dd2a679b79 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -43,7 +43,6 @@ #define CONFIG_FSL_SPI_INTERFACE #define CONFIG_SF_DATAFLASH -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION From 73420f0220e03caea1e11688a04636719760b534 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Fri, 31 May 2019 16:00:26 +0200 Subject: [PATCH 20/29] arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046a As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index f8310f2105..91de5ff0d3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, - {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, + {0x3363, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, From c34d8dcb3ed7f4c2b09d1cb7d5dc534d0c7aeae3 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Fri, 31 May 2019 16:11:35 +0200 Subject: [PATCH 21/29] arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046A Signed-off-by: Maciej Pijanowski Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index 91de5ff0d3..12775c6543 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -33,6 +33,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x3040, {SGMII_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} }, {} }; From fd90b6d5ab20ce321eef7b68696d064efb2f5063 Mon Sep 17 00:00:00 2001 From: Maciej Pijanowski Date: Fri, 31 May 2019 22:30:58 +0200 Subject: [PATCH 22/29] configs/ls1046ardb_*: disable CONFIG_SPI_FLASH_USE_4K_SECTORS With this setting enabled, the on-board QSPI cannot be properly flashed. There are no error messages, but the simple write / read / compare tests fail. This is already disabled in the qspi and tfa defconfigs for the LS1046ARDB platform. Signed-off-by: Maciej Pijanowski Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha --- configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 63f6588d2b..855edc726e 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index a4038b8d29..6326c47cdb 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -52,6 +52,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 92afc919a5..7bf23ad7fd 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_DM=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 9c124fd7e0..829861b03b 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y From 0dd74ec2df8ca77b1264e82c3a9a17ef7e4c0f14 Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Mon, 3 Jun 2019 19:24:23 +0800 Subject: [PATCH 23/29] armv8: fsl-lsch2: add clock support for the second eSDHC Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 723d7eac5d..9ece4b90e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP. */ #include @@ -250,6 +251,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: From 062d8148f8a6ed574a45f8b3096ba0226c4b5fca Mon Sep 17 00:00:00 2001 From: Alex Marginean Date: Fri, 7 Jun 2019 17:03:07 +0300 Subject: [PATCH 24/29] arm: ls1028a: define the integrated PCI bus (ECAM) LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/arm/dts/fsl-ls1028a.dtsi | 11 +++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++ .../arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++ configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028ardb_tfa_defconfig | 1 + 5 files changed, 18 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 29a0858cea..49074112c4 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -108,6 +108,17 @@ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie@1f0000000 { + compatible = "pci-host-ecam-generic"; + /* ECAM bus 0, HW has more space reserved but not populated */ + bus-range = <0x0 0x0>; + reg = <0x01 0xf0000000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index bdeb62576c..7759acdb8f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -42,7 +42,9 @@ #else #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#endif #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 2b12e9f81a..ee9b33becf 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -186,6 +186,9 @@ #elif CONFIG_ARCH_LS1028A #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +/* this is used by integrated PCI on LS1028, includes ECAM and register space */ +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 717b810523..7982ce4157 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index a8e4ddb7a8..c65e37df79 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y From d7a4ddd3b23e119d2cfc94f7d9751d1fafb3c258 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 10 Jun 2019 10:17:25 +0000 Subject: [PATCH 25/29] armv8: ls2088aqds: Add bootcmd for TFA boot Add bootcmd for IFC NOR boot and SD boot. Signed-off-by: Wasim Khan Reviewed-by: Prabhakar Kushwaha --- include/configs/ls2080aqds.h | 45 +++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 74c7dc4f8a..11c6ffdddb 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -378,8 +378,8 @@ unsigned long get_board_ddr_clk(void); "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "loadaddr_sd=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "kernel_addr_sd=0x800\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_addr_sd=0x8000\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ @@ -389,9 +389,23 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ - "mcinitcmd=fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" \ - "mcmemsize=0x70000000 \0" + "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_size=0x40000\0" \ + "BOARD=ls2088aqds\0" \ + "mcmemsize=0x70000000 \0" \ + IFC_MC_INIT_CMD \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$BOARD\0" #elif defined(CONFIG_SD_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -426,6 +440,25 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_TFABOOT */ #endif /* CONFIG_SECURE_BOOT */ +#ifdef CONFIG_TFABOOT +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x88000000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x88000000; " \ + "run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#define IFC_NOR_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) #define CONFIG_FSL_MEMAC #define CONFIG_PHYLIB_10G From c3d141e03a2fe0196b686535ccc258e472f43996 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 10 Jun 2019 10:17:27 +0000 Subject: [PATCH 26/29] armv8: ls2088aqds: Fix MC firmware loading during SD boot During SD boot, MC firmware and DPC are copied from SD card to DDR. Size reserved between MC and DPC firmware on DDR is 1MB. If the size of MC firmware(load address 0x80000000) is more than 1 MB then part of MC firmware will be overwritten by DPC firmware (load address 0x80100000). Fix: Update the MC/DPL/DPC firmware's DDR address as per their respective addresses in SD card. Signed-off-by: Wasim Khan Reviewed-by: Prabhakar Kushwaha --- include/configs/ls2080aqds.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 11c6ffdddb..18f30b585c 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -368,9 +368,9 @@ unsigned long get_board_ddr_clk(void); #else #ifdef CONFIG_TFABOOT #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" @@ -446,8 +446,8 @@ unsigned long get_board_ddr_clk(void); "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x88000000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x88000000; " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ "run sd_bootcmd; " \ "env exists secureboot && esbc_halt;" From 196fa2efbe0cd1fcb3d2f13cb02ba3dfdde56122 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Mon, 10 Jun 2019 10:17:29 +0000 Subject: [PATCH 27/29] armv8: ls2088ardb: Fix MC firmware loading during SD boot During SD boot, MC firmware and DPC are copied from SD card to DDR. Size reserved between MC and DPC firmware on DDR is 1MB. If the size of MC firmware(load address 0x80000000) is more than 1 MB then part of MC firmware will be overwritten by DPC firmware (load address 0x80100000). Fix: Update the MC/DPL/DPC firmware's DDR address as per their respective addresses in SD card. Signed-off-by: Wasim Khan Reviewed-by: Prabhakar Kushwaha --- include/configs/ls2080ardb.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2e8a8bbdb7..bfb54be79b 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -342,14 +342,14 @@ unsigned long get_board_sys_clk(void); "esbc_validate 0x20740000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ "mmc read 0x80700000 0x3800 0x10 && " \ "mmc read 0x80740000 0x3A00 0x10 && " \ "esbc_validate 0x80700000 && " \ "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "env exists secureboot && " \ "esbc_validate 0x580700000 && " \ @@ -528,8 +528,8 @@ unsigned long get_board_sys_clk(void); "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x88000000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x88000000; " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ "run distro_bootcmd;run sd_bootcmd; " \ "env exists secureboot && esbc_halt;" From d90c7ac7a95d1347747466779b6821b4600db4b8 Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Thu, 6 Jun 2019 12:35:28 +0000 Subject: [PATCH 28/29] armv8: ls1046afrwy: Add support for LS1046AFRWY platform LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza Signed-off-by: Madalin Bucur Signed-off-by: Pankit Garg Signed-off-by: Pramod Kumar Signed-off-by: Rajesh Bhagat Signed-off-by: Vabhav Sharma Reviewed-by: Prabhakar Kushwaha --- arch/arm/Kconfig | 15 ++ arch/arm/cpu/armv8/Kconfig | 1 + .../cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-frwy.dts | 34 +++ board/freescale/ls1046afrwy/Kconfig | 17 ++ board/freescale/ls1046afrwy/MAINTAINERS | 7 + board/freescale/ls1046afrwy/Makefile | 7 + board/freescale/ls1046afrwy/README | 76 ++++++ board/freescale/ls1046afrwy/ddr.c | 19 ++ board/freescale/ls1046afrwy/eth.c | 114 +++++++++ board/freescale/ls1046afrwy/ls1046afrwy.c | 223 ++++++++++++++++++ configs/ls1046afrwy_tfa_defconfig | 56 +++++ include/configs/ls1046a_common.h | 13 +- include/configs/ls1046afrwy.h | 136 +++++++++++ include/fm_eth.h | 12 + 16 files changed, 730 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1046a-frwy.dts create mode 100644 board/freescale/ls1046afrwy/Kconfig create mode 100644 board/freescale/ls1046afrwy/MAINTAINERS create mode 100644 board/freescale/ls1046afrwy/Makefile create mode 100644 board/freescale/ls1046afrwy/README create mode 100644 board/freescale/ls1046afrwy/ddr.c create mode 100644 board/freescale/ls1046afrwy/eth.c create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy.c create mode 100644 configs/ls1046afrwy_tfa_defconfig create mode 100644 include/configs/ls1046afrwy.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 01ff57cf1b..d9ad32c0bc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1406,6 +1406,20 @@ config TARGET_LS1046ARDB development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config TARGET_LS1046AFRWY + bool "Support ls1046afrwy" + select ARCH_LS1046A + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM_SPI_FLASH if DM_SPI + imply SCSI + help + Support for Freescale LS1046AFRWY platform. + The LS1046A Freeway Board (FRWY) is a high-performance + development platform that supports the QorIQ LS1046A + Layerscape Architecture processor. config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -1697,6 +1711,7 @@ source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" +source "board/freescale/ls1046afrwy/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 8a97d5b3fb..92a2b58ed4 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -107,6 +107,7 @@ config PSCI_RESET !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ + !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LX2160AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index 12775c6543..9347e516bf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 528fb909d5..4dfc2c6309 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -342,6 +342,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1046a-qds-duart.dtb \ fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ + fsl-ls1046a-frwy.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ fsl-ls1012a-2g5rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts new file mode 100644 index 0000000000..3d41e3bd44 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device Tree Include file for NXP Layerscape-1046A family SoC. + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; +/include/ "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A FRWY Board"; + + aliases { + spi0 = &qspi; + }; + +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: mt25qu512abb8esf@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + +}; + diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig new file mode 100644 index 0000000000..6a4c3e92f7 --- /dev/null +++ b/board/freescale/ls1046afrwy/Kconfig @@ -0,0 +1,17 @@ + +if TARGET_LS1046AFRWY + +config SYS_BOARD + default "ls1046afrwy" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046afrwy" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS new file mode 100644 index 0000000000..357d23e70d --- /dev/null +++ b/board/freescale/ls1046afrwy/MAINTAINERS @@ -0,0 +1,7 @@ +LS1046AFRWY BOARD +M: Pramod Kumar +S: Maintained +F: board/freescale/ls1046afrwy/ +F: board/freescale/ls1046afrwy/ls1046afrwy.c +F: include/configs/ls1046afrwy.h +F: configs/ls1046afrwy_tfa_defconfig diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile new file mode 100644 index 0000000000..c70f5cda79 --- /dev/null +++ b/board/freescale/ls1046afrwy/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 NXP + +obj-y += ddr.o +obj-y += ls1046afrwy.o +obj-$(CONFIG_NET) += eth.o diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README new file mode 100644 index 0000000000..d7b5a7794f --- /dev/null +++ b/board/freescale/ls1046afrwy/README @@ -0,0 +1,76 @@ +Overview +-------- +The LS1046A Freeway Board (iFRWY) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The FRWY-LS1046A provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + FRWY-LS1046A board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: Unused + - Lane2: QSGMII + - Lane3: Unused + - SERDES2 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: PCIe3 with PCIe x1 slot + - Lane2: Unused + - Lane3: PCIe3 with PCIe x1 slot + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One 512 MB NAND flash with ECC support + - USB 3.0 + - Two Type A port + - SDHC: connects directly to a full microSD slot + - QSPI: 64 MB high-speed flash Memory for boot code and storage + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +QSPI flash map: +Start Address End Address Description Size +0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB +0x00_4010_0000 - 0x00_404F_FFFF FIP Image + (Bl31 + BL32(optee. + bin) + Bl33(uboot) + + headers for secure + boot) 4MB +0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB +0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB +0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB +0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB +0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB +0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB + +Booting Options +--------------- +a) QSPI boot +b) microSD boot diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c new file mode 100644 index 0000000000..daf17e0169 --- /dev/null +++ b/board/freescale/ls1046afrwy/ddr.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c new file mode 100644 index 0000000000..9f8bd92850 --- /dev/null +++ b/board/freescale/ls1046afrwy/eth.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info dtsec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x3040: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(FM1_DTSEC6, dev); + fm_info_set_mdio(FM1_DTSEC5, dev); + fm_info_set_mdio(FM1_DTSEC10, dev); + fm_info_set_mdio(FM1_DTSEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + u32 srds_s1; + int i, prop; + int offset, nodeoff; + const char *path; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Cycle through all aliases */ + for (prop = 0; ; prop++) { + const char *name; + + /* FDT might have been edited, recompute the offset */ + offset = fdt_first_property_offset(blob, + fdt_path_offset(blob, + "/aliases") + ); + /* Select property number 'prop' */ + for (i = 0; i < prop; i++) + offset = fdt_next_property_offset(blob, offset); + + if (offset < 0) + break; + + path = fdt_getprop_by_offset(blob, offset, &name, NULL); + nodeoff = fdt_path_offset(blob, path); + + switch (srds_s1) { + case 0x3040: + if (!strcmp(name, "ethernet1")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet2")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet3")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet6")) + fdt_status_disabled(blob, nodeoff); + break; + default: + printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n", + __func__, srds_s1); + break; + } + } + + return 0; +} +#endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c new file mode 100644 index 0000000000..41412a76b6 --- /dev/null +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LS1046A_PORSR1_REG 0x1EE0000 +#define BOOT_SRC_SD 0x20000000 +#define BOOT_SRC_MASK 0xFF800000 +#define BOARD_REV_GPIO 13 +#define USB2_SEL_MASK 0x00000100 + +#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ +(((word) & 0x00ff0000) >> 8) | \ +(((word) & 0x0000ff00) << 8) | \ +(((word) & 0x000000ff) << 24)) +#define SPI_MCR_REG 0x2100000 + +DECLARE_GLOBAL_DATA_PTR; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static inline void demux_select_usb2(void) +{ + u32 val; + struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); + + val = in_be32(&pgpio->gpdir); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdir, val); + + val = in_be32(&pgpio->gpdat); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdat, val); +} + +static inline void set_spi_cs_signal_inactive(void) +{ + /* default: all CS signals inactive state is high */ + uint mcr_val; + uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + mcr_val = in_be32(SPI_MCR_REG); + mcr_val |= DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); + out_be32(SPI_MCR_REG, mcr_cfg_val); + mcr_val = in_be32(SPI_MCR_REG); + mcr_val &= ~DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +static inline uint8_t get_board_version(void) +{ + u8 val; + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03; + + return val; +} + +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; + u32 boot_src; + u8 rev; + + rev = get_board_version(); + switch (rev) { + case 0x00: + puts("Board: LS1046AFRWY, Rev: A, boot from "); + break; + case 0x01: + puts("Board: LS1046AFRWY, Rev: B, boot from "); + break; + default: + puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); + break; + } + boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); + + if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) + puts("SD\n"); + else + puts("QSPI\n"); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; +val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + /* + * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT + * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); +#ifdef CONFIG_HAS_FSL_IIC3 + /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x0000); +#endif + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#ifndef CONFIG_HAS_FSL_IIC3 + /* + * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input + * to select I2C3_USB2_SEL_IO + * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to + * I2C3 header (default) + * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to + * USB2 port + * programmed to select USB2 by setting GPIO3_23 output to one + */ + demux_select_usb2(); +#endif +#endif + set_spi_cs_signal_inactive(); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig new file mode 100644 index 0000000000..0b94b018d6 --- /dev/null +++ b/configs/ls1046afrwy_tfa_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 34b4756ed8..59c43f1ae1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046A_COMMON_H @@ -202,6 +203,15 @@ #include #endif +#if defined(CONFIG_TARGET_LS1046AFRWY) +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046afrwy_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" +#else +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046ardb_bs.out\0" +#endif #ifndef SPL_NO_MISC /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -232,8 +242,7 @@ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ - "boot_scripts=ls1046ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ + LS1046A_BOOT_SRC_AND_HDR \ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} devplist; " \ "env exists devplist || setenv devplist 1; " \ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h new file mode 100644 index 0000000000..791bb8dc47 --- /dev/null +++ b/include/configs/ls1046afrwy.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1046AFRWY_H__ +#define __LS1046AFRWY_H__ + +#include "ls1046a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_UBOOT_BASE 0x40100000 + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ +#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET + +#define QSGMII_PORT1_PHY_ADDR 0x1c +#define QSGMII_PORT2_PHY_ADDR 0x1d +#define QSGMII_PORT3_PHY_ADDR 0x1e +#define QSGMII_PORT4_PHY_ADDR 0x1f + +#define FDT_SEQ_MACADDR_FROM_ENV + +#define CONFIG_ETHPRIME "FM1@DTSEC3" + +#endif + +/* QSPI device */ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#undef CONFIG_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#include + +#endif /* __LS1046AFRWY_H__ */ diff --git a/include/fm_eth.h b/include/fm_eth.h index 2e2ba756a0..729ad63cd5 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __FM_ETH_H__ @@ -41,8 +42,19 @@ enum fm_eth_type { FM_ETH_10G_E, }; +/* Historically, on FMan v3 platforms, the first MDIO bus has been used for + * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the + * TGEC name). + * + * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus, + * and no TGEC ports are present on-board. + */ #ifdef CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_TARGET_LS1046AFRWY +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#else #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) #if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) From da70f766dd19d3645f32ed51a64b137bac7da423 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Tue, 11 Jun 2019 09:37:49 +0000 Subject: [PATCH 29/29] board/freescale/common: secure_boot: Set bootdelay to -2. Uboot prompt must not be available while running secure boot. TO ensure this bootdelay must be set to -2. Signed-off-by: Udit Agarwal Reviewed-by: Prabhakar Kushwaha --- board/freescale/common/fsl_chain_of_trust.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 97376c4165..dddfd26a13 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -79,7 +79,7 @@ int fsl_setenv_chain_of_trust(void) * bootdelay = 0 (To disable Boot Prompt) * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) */ - env_set("bootdelay", "0"); + env_set("bootdelay", "-2"); #ifdef CONFIG_ARM env_set("secureboot", "y");