From 54d5d2d56bb6c46c996a4d249dbae3b12a7a4fac Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 11 Sep 2021 13:20:00 -0400 Subject: [PATCH 001/228] clk: k210: Fix checking if ulongs are less than 0 The PLL functions take ulong arguments for rate, but still check if that rate is negative (which is never true). The correct way to handle this is to use IS_ERR_VALUE (like is already done in k210_clk_set_rate). While we're at it, we can move the error checking up into the caller of the pll set/get rate functions. This also protects our other calculations from using bogus values for rate. Fixes: 609bd60b94 ("clk: k210: Rewrite to remove CCF") Reported-by: Coverity Scan Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/clk_kendryte.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk_kendryte.c b/drivers/clk/clk_kendryte.c index 3148756968..2caa21aec9 100644 --- a/drivers/clk/clk_kendryte.c +++ b/drivers/clk/clk_kendryte.c @@ -849,9 +849,6 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate, u32 reg; ulong calc_rate; - if (rate_in < 0) - return rate_in; - err = k210_pll_calc_config(rate, rate_in, &config); if (err) return err; @@ -895,7 +892,7 @@ static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, u64 r, f, od; u32 reg = readl(priv->base + k210_plls[id].off); - if (rate_in < 0 || (reg & K210_PLL_BYPASS)) + if (reg & K210_PLL_BYPASS) return rate_in; if (!(reg & K210_PLL_PWRD)) @@ -1029,6 +1026,8 @@ static ulong do_k210_clk_get_rate(struct k210_clk_priv *priv, int id) parent = k210_clk_get_parent(priv, id); parent_rate = do_k210_clk_get_rate(priv, parent); + if (IS_ERR_VALUE(parent_rate)) + return parent_rate; if (k210_clks[id].flags & K210_CLKF_PLL) return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate); @@ -1099,6 +1098,8 @@ static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate) parent = k210_clk_get_parent(priv, clk->id); rate_in = do_k210_clk_get_rate(priv, parent); + if (IS_ERR_VALUE(rate_in)) + return rate_in; log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in); From 49708749701d957dacb2b01ea3d71e457804f7eb Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 11 Sep 2021 13:20:01 -0400 Subject: [PATCH 002/228] k210: clk: Refactor out_of_spec tests Everything here sits in a while (true) loop. However, this introduces a couple of layers of indentation. We can simplify the code by introducing a single goto instead of using continue/break. This will also make adding loops in the next patch easier. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/clk_kendryte.c | 105 ++++++++++++++++++------------------- 1 file changed, 52 insertions(+), 53 deletions(-) diff --git a/drivers/clk/clk_kendryte.c b/drivers/clk/clk_kendryte.c index 2caa21aec9..69691c4a04 100644 --- a/drivers/clk/clk_kendryte.c +++ b/drivers/clk/clk_kendryte.c @@ -709,6 +709,10 @@ TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, * Whether we swapped r and od while enforcing frequency limits */ bool swapped = false; + /* + * Whether the intermediate frequencies are out-of-spec + */ + bool out_of_spec; u64 last_od = od; u64 last_r = r; @@ -767,76 +771,71 @@ TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, * aren't in spec, try swapping r and od. If everything is * in-spec, calculate the relative error. */ - while (true) { +again: + out_of_spec = false; + if (r > max_r) { + out_of_spec = true; + } else { /* - * Whether the intermediate frequencies are out-of-spec + * There is no way to only divide once; we need + * to examine the frequency with and without the + * effect of od. */ - bool out_of_spec = false; + u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); - if (r > max_r) { + if (vco > 1750000000 || vco < 340000000) out_of_spec = true; - } else { - /* - * There is no way to only divide once; we need - * to examine the frequency with and without the - * effect of od. - */ - u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); + } - if (vco > 1750000000 || vco < 340000000) - out_of_spec = true; + if (out_of_spec) { + u64 new_r, new_od; + + if (!swapped) { + u64 tmp = r; + + r = od; + od = tmp; + swapped = true; + goto again; } - if (out_of_spec) { - if (!swapped) { - u64 tmp = r; - - r = od; - od = tmp; - swapped = true; - continue; - } else { - /* - * Try looking ahead to see if there are - * additional factors for the same - * product. - */ - if (i + 1 < ARRAY_SIZE(factors)) { - u64 new_r, new_od; - - i++; - new_r = UNPACK_R(factors[i]); - new_od = UNPACK_OD(factors[i]); - if (r * od == new_r * new_od) { - r = new_r; - od = new_od; - swapped = false; - continue; - } - i--; - } - break; + /* + * Try looking ahead to see if there are additional + * factors for the same product. + */ + if (i + 1 < ARRAY_SIZE(factors)) { + i++; + new_r = UNPACK_R(factors[i]); + new_od = UNPACK_OD(factors[i]); + if (r * od == new_r * new_od) { + r = new_r; + od = new_od; + swapped = false; + goto again; } + i--; } - error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); - /* The lower 16 bits are spurious */ - error = abs((error - BIT(32))) >> 16; + /* We ran out of things to try */ + continue; + } - if (error < best_error) { - best->r = r; - best->f = f; - best->od = od; - best_error = error; - } - break; + error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); + /* The lower 16 bits are spurious */ + error = abs((error - BIT(32))) >> 16; + + if (error < best_error) { + best->r = r; + best->f = f; + best->od = od; + best_error = error; } } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0); + log_debug("best error %lld\n", best_error); if (best_error == S64_MAX) return -EINVAL; - log_debug("best error %lld\n", best_error); return 0; } From 6e23c9f0c1ebe9b93077b6901733cd01d3848208 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 11 Sep 2021 13:20:02 -0400 Subject: [PATCH 003/228] test: dm: k210: Reduce duplication in test cases Having to copy-paste the same 3 lines makes adding new test cases error-prone. Use a macro. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Reviewed-by: Leo Yu-Chi Liang --- test/dm/k210_pll.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c index 54764f269c..5574ac96fa 100644 --- a/test/dm/k210_pll.c +++ b/test/dm/k210_pll.c @@ -69,27 +69,21 @@ static int dm_test_k210_pll(struct unit_test_state *uts) &theirs)); ut_asserteq(-EINVAL, k210_pll_calc_config(1500000000, 20000000, &theirs)); + ut_asserteq(-EINVAL, k210_pll_calc_config(1750000000, 13300000, + &theirs)); /* Verify we get the same output with brute-force */ - ut_assertok(dm_test_k210_pll_calc_config(390000000, 26000000, &ours)); - ut_assertok(k210_pll_calc_config(390000000, 26000000, &theirs)); - ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); +#define compare(rate, rate_in) do { \ + ut_assertok(dm_test_k210_pll_calc_config(rate, rate_in, &ours)); \ + ut_assertok(k210_pll_calc_config(rate, rate_in, &theirs)); \ + ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); \ +} while (0) - ut_assertok(dm_test_k210_pll_calc_config(26000000, 390000000, &ours)); - ut_assertok(k210_pll_calc_config(26000000, 390000000, &theirs)); - ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); - - ut_assertok(dm_test_k210_pll_calc_config(400000000, 26000000, &ours)); - ut_assertok(k210_pll_calc_config(400000000, 26000000, &theirs)); - ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); - - ut_assertok(dm_test_k210_pll_calc_config(27000000, 26000000, &ours)); - ut_assertok(k210_pll_calc_config(27000000, 26000000, &theirs)); - ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); - - ut_assertok(dm_test_k210_pll_calc_config(26000000, 27000000, &ours)); - ut_assertok(k210_pll_calc_config(26000000, 27000000, &theirs)); - ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); + compare(390000000, 26000000); + compare(26000000, 390000000); + compare(400000000, 26000000); + compare(27000000, 26000000); + compare(26000000, 27000000); return 0; } From 425c08faa8a2d6af5d9c1d83a97572f6401137bf Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 11 Sep 2021 13:20:03 -0400 Subject: [PATCH 004/228] clk: k210: Try harder to get the best config In some cases, the best config cannot be used because the VCO would be out-of-spec. In these cases, we may need to try a worse combination of r/od in order to find the best representable config. This also adds a few test cases to catch this and other (possible) unlikely errors. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- drivers/clk/clk_kendryte.c | 24 ++++++++++++++++++++++++ test/dm/k210_pll.c | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/drivers/clk/clk_kendryte.c b/drivers/clk/clk_kendryte.c index 69691c4a04..97efda5b6f 100644 --- a/drivers/clk/clk_kendryte.c +++ b/drivers/clk/clk_kendryte.c @@ -816,6 +816,30 @@ again: i--; } + /* + * Try looking back to see if there is a worse ratio + * that we could try anyway + */ + while (i > 0) { + i--; + new_r = UNPACK_R(factors[i]); + new_od = UNPACK_OD(factors[i]); + /* + * Don't loop over factors for the same product + * to avoid getting stuck because of the above + * clause + */ + if (r * od != new_r * new_od) { + if (new_r * new_od > last_r * last_od) { + r = new_r; + od = new_od; + swapped = false; + goto again; + } + break; + } + } + /* We ran out of things to try */ continue; } diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c index 5574ac96fa..f55379f336 100644 --- a/test/dm/k210_pll.c +++ b/test/dm/k210_pll.c @@ -84,6 +84,10 @@ static int dm_test_k210_pll(struct unit_test_state *uts) compare(400000000, 26000000); compare(27000000, 26000000); compare(26000000, 27000000); + compare(13300000 * 64, 13300000); + compare(21250000, 21250000 * 70); + compare(21250000, 1750000000); + compare(1750000000, 1750000000); return 0; } From 41f7be733444b9221c828ee9c7c22cddfac5a28c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 10:56:09 -0500 Subject: [PATCH 005/228] serial: Add a debug console using the RISC-V SBI interface The RISC-V SBI interface v0.1 provides a function for printing a character to the console. Even though SBI v0.1 functions are deprecated, the SBI console is quite useful for early debugging, because it works without any dcache, memory, or MMIO access in S mode. Signed-off-by: Samuel Holland Reviewed-by: Sean Anderson Reviewed-by: Bin Meng --- drivers/serial/Kconfig | 10 ++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_sbi.c | 16 ++++++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 drivers/serial/serial_sbi.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 3bb5b02eab..122a39789c 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -280,6 +280,14 @@ config DEBUG_EFI_CONSOLE U-Boot when running on top of EFI (Extensive Firmware Interface). This is a type of BIOS used by PCs. +config DEBUG_SBI_CONSOLE + bool "SBI" + depends on SBI_V01 + help + Select this to enable a debug console which calls back to SBI to + output to the console. This can be useful for early debugging of + U-Boot when running on top of SBI (Supervisor Binary Interface). + config DEBUG_UART_S5P bool "Samsung S5P" depends on ARCH_EXYNOS || ARCH_S5PC1XX @@ -442,6 +450,7 @@ endchoice config DEBUG_UART_BASE hex "Base address of UART" depends on DEBUG_UART + default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX help This is the base address of your UART for memory-mapped UARTs. @@ -452,6 +461,7 @@ config DEBUG_UART_BASE config DEBUG_UART_CLOCK int "UART input clock" depends on DEBUG_UART + default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX default 0 if DEBUG_MVEBU_A3700_UART help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3cbea8156f..4edd2aa945 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o obj-$(CONFIG_CORTINA_UART) += serial_cortina.o +obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o obj-$(CONFIG_EFI_APP) += serial_efi.o obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += serial_mcf.o diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c new file mode 100644 index 0000000000..b9f35ed36e --- /dev/null +++ b/drivers/serial/serial_sbi.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include + +static inline void _debug_uart_init(void) +{ +} + +static inline void _debug_uart_putc(int c) +{ + if (CONFIG_IS_ENABLED(RISCV_SMODE)) + sbi_console_putchar(c); +} + +DEBUG_UART_FUNCS From 0d625f400bcab5361484a5446aa54133fd6fe213 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 11:05:47 -0500 Subject: [PATCH 006/228] riscv: Fix setting no-map in reserved memory nodes The no-map property is wrongly skipped if a no-map reserved memory node follows one without that property. Fix this by not remembering the absence of a no-map property across loop iterations. Fixes: d4ea649f179a ("riscv: Provide a mechanism to fix DT for reserved memory") Signed-off-by: Samuel Holland Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Atish Patra --- arch/riscv/lib/fdt_fixup.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index f636b28449..61cf893526 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -31,7 +31,6 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) fdt_addr_t addr; fdt_size_t size; int offset, node, err, rmem_offset; - bool nomap = true; char basename[32] = {0}; int bname_len; int max_len = sizeof(basename); @@ -81,9 +80,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) log_err("failed to add reserved memory: %d\n", err); return err; } - if (!fdt_getprop(src, node, "no-map", NULL)) - nomap = false; - if (nomap) { + if (fdt_getprop(src, node, "no-map", NULL)) { rmem_offset = fdt_node_offset_by_phandle(dst, phandle); fdt_setprop_empty(dst, rmem_offset, "no-map"); } From dd573b6b213e859b9d705aabee3ba09e7e7012d2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 11:26:45 -0500 Subject: [PATCH 007/228] riscv: image: Use the first DRAM bank for bootm_low bootm_low is used as a base address is used to allocate space for the FDT blob, initrd, cmdline, etc. when booting Linux. Set the default value for RISC-V to the start of the first DRAM bank, so platforms can get their DRAM layout from the device tree, and do not need to define CONFIG_SYS_SDRAM_BASE. Signed-off-by: Samuel Holland Reviewed-by: Leo Yu-Chi Liang --- common/image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/image.c b/common/image.c index e199d61a4c..8ac57081fd 100644 --- a/common/image.c +++ b/common/image.c @@ -684,7 +684,7 @@ ulong env_get_bootm_low(void) #if defined(CONFIG_SYS_SDRAM_BASE) return CONFIG_SYS_SDRAM_BASE; -#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) +#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) return gd->bd->bi_dram[0].start; #else return 0; From 3fbcfaa6f38c7549553fb8bf31896f205a7bf93a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 12 Sep 2021 21:11:44 +0200 Subject: [PATCH 008/228] riscv: add missing SBI extension definitions Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Sean Anderson Reviewed-by: Bin Meng --- arch/riscv/include/asm/sbi.h | 39 ++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 53ca316180..34a115afc3 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -12,7 +12,6 @@ #include enum sbi_ext_id { -#ifdef CONFIG_SBI_V01 SBI_EXT_0_1_SET_TIMER = 0x0, SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, @@ -22,11 +21,12 @@ enum sbi_ext_id { SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, SBI_EXT_0_1_SHUTDOWN = 0x8, -#endif SBI_EXT_BASE = 0x10, SBI_EXT_TIME = 0x54494D45, SBI_EXT_IPI = 0x735049, SBI_EXT_RFENCE = 0x52464E43, + SBI_EXT_HSM = 0x48534D, + SBI_EXT_SRST = 0x53525354, }; enum sbi_ext_base_fid { @@ -51,6 +51,41 @@ enum sbi_ext_rfence_fid { SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, +}; + +enum sbi_ext_hsm_fid { + SBI_EXT_HSM_HART_START = 0, + SBI_EXT_HSM_HART_STOP, + SBI_EXT_HSM_HART_STATUS, + SBI_EXT_HSM_HART_SUSPEND, +}; + +enum sbi_hsm_hart_status { + SBI_HSM_HART_STATUS_STARTED = 0, + SBI_HSM_HART_STATUS_STOPPED, + SBI_HSM_HART_STATUS_START_PENDING, + SBI_HSM_HART_STATUS_STOP_PENDING, + SBI_HSM_HART_STATUS_SUSPEND_PENDING, + SBI_HSM_HART_STATUS_RESUME_PENDING, +}; + +enum sbi_ext_srst_fid { + SBI_EXT_SRST_RESET = 0, +}; + +enum sbi_srst_reset_type { + SBI_SRST_RESET_TYPE_SHUTDOWN = 0, + SBI_SRST_RESET_TYPE_COLD_REBOOT, + SBI_SRST_RESET_TYPE_WARM_REBOOT, +}; + +enum sbi_srst_reset_reason { + SBI_SRST_RESET_REASON_NONE = 0, + SBI_SRST_RESET_REASON_SYS_FAILURE, }; #ifdef CONFIG_SBI_V01 From 09d7cc3369fcb9a6c86996ae8a58ff5dc34b3798 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 12 Sep 2021 21:11:45 +0200 Subject: [PATCH 009/228] cmd/sbi: use constants instead of numerical values Use constants for extension IDs. Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Bin Meng --- cmd/riscv/sbi.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 90c0811e14..65a2c93290 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -29,21 +29,21 @@ static struct sbi_imp implementations[] = { }; static struct sbi_ext extensions[] = { - { 0x00000000, "sbi_set_timer" }, - { 0x00000001, "sbi_console_putchar" }, - { 0x00000002, "sbi_console_getchar" }, - { 0x00000003, "sbi_clear_ipi" }, - { 0x00000004, "sbi_send_ipi" }, - { 0x00000005, "sbi_remote_fence_i" }, - { 0x00000006, "sbi_remote_sfence_vma" }, - { 0x00000007, "sbi_remote_sfence_vma_asid" }, - { 0x00000008, "sbi_shutdown" }, - { 0x00000010, "SBI Base Functionality" }, - { 0x54494D45, "Timer Extension" }, - { 0x00735049, "IPI Extension" }, - { 0x52464E43, "RFENCE Extension" }, - { 0x0048534D, "Hart State Management Extension" }, - { 0x53525354, "System Reset Extension" }, + { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" }, + { SBI_EXT_0_1_CONSOLE_PUTCHAR, "sbi_console_putchar" }, + { SBI_EXT_0_1_CONSOLE_GETCHAR, "sbi_console_getchar" }, + { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" }, + { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" }, + { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" }, + { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" }, + { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" }, + { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" }, + { SBI_EXT_BASE, "SBI Base Functionality" }, + { SBI_EXT_TIME, "Timer Extension" }, + { SBI_EXT_IPI, "IPI Extension" }, + { SBI_EXT_RFENCE, "RFENCE Extension" }, + { SBI_EXT_HSM, "Hart State Management Extension" }, + { SBI_EXT_SRST, "System Reset Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, From 24ed5317d427bfe278a1329abbf4522dba1025a3 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 12 Sep 2021 21:11:46 +0200 Subject: [PATCH 010/228] sysreset: provide SBI based sysreset driver Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson Reviewed-by: Bin Meng Tested-by: Samuel Holland --- MAINTAINERS | 1 + arch/riscv/cpu/cpu.c | 13 ++++++++- arch/riscv/include/asm/sbi.h | 1 + arch/riscv/lib/sbi.c | 12 ++++++++ drivers/sysreset/Kconfig | 12 ++++++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sbi.c | 51 +++++++++++++++++++++++++++++++++ 7 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 drivers/sysreset/sysreset_sbi.c diff --git a/MAINTAINERS b/MAINTAINERS index 31b49c0a95..71f468c00a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1026,6 +1026,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ F: cmd/riscv/ F: doc/usage/sbi.rst +F: drivers/sysreset/sysreset_sbi.c F: drivers/timer/andes_plmt_timer.c F: drivers/timer/sifive_clint_timer.c F: tools/prelink-riscv.c diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c894ac10b5..8e49b6d736 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -138,7 +139,17 @@ int arch_cpu_init_dm(void) int arch_early_init_r(void) { - return riscv_cpu_probe(); + int ret; + + ret = riscv_cpu_probe(); + if (ret) + return ret; + + if (IS_ENABLED(CONFIG_SYSRESET_SBI)) + device_bind_driver(gd->dm_root, "sbi-sysreset", + "sbi-sysreset", NULL); + + return 0; } /** diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 34a115afc3..5030892b47 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -153,5 +153,6 @@ void sbi_set_timer(uint64_t stime_value); long sbi_get_spec_version(void); int sbi_get_impl_id(void); int sbi_probe_extension(int ext); +void sbi_srst_reset(unsigned long type, unsigned long reason); #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 77845a73ca..2b53896b8a 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -108,6 +108,18 @@ int sbi_probe_extension(int extid) return -ENOTSUPP; } +/** + * sbi_srst_reset() - invoke system reset extension + * + * @type: type of reset + * @reason: reason for reset + */ +void sbi_srst_reset(unsigned long type, unsigned long reason) +{ + sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason, + 0, 0, 0, 0); +} + #ifdef CONFIG_SBI_V01 /** diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index ac77ffbc8b..43a948cfcd 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -85,6 +85,18 @@ config SYSRESET_PSCI Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. +config SYSRESET_SBI + bool "Enable support for SBI System Reset" + depends on RISCV_SMODE && SBI_V02 + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + help + Enable system reset and poweroff via the SBI system reset extension. + The extension was introduced in version 0.3 of the SBI specification. + + If the SBI implementation provides the extension, is board specific. + The RISC-V platform specification mandates the extension for rich + operating system platforms. + config SYSRESET_SOCFPGA bool "Enable support for Intel SOCFPGA family" depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index de81c399d7..8e00be0779 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o +obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o diff --git a/drivers/sysreset/sysreset_sbi.c b/drivers/sysreset/sysreset_sbi.c new file mode 100644 index 0000000000..5e8090d62b --- /dev/null +++ b/drivers/sysreset/sysreset_sbi.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021, Heinrich Schuchardt + */ + +#include +#include +#include +#include +#include +#include + +static enum sbi_srst_reset_type reset_type_map[SYSRESET_COUNT] = { + [SYSRESET_WARM] = SBI_SRST_RESET_TYPE_WARM_REBOOT, + [SYSRESET_COLD] = SBI_SRST_RESET_TYPE_COLD_REBOOT, + [SYSRESET_POWER] = SBI_SRST_RESET_TYPE_COLD_REBOOT, + [SYSRESET_POWER_OFF] = SBI_SRST_RESET_TYPE_SHUTDOWN, +}; + +static int sbi_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + enum sbi_srst_reset_type reset_type; + + reset_type = reset_type_map[type]; + sbi_srst_reset(reset_type, SBI_SRST_RESET_REASON_NONE); + + return -EINPROGRESS; +} + +static int sbi_sysreset_probe(struct udevice *dev) +{ + long have_reset; + + have_reset = sbi_probe_extension(SBI_EXT_SRST); + if (have_reset) + return 0; + + log_warning("SBI has no system reset extension\n"); + return -ENOENT; +} + +static struct sysreset_ops sbi_sysreset_ops = { + .request = sbi_sysreset_request, +}; + +U_BOOT_DRIVER(sbi_sysreset) = { + .name = "sbi-sysreset", + .id = UCLASS_SYSRESET, + .ops = &sbi_sysreset_ops, + .probe = sbi_sysreset_probe, +}; From b11f42015f82904f72cbd5a25032c0d82402a423 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 12 Sep 2021 21:11:47 +0200 Subject: [PATCH 011/228] configs: enable SYSRESET_SBI on qemu-riscvXX_smode_defconfig There should be a platform compiled with the new driver. Enable CONFIG_SYSRESET_SBI for all QEMU boards using SBI. If you want to test the SBI sysreset driver, disable CONFIG_SYSRESET_SYSCON. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index f13661e2ed..a009f62369 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -15,3 +15,4 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index da7a4d2c80..aac6f389a7 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -17,3 +17,4 @@ CONFIG_CMD_SBI=y CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 63b205d2a7..db2f21d8db 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -18,3 +18,4 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 96f2e3ae5d..cf33870135 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -18,3 +18,4 @@ CONFIG_CMD_SBI=y CONFIG_OF_PRIOR_STAGE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_SYSRESET_SBI=y From 1b2b52f29402b5aaccccadfe4ba11bd3f29bd414 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Thu, 23 Sep 2021 10:34:29 +0800 Subject: [PATCH 012/228] riscv: ae350: enable Coherence Manager for ae350 If Coherence Manager were not set in the beginning, u-boot-spl would sometimes fail to boot to u-boot proper. Enable CM and I/D cache at the same time in harts_early_init Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/cpu/ax25/cpu.c | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index f092600e14..c4c2de2ef0 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -9,6 +9,22 @@ #include #include #include +#include + +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 + +#define V5_MCACHE_CTL_IC_EN_OFFSET 0 +#define V5_MCACHE_CTL_DC_EN_OFFSET 1 +#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 +#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 + +#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) +#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) +#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) +#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) + /* * cleanup_before_linux() is called just before we call linux @@ -27,3 +43,29 @@ int cleanup_before_linux(void) return 0; } + +void harts_early_init(void) +{ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + + if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) + mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; + if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) + mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; + if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) + mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; + csr_write(CSR_MCACHE_CTL, mcache_ctl_val); + + /* + * Check DC_COHEN_EN, if cannot write to mcache_ctl, + * we assume this bitmap not support L2 CM + */ + mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { + /* Wait for DC_COHSTA bit be set */ + while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) + mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + } + } +} From ea36f110f72bc7557ff8935799f35a48f5c928d0 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Fri, 20 Aug 2021 02:18:36 +0000 Subject: [PATCH 013/228] ARM: meson: Add S905Y2 SOC ID Add the SOC ID for the S905Y2 to board info, see below for before/after tested with a Radxa Zero board: SoC: Amlogic Meson G12A (Unknown) Revision 28:b (30:2) SoC: Amlogic Meson G12A (S905Y2) Revision 28:b (30:2) Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong --- arch/arm/mach-meson/board-info.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c index d16d3f194d..2421acd817 100644 --- a/arch/arm/mach-meson/board-info.c +++ b/arch/arm/mach-meson/board-info.c @@ -64,6 +64,7 @@ static const struct meson_gx_package_id { { "A113X", 0x25, 0x37, 0xff }, { "A113D", 0x25, 0x22, 0xff }, { "S905D2", 0x28, 0x10, 0xf0 }, + { "S905Y2", 0x28, 0x30, 0xf0 }, { "S905X2", 0x28, 0x40, 0xf0 }, { "A311D", 0x29, 0x10, 0xf0 }, { "S922X", 0x29, 0x40, 0xf0 }, From d6c10360dcb4c64ba0877f07bd860dc70db86ee8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Sep 2021 14:32:12 +0200 Subject: [PATCH 014/228] pci: pcie_dw_meson: fix usb fail when pci link fails to go up On Amlogic A311D, when the PCIe link fails disabling the related clocks makes USB fail. For an unknown reason, this doesn happen on the S905D3 SoC. Mimic the Linux behavior by not considering a link failure a probe failure, and continue even if the PCIe link is down. Reported-by: Art Nikpal Signed-off-by: Neil Armstrong Reviewed-by: Bin Meng --- drivers/pci/pcie_dw_meson.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c index 0525ecbea6..07da9fa533 100644 --- a/drivers/pci/pcie_dw_meson.c +++ b/drivers/pci/pcie_dw_meson.c @@ -319,15 +319,9 @@ static int meson_pcie_init_port(struct udevice *dev) pcie_dw_setup_host(&priv->dw); - ret = meson_pcie_link_up(priv, LINK_SPEED_GEN_2); - if (ret < 0) - goto err_link_up; + meson_pcie_link_up(priv, LINK_SPEED_GEN_2); return 0; -err_link_up: - clk_disable(&priv->clk_port); - clk_disable(&priv->clk_general); - clk_disable(&priv->clk_pclk); err_deassert_bulk: reset_assert_bulk(&priv->rsts); err_power_off_phy: From 2e8d47c641aa951c8d8a7f401e2c652af1355f28 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:00 +0200 Subject: [PATCH 015/228] ARM: meson: Sync Amlogic DT from Linux 5.14 Import Amlogic DT changes from Linux commit 7d2a07b76933 ("Linux 5.14"), dt-bindings clock changes and new meson-g12b-gsking-x.dts, meson-sm1-bananapi-m5 & odroid-hc4 boards. Signed-off-by: Neil Armstrong --- arch/arm/dts/Makefile | 3 + arch/arm/dts/meson-axg-s400.dts | 16 + arch/arm/dts/meson-axg.dtsi | 181 +++++ arch/arm/dts/meson-g12-common.dtsi | 31 +- arch/arm/dts/meson-g12a-sei510.dts | 2 +- arch/arm/dts/meson-g12b-gsking-x.dts | 133 ++++ arch/arm/dts/meson-g12b-gtking-pro.dts | 23 +- arch/arm/dts/meson-g12b-gtking.dts | 22 +- arch/arm/dts/meson-g12b-odroid-n2-plus.dts | 2 +- arch/arm/dts/meson-g12b-odroid-n2.dtsi | 74 +- arch/arm/dts/meson-g12b-w400.dtsi | 2 +- arch/arm/dts/meson-g12b.dtsi | 4 + arch/arm/dts/meson-gx-libretech-pc.dtsi | 2 +- arch/arm/dts/meson-gx-p23x-q20x.dtsi | 2 +- arch/arm/dts/meson-gx.dtsi | 7 + arch/arm/dts/meson-gxbb-nanopi-k2.dts | 42 +- arch/arm/dts/meson-gxbb-odroidc2.dts | 44 +- arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 2 +- arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 50 +- .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 6 +- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 2 +- arch/arm/dts/meson-gxm-khadas-vim2.dts | 55 +- arch/arm/dts/meson-gxm-wetek-core2.dts | 2 +- arch/arm/dts/meson-gxm.dtsi | 20 + arch/arm/dts/meson-khadas-vim3.dtsi | 73 +- arch/arm/dts/meson-sm1-bananapi-m5.dts | 646 ++++++++++++++++++ arch/arm/dts/meson-sm1-khadas-vim3l.dts | 20 +- arch/arm/dts/meson-sm1-odroid-c4.dts | 448 +----------- arch/arm/dts/meson-sm1-odroid-hc4.dts | 140 ++++ arch/arm/dts/meson-sm1-odroid.dtsi | 449 ++++++++++++ arch/arm/dts/meson-sm1-sei610.dts | 10 +- arch/arm/dts/meson-sm1.dtsi | 12 +- include/dt-bindings/clock/axg-clkc.h | 26 +- include/dt-bindings/clock/g12a-clkc.h | 2 + 34 files changed, 2030 insertions(+), 523 deletions(-) create mode 100644 arch/arm/dts/meson-g12b-gsking-x.dts create mode 100644 arch/arm/dts/meson-sm1-bananapi-m5.dts create mode 100644 arch/arm/dts/meson-sm1-odroid-hc4.dts create mode 100644 arch/arm/dts/meson-sm1-odroid.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9438bf735a..7c251853ea 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -177,11 +177,14 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-g12a-sei510.dtb \ meson-g12b-gtking.dtb \ meson-g12b-gtking-pro.dtb \ + meson-g12b-gsking-x.dtb \ meson-g12b-odroid-n2.dtb \ meson-g12b-odroid-n2-plus.dtb \ meson-g12b-a311d-khadas-vim3.dtb \ + meson-sm1-bananapi-m5.dtb \ meson-sm1-khadas-vim3l.dtb \ meson-sm1-odroid-c4.dtb \ + meson-sm1-odroid-hc4.dtb \ meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts index cb1360ae12..359589d1df 100644 --- a/arch/arm/dts/meson-axg-s400.dts +++ b/arch/arm/dts/meson-axg-s400.dts @@ -441,6 +441,16 @@ status = "okay"; }; +&pcieA { + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieB { + reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + &pwm_ab { status = "okay"; pinctrl-0 = <&pwm_a_x20_pins>; @@ -584,3 +594,9 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&usb { + status = "okay"; + dr_mode = "otg"; + vbus-supply = <&usb_pwr>; +}; diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi index b9efc84692..3f5254eeb4 100644 --- a/arch/arm/dts/meson-axg.dtsi +++ b/arch/arm/dts/meson-axg.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-axg"; @@ -171,6 +172,98 @@ #size-cells = <2>; ranges; + pcieA: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xf9800000 0x0 0x400000>, + <0x0 0xff646000 0x0 0x2000>, + <0x0 0xf9f00000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; + clock-names = "general", "pclk", "port"; + resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; + reset-names = "port", "apb"; + num-lanes = <1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + status = "disabled"; + }; + + pcieB: pcie@fa000000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xfa000000 0x0 0x400000>, + <0x0 0xff648000 0x0 0x2000>, + <0x0 0xfa400000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; + clock-names = "general", "pclk", "port"; + resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; + reset-names = "port", "apb"; + num-lanes = <1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + status = "disabled"; + }; + + usb: usb@ffe09080 { + compatible = "amlogic,meson-axg-usb-ctrl"; + reg = <0x0 0xffe09080 0x0 0x20>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "usb_ctrl", "ddr"; + resets = <&reset RESET_USB_OTG>; + + dr_mode = "otg"; + + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; + + dwc2: usb@ff400000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1>; + clock-names = "otg"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@ff500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff500000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + }; + }; + ethmac: ethernet@ff3f0000 { compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.70a", @@ -187,9 +280,19 @@ "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; + power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; status = "disabled"; }; + pcie_phy: phy@ff644000 { + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x1c>; + resets = <&reset RESET_PCIE_PHY>; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + }; + pdm: audio-controller@ff632000 { compatible = "amlogic,axg-pdm"; reg = <0x0 0xff632000 0x0 0x34>; @@ -1117,6 +1220,52 @@ clocks = <&xtal>; clock-names = "xtal"; }; + + pwrc: power-controller { + compatible = "amlogic,meson-axg-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + reset-names = "viu", "venc", "vcbus", + "vencl", "vid_lock"; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <250000000>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ + }; + + mipi_pcie_analog_dphy: phy { + compatible = "amlogic,axg-mipi-pcie-analog-phy"; + #phy-cells = <0>; + status = "disabled"; + }; }; }; @@ -1129,6 +1278,19 @@ #mbox-cells = <1>; }; + mipi_dphy: phy@ff640000 { + compatible = "amlogic,axg-mipi-dphy"; + reg = <0x0 0xff640000 0x0 0x100>; + clocks = <&clkc CLKID_MIPI_DSI_PHY>; + clock-names = "pclk"; + resets = <&reset RESET_MIPI_PHY>; + reset-names = "phy"; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + status = "disabled"; + }; + audio: bus@ff642000 { compatible = "simple-bus"; reg = <0x0 0xff642000 0x0 0x2000>; @@ -1563,6 +1725,14 @@ }; }; + ge2d: ge2d@ff940000 { + compatible = "amlogic,axg-ge2d"; + reg = <0x0 0xff940000 0x0 0x10000>; + interrupts = ; + clocks = <&clkc CLKID_VAPB>; + resets = <&reset RESET_GE2D>; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; reg = <0x0 0xffc01000 0 0x1000>, @@ -1701,6 +1871,7 @@ status = "disabled"; clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; + fifo-size = <128>; }; }; @@ -1734,6 +1905,16 @@ clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; }; + + usb2_phy1: phy@9020 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x9020 0x0 0x20>; + clocks = <&clkc CLKID_USB>; + clock-names = "phy"; + resets = <&reset RESET_USB_OTG>; + reset-names = "phy"; + }; }; sram: sram@fffc0000 { diff --git a/arch/arm/dts/meson-g12-common.dtsi b/arch/arm/dts/meson-g12-common.dtsi index 1e83ec5b8c..00c6f53290 100644 --- a/arch/arm/dts/meson-g12-common.dtsi +++ b/arch/arm/dts/meson-g12-common.dtsi @@ -17,6 +17,12 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + mmc0 = &sd_emmc_b; /* SD card */ + mmc1 = &sd_emmc_c; /* eMMC */ + mmc2 = &sd_emmc_a; /* SDIO */ + }; + chosen { #address-cells = <2>; #size-cells = <2>; @@ -122,9 +128,9 @@ pcie: pcie@fc000000 { compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; - reg = <0x0 0xfc000000 0x0 0x400000 - 0x0 0xff648000 0x0 0x2000 - 0x0 0xfc400000 0x0 0x200000>; + reg = <0x0 0xfc000000 0x0 0x400000>, + <0x0 0xff648000 0x0 0x2000>, + <0x0 0xfc400000 0x0 0x200000>; reg-names = "elbi", "cfg", "config"; interrupts = ; #interrupt-cells = <1>; @@ -134,8 +140,8 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 - 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; + ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, + <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; clocks = <&clkc CLKID_PCIE_PHY &clkc CLKID_PCIE_COMB @@ -209,7 +215,7 @@ }; ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", + compatible = "amlogic,meson-g12a-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = <0x0 0xff3f0000 0x0 0x10000>, @@ -282,6 +288,8 @@ hwrng: rng@218 { compatible = "amlogic,meson-rng"; reg = <0x0 0x218 0x0 0x4>; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; }; }; @@ -2001,7 +2009,7 @@ }; }; - vrtc: rtc@0a8 { + vrtc: rtc@a8 { compatible = "amlogic,meson-vrtc"; reg = <0x0 0x000a8 0x0 0x4>; }; @@ -2179,6 +2187,12 @@ amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; }; + watchdog: watchdog@f0d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0xf0d0 0x0 0x10>; + clocks = <&xtal>; + }; + spicc0: spi@13000 { compatible = "amlogic,meson-g12a-spicc"; reg = <0x0 0x13000 0x0 0x44>; @@ -2303,6 +2317,7 @@ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; + fifo-size = <128>; }; }; @@ -2380,7 +2395,7 @@ interrupts = ; dr_mode = "host"; snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment; + snps,quirk-frame-length-adjustment = <0x20>; snps,parkmode-disable-ss-quirk; }; }; diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts index b00d0468c7..81269ccc24 100644 --- a/arch/arm/dts/meson-g12a-sei510.dts +++ b/arch/arm/dts/meson-g12a-sei510.dts @@ -181,7 +181,7 @@ sound { compatible = "amlogic,axg-sound-card"; - model = "G12A-SEI510"; + model = "SEI510"; audio-aux-devs = <&tdmout_a>, <&tdmout_b>, <&tdmin_a>, <&tdmin_b>; audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", diff --git a/arch/arm/dts/meson-g12b-gsking-x.dts b/arch/arm/dts/meson-g12b-gsking-x.dts new file mode 100644 index 0000000000..6c7bfacbad --- /dev/null +++ b/arch/arm/dts/meson-g12b-gsking-x.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (c) 2019 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-w400.dtsi" +#include +#include + +/ { + compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b"; + model = "Beelink GS-King X"; + + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + power-button { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "GSKING-X"; + audio-aux-devs = <&tdmout_a>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1", + "TDMOUT_A IN 1", "FRDDR_B OUT 1", + "TDMOUT_A IN 2", "FRDDR_C OUT 1", + "TDM_A Playback", "TDMOUT_A OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_a>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; + }; + }; + + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + +&tdmif_a { + status = "okay"; +}; + +&tdmout_a { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-g12b-gtking-pro.dts b/arch/arm/dts/meson-g12b-gtking-pro.dts index f0c56a16af..707daf9278 100644 --- a/arch/arm/dts/meson-g12b-gtking-pro.dts +++ b/arch/arm/dts/meson-g12b-gtking-pro.dts @@ -11,9 +11,14 @@ #include / { - compatible = "azw,gtking", "amlogic,g12b"; + compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; model = "Beelink GT-King Pro"; + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -30,7 +35,7 @@ leds { compatible = "gpio-leds"; - white { + led-white { label = "power:white"; gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; default-state = "on"; @@ -39,7 +44,7 @@ sound { compatible = "amlogic,axg-sound-card"; - model = "G12B-GTKING-PRO"; + model = "GTKING-PRO"; audio-aux-devs = <&tdmout_b>; audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", "TDMOUT_B IN 1", "FRDDR_B OUT 1", @@ -112,6 +117,18 @@ status = "okay"; }; +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &tdmif_b { status = "okay"; }; diff --git a/arch/arm/dts/meson-g12b-gtking.dts b/arch/arm/dts/meson-g12b-gtking.dts index eeb7bc5539..5d96c14490 100644 --- a/arch/arm/dts/meson-g12b-gtking.dts +++ b/arch/arm/dts/meson-g12b-gtking.dts @@ -11,9 +11,14 @@ #include / { - compatible = "azw,gtking", "amlogic,g12b"; + compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; model = "Beelink GT-King"; + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + spdif_dit: audio-codec-1 { #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; @@ -23,7 +28,7 @@ sound { compatible = "amlogic,axg-sound-card"; - model = "G12B-GTKING"; + model = "GTKING"; audio-aux-devs = <&tdmout_b>; audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", "TDMOUT_B IN 1", "FRDDR_B OUT 1", @@ -122,6 +127,19 @@ status = "okay"; }; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &spdifout { pinctrl-0 = <&spdif_out_h_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts index 5de2815ba9..ce1198ad34 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts +++ b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts @@ -19,7 +19,7 @@ regulator-min-microvolt = <680000>; regulator-max-microvolt = <1040000>; - pwms = <&pwm_AO_cd 1 1500 0>; + pwms = <&pwm_ab 0 1500 0>; }; &vddcpu_b { diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi b/arch/arm/dts/meson-g12b-odroid-n2.dtsi index 6982632ae6..344573e157 100644 --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi +++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi @@ -13,6 +13,8 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + rtc0 = &rtc; + rtc1 = &vrtc; }; dioo2133: audio-amplifier-0 { @@ -40,7 +42,7 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { label = "n2:blue"; gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -211,7 +213,7 @@ sound { compatible = "amlogic,axg-sound-card"; - model = "G12B-ODROID-N2"; + model = "ODROID-N2"; audio-widgets = "Line", "Lineout"; audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, @@ -408,12 +410,12 @@ &ext_mdio { external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; @@ -444,13 +446,58 @@ }; &gpio { + gpio-line-names = + /* GPIOZ */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* GPIOH */ + "", "", "", "", "", "", "", "", + "", + /* BOOT */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* GPIOC */ + "", "", "", "", "", "", "", "", + /* GPIOA */ + "PIN_44", /* GPIOA_0 */ + "PIN_46", /* GPIOA_1 */ + "PIN_45", /* GPIOA_2 */ + "PIN_47", /* GPIOA_3 */ + "PIN_26", /* GPIOA_4 */ + "", "", "", "", "", "", + "PIN_42", /* GPIOA_11 */ + "PIN_32", /* GPIOA_12 */ + "PIN_7", /* GPIOA_13 */ + "PIN_27", /* GPIOA_14 */ + "PIN_28", /* GPIOA_15 */ + /* GPIOX */ + "PIN_16", /* GPIOX_0 */ + "PIN_18", /* GPIOX_1 */ + "PIN_22", /* GPIOX_2 */ + "PIN_11", /* GPIOX_3 */ + "PIN_13", /* GPIOX_4 */ + "PIN_33", /* GPIOX_5 */ + "PIN_35", /* GPIOX_6 */ + "PIN_15", /* GPIOX_7 */ + "PIN_19", /* GPIOX_8 */ + "PIN_21", /* GPIOX_9 */ + "PIN_24", /* GPIOX_10 */ + "PIN_23", /* GPIOX_11 */ + "PIN_8", /* GPIOX_12 */ + "PIN_10", /* GPIOX_13 */ + "PIN_29", /* GPIOX_14 */ + "PIN_31", /* GPIOX_15 */ + "PIN_12", /* GPIOX_16 */ + "PIN_3", /* GPIOX_17 */ + "PIN_5", /* GPIOX_18 */ + "PIN_36"; /* GPIOX_19 */ /* * WARNING: The USB Hub on the Odroid-N2 needs a reset signal * to be turned high in order to be detected by the USB Controller * This signal should be handled by a USB specific power sequence * in order to reset the Hub when USB bus is powered down. */ - usb-hub { + hog-0 { gpio-hog; gpios = ; output-high; @@ -478,6 +525,18 @@ linux,rc-map-name = "rc-odroid"; }; +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; @@ -494,6 +553,11 @@ status = "okay"; }; +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + /* SD card */ &sd_emmc_b { status = "okay"; diff --git a/arch/arm/dts/meson-g12b-w400.dtsi b/arch/arm/dts/meson-g12b-w400.dtsi index 2802ddbb83..feb0885047 100644 --- a/arch/arm/dts/meson-g12b-w400.dtsi +++ b/arch/arm/dts/meson-g12b-w400.dtsi @@ -264,7 +264,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi index 9b8548e5f6..ee8fcae9f9 100644 --- a/arch/arm/dts/meson-g12b.dtsi +++ b/arch/arm/dts/meson-g12b.dtsi @@ -135,3 +135,7 @@ }; }; }; + +&mali { + dma-coherent; +}; diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi b/arch/arm/dts/meson-gx-libretech-pc.dtsi index c2480bab8d..2d7032f41e 100644 --- a/arch/arm/dts/meson-gx-libretech-pc.dtsi +++ b/arch/arm/dts/meson-gx-libretech-pc.dtsi @@ -186,7 +186,7 @@ sound { compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S9XX-PC"; + model = "LIBRETECH-PC"; audio-aux-devs = <&dio2133>; audio-widgets = "Speaker", "7J4-14 LEFT", "Speaker", "7J4-11 RIGHT"; diff --git a/arch/arm/dts/meson-gx-p23x-q20x.dtsi b/arch/arm/dts/meson-gx-p23x-q20x.dtsi index 6b57e15aad..dafc841f7c 100644 --- a/arch/arm/dts/meson-gx-p23x-q20x.dtsi +++ b/arch/arm/dts/meson-gx-p23x-q20x.dtsi @@ -121,7 +121,7 @@ sound { compatible = "amlogic,gx-sound-card"; - model = "GX-P230-Q200"; + model = "P230-Q200"; audio-aux-devs = <&dio2133>; audio-widgets = "Line", "Lineout"; audio-routing = "AU2 INL", "ACODEC LOLP", diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 0edd137151..6b457b2c30 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -20,6 +20,12 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + mmc0 = &sd_emmc_b; /* SD card */ + mmc1 = &sd_emmc_c; /* eMMC */ + mmc2 = &sd_emmc_a; /* SDIO */ + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -295,6 +301,7 @@ reg = <0x0 0x84c0 0x0 0x18>; interrupts = ; status = "disabled"; + fifo-size = <128>; }; uart_B: serial@84dc { diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts index 7be3e35409..7273eed529 100644 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts @@ -7,6 +7,7 @@ #include "meson-gxbb.dtsi" #include +#include / { compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; @@ -130,6 +131,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "NANOPI-K2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -165,7 +205,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index 70fcfb7b06..201596247f 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -9,6 +9,7 @@ #include "meson-gxbb.dtsi" #include +#include / { compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; @@ -172,6 +173,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "ODROID-C2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -200,7 +240,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; @@ -217,7 +257,7 @@ * This signal should be handled by a USB specific power sequence * in order to reset the Hub when USB bus is powered down. */ - usb-hub { + hog-0 { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts index 9e43f4dca9..2d769203f6 100644 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts @@ -118,7 +118,7 @@ sound { compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S805X-AC"; + model = "LIBRETECH-AC"; audio-widgets = "Speaker", "9J5-3 LEFT", "Speaker", "9J5-2 RIGHT"; audio-routing = "9J5-3 LEFT", "ACODEC LOLN", diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts index 8bcdffdf55..60feac0179 100644 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts @@ -5,9 +5,9 @@ /dts-v1/; -#include - #include "meson-gxl-s905x-p212.dtsi" +#include +#include / { compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; @@ -42,10 +42,10 @@ }; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - power { + led-1 { label = "vim:red:power"; pwms = <&pwm_AO_ab 1 7812500 0>; max-brightness = <255>; @@ -63,6 +63,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "KHADAS-VIM"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -97,8 +136,7 @@ pinctrl-names = "default"; rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; + status = "okay"; compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts index 675eaa8796..93d8f8aff7 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts @@ -84,7 +84,6 @@ regulator-always-on; }; - vcck: regulator-vcck { compatible = "regulator-fixed"; regulator-name = "VCCK"; @@ -124,7 +123,6 @@ regulator-always-on; }; - vddio_card: regulator-vddio-card { compatible = "regulator-gpio"; regulator-name = "VDDIO_CARD"; @@ -161,7 +159,7 @@ sound { compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S905X-CC-V2"; + model = "LIBRETECH-CC-V2"; assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; @@ -195,7 +193,6 @@ }; }; - &aiu { status = "okay"; }; @@ -207,7 +204,6 @@ hdmi-phandle = <&hdmi_tx>; }; - ðmac { status = "okay"; }; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts index 5ae7bb6209..82bfabfbd3 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -135,7 +135,7 @@ sound { compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S905X-CC"; + model = "LIBRETECH-CC"; audio-aux-devs = <&dio2133>; audio-widgets = "Line", "Lineout"; audio-routing = "AU2 INL", "ACODEC LOLN", diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index bff8ec2c1c..18a4b7a6c5 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -7,9 +7,9 @@ /dts-v1/; -#include - #include "meson-gxm.dtsi" +#include +#include / { compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; @@ -81,10 +81,10 @@ }; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - power { + led-1 { label = "vim:red:power"; pwms = <&pwm_AO_ab 1 7812500 0>; max-brightness = <255>; @@ -145,6 +145,45 @@ clock-frequency = <32768>; pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "KHADAS-VIM2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -154,7 +193,6 @@ hdmi-phandle = <&hdmi_tx>; }; - &cpu_cooling_maps { map0 { cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; @@ -194,7 +232,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; @@ -228,8 +266,7 @@ pinctrl-names = "default"; rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; + status = "okay"; compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; @@ -341,7 +378,7 @@ #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <3000000>; + spi-max-frequency = <104000000>; }; }; diff --git a/arch/arm/dts/meson-gxm-wetek-core2.dts b/arch/arm/dts/meson-gxm-wetek-core2.dts index ec794c134c..1e7f77f9b5 100644 --- a/arch/arm/dts/meson-gxm-wetek-core2.dts +++ b/arch/arm/dts/meson-gxm-wetek-core2.dts @@ -22,7 +22,7 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { color = ; function = LED_FUNCTION_STATUS; gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi index fe41451122..411cc312fc 100644 --- a/arch/arm/dts/meson-gxm.dtsi +++ b/arch/arm/dts/meson-gxm.dtsi @@ -42,11 +42,28 @@ }; }; + cpu0: cpu@0 { + capacity-dmips-mhz = <1024>; + }; + + cpu1: cpu@1 { + capacity-dmips-mhz = <1024>; + }; + + cpu2: cpu@2 { + capacity-dmips-mhz = <1024>; + }; + + cpu3: cpu@3 { + capacity-dmips-mhz = <1024>; + }; + cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -57,6 +74,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -67,6 +85,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -77,6 +96,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi index 7b46555ac5..3cf4ecb6d5 100644 --- a/arch/arm/dts/meson-khadas-vim3.dtsi +++ b/arch/arm/dts/meson-khadas-vim3.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -13,6 +14,8 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + rtc0 = &rtc; + rtc1 = &vrtc; }; chosen { @@ -41,13 +44,15 @@ compatible = "gpio-leds"; led-white { - label = "vim3:white:sys"; + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-red { - label = "vim3:red"; + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; }; }; @@ -165,12 +170,17 @@ sound { compatible = "amlogic,axg-sound-card"; - model = "G12B-KHADAS-VIM3"; - audio-aux-devs = <&tdmout_a>; + model = "KHADAS-VIM3"; + audio-aux-devs = <&tdmin_a>, <&tdmout_a>; audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", "TDMOUT_A IN 1", "FRDDR_B OUT 0", "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT"; + "TDM_A Playback", "TDMOUT_A OUT", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 3", "TDM_A Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT"; assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, @@ -193,8 +203,20 @@ sound-dai = <&frddr_c>; }; - /* 8ch hdmi interface */ dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { sound-dai = <&tdmif_a>; dai-format = "i2s"; dai-tdm-slot-tx-mask-0 = <1 1>; @@ -209,7 +231,7 @@ }; /* hdmi glue */ - dai-link-4 { + dai-link-7 { sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; codec { @@ -278,12 +300,12 @@ }; ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; }; &frddr_a { @@ -330,7 +352,7 @@ #gpio-cells = <2>; }; - rtc@51 { + rtc: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; @@ -349,9 +371,9 @@ }; &pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; }; &saradc { @@ -445,15 +467,30 @@ }; }; - &tdmif_a { status = "okay"; }; +&tdmin_a { + status = "okay"; +}; + &tdmout_a { status = "okay"; }; +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + &tohdmitx { status = "okay"; }; diff --git a/arch/arm/dts/meson-sm1-bananapi-m5.dts b/arch/arm/dts/meson-sm1-bananapi-m5.dts new file mode 100644 index 0000000000..effaa138b5 --- /dev/null +++ b/arch/arm/dts/meson-sm1-bananapi-m5.dts @@ -0,0 +1,646 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 BayLibre SAS + * Author: Neil Armstrong + */ + +/dts-v1/; + +#include "meson-sm1.dtsi" +#include +#include +#include +#include +#include + +/ { + compatible = "bananapi,bpi-m5", "amlogic,sm1"; + model = "Banana Pi BPI-M5"; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + key { + label = "SW3"; + linux,code = ; + press-threshold-microvolt = <1700000>; + }; + }; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* TOFIX: handle CVBS_DET on SARADC channel 0 */ + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "SW1"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + + blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddio_c: regulator-vddio_c { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_C"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + + gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; + gpios-states = <1>; + + states = <1800000 0>, + <3300000 1>; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + /* USB Hub Power Enable */ + vl_pwr_en: regulator-vl_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "VL_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "BPI-M5"; + audio-widgets = "Line", "Lineout"; + audio-aux-devs = <&tdmout_b>, <&tdmout_c>, + <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 4", "TDM_B Loopback", + "TDMIN_B IN 4", "TDM_B Loopback", + "TDMIN_C IN 4", "TDM_B Loopback", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 5", "TDM_C Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "Lineout", "ACODEC LOLP", + "Lineout", "ACODEC LORP"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_B>; + }; + }; + + /* i2s jack output interface */ + dai-link-7 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_C>; + }; + }; + + /* hdmi glue */ + dai-link-8 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + + /* acodec glue */ + dai-link-9 { + sound-dai = <&toacodec TOACODEC_OUT>; + + codec { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddao_1v8>; + status = "okay"; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + gpio-line-names = + /* GPIOZ */ + "ETH_MDIO", /* GPIOZ_0 */ + "ETH_MDC", /* GPIOZ_1 */ + "ETH_RXCLK", /* GPIOZ_2 */ + "ETH_RX_DV", /* GPIOZ_3 */ + "ETH_RXD0", /* GPIOZ_4 */ + "ETH_RXD1", /* GPIOZ_5 */ + "ETH_RXD2", /* GPIOZ_6 */ + "ETH_RXD3", /* GPIOZ_7 */ + "ETH_TXCLK", /* GPIOZ_8 */ + "ETH_TXEN", /* GPIOZ_9 */ + "ETH_TXD0", /* GPIOZ_10 */ + "ETH_TXD1", /* GPIOZ_11 */ + "ETH_TXD2", /* GPIOZ_12 */ + "ETH_TXD3", /* GPIOZ_13 */ + "ETH_INTR", /* GPIOZ_14 */ + "ETH_NRST", /* GPIOZ_15 */ + /* GPIOH */ + "HDMI_SDA", /* GPIOH_0 */ + "HDMI_SCL", /* GPIOH_1 */ + "HDMI_HPD", /* GPIOH_2 */ + "HDMI_CEC", /* GPIOH_3 */ + "VL-RST_N", /* GPIOH_4 */ + "CON1-P36", /* GPIOH_5 */ + "VL-PWREN", /* GPIOH_6 */ + "WiFi_3V3_1V8", /* GPIOH_7 */ + "TFLASH_VDD_EN", /* GPIOH_8 */ + /* BOOT */ + "eMMC_D0", /* BOOT_0 */ + "eMMC_D1", /* BOOT_1 */ + "eMMC_D2", /* BOOT_2 */ + "eMMC_D3", /* BOOT_3 */ + "eMMC_D4", /* BOOT_4 */ + "eMMC_D5", /* BOOT_5 */ + "eMMC_D6", /* BOOT_6 */ + "eMMC_D7", /* BOOT_7 */ + "eMMC_CLK", /* BOOT_8 */ + "", + "eMMC_CMD", /* BOOT_10 */ + "", + "eMMC_RST#", /* BOOT_12 */ + "eMMC_DS", /* BOOT_13 */ + /* GPIOC */ + "SD_D0_B", /* GPIOC_0 */ + "SD_D1_B", /* GPIOC_1 */ + "SD_D2_B", /* GPIOC_2 */ + "SD_D3_B", /* GPIOC_3 */ + "SD_CLK_B", /* GPIOC_4 */ + "SD_CMD_B", /* GPIOC_5 */ + "CARD_EN_DET", /* GPIOC_6 */ + "", + /* GPIOA */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", + "CON1-P27", /* GPIOA_14 */ + "CON1-P28", /* GPIOA_15 */ + /* GPIOX */ + "CON1-P16", /* GPIOX_0 */ + "CON1-P18", /* GPIOX_1 */ + "CON1-P22", /* GPIOX_2 */ + "CON1-P11", /* GPIOX_3 */ + "CON1-P13", /* GPIOX_4 */ + "CON1-P07", /* GPIOX_5 */ + "CON1-P33", /* GPIOX_6 */ + "CON1-P15", /* GPIOX_7 */ + "CON1-P19", /* GPIOX_8 */ + "CON1-P21", /* GPIOX_9 */ + "CON1-P24", /* GPIOX_10 */ + "CON1-P23", /* GPIOX_11 */ + "CON1-P08", /* GPIOX_12 */ + "CON1-P10", /* GPIOX_13 */ + "CON1-P29", /* GPIOX_14 */ + "CON1-P31", /* GPIOX_15 */ + "CON1-P26", /* GPIOX_16 */ + "CON1-P03", /* GPIOX_17 */ + "CON1-P05", /* GPIOX_18 */ + "CON1-P32"; /* GPIOX_19 */ + + /* + * WARNING: The USB Hub on the BPI-M5 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = ; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&gpio_ao { + gpio-line-names = + /* GPIOAO */ + "DEBUG TX", /* GPIOAO_0 */ + "DEBUG RX", /* GPIOAO_1 */ + "SYS_LED2", /* GPIOAO_2 */ + "UPDATE_KEY", /* GPIOAO_3 */ + "CON1-P40", /* GPIOAO_4 */ + "IR_IN", /* GPIOAO_5 */ + "TF_3V3N_1V8_EN", /* GPIOAO_6 */ + "CON1-P35", /* GPIOAO_7 */ + "CON1-P12", /* GPIOAO_8 */ + "CON1-P37", /* GPIOAO_9 */ + "CON1-P38", /* GPIOAO_10 */ + "SYS_LED", /* GPIOAO_11 */ + /* GPIOE */ + "VDDEE_PWM", /* GPIOE_0 */ + "VDDCPU_PWM", /* GPIOE_1 */ + "TF_PWR_EN"; /* GPIOE_2 */ +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&dc_in>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + /* TOFIX: SD card is barely usable in SDR modes */ + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&vddio_c>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmif_c { + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmin_c { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tdmout_c { + status = "okay"; +}; + +&toacodec { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; +}; + +&usb2_phy0 { + phy-supply = <&dc_in>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&vl_pwr_en>; +}; diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts index 4b517ca720..f2c0981435 100644 --- a/arch/arm/dts/meson-sm1-khadas-vim3l.dts +++ b/arch/arm/dts/meson-sm1-khadas-vim3l.dts @@ -32,6 +32,19 @@ regulator-boot-on; regulator-always-on; }; + + sound { + model = "G12B-KHADAS-VIM3L"; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 13", "TDM_A Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT"; + }; }; &cpu0 { @@ -89,13 +102,12 @@ status = "okay"; }; -&sd_emmc_a { - sd-uhs-sdr50; -}; - &usb { phys = <&usb2_phy0>, <&usb2_phy1>; phy-names = "usb2-phy0", "usb2-phy1"; }; */ +&sd_emmc_a { + sd-uhs-sdr50; +}; diff --git a/arch/arm/dts/meson-sm1-odroid-c4.dts b/arch/arm/dts/meson-sm1-odroid-c4.dts index cf5a98f0e4..8c30ce6368 100644 --- a/arch/arm/dts/meson-sm1-odroid-c4.dts +++ b/arch/arm/dts/meson-sm1-odroid-c4.dts @@ -5,34 +5,12 @@ /dts-v1/; -#include "meson-sm1.dtsi" -#include -#include -#include +#include "meson-sm1-odroid.dtsi" / { compatible = "hardkernel,odroid-c4", "amlogic,sm1"; model = "Hardkernel ODROID-C4"; - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - leds { compatible = "gpio-leds"; @@ -45,324 +23,19 @@ }; }; - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - sound { - compatible = "amlogic,axg-sound-card"; - model = "SM1-ODROID-C4"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; + model = "ODROID-C4"; }; }; -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - &gpio { - gpio-line-names = - /* GPIOZ */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "", - "PIN_36", /* GPIOH_5 */ - "PIN_26", /* GPIOH_6 */ - "PIN_32", /* GPIOH_7 */ - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "", "", - /* GPIOA */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", - "PIN_27", /* GPIOA_14 */ - "PIN_28", /* GPIOA_15 */ - /* GPIOX */ - "PIN_16", /* GPIOX_0 */ - "PIN_18", /* GPIOX_1 */ - "PIN_22", /* GPIOX_2 */ - "PIN_11", /* GPIOX_3 */ - "PIN_13", /* GPIOX_4 */ - "PIN_7", /* GPIOX_5 */ - "PIN_33", /* GPIOX_6 */ - "PIN_15", /* GPIOX_7 */ - "PIN_19", /* GPIOX_8 */ - "PIN_21", /* GPIOX_9 */ - "PIN_24", /* GPIOX_10 */ - "PIN_23", /* GPIOX_11 */ - "PIN_8", /* GPIOX_12 */ - "PIN_10", /* GPIOX_13 */ - "PIN_29", /* GPIOX_14 */ - "PIN_31", /* GPIOX_15 */ - "PIN_12", /* GPIOX_16 */ - "PIN_3", /* GPIOX_17 */ - "PIN_5", /* GPIOX_18 */ - "PIN_35"; /* GPIOX_19 */ - /* * WARNING: The USB Hub on the Odroid-C4 needs a reset signal * to be turned high in order to be detected by the USB Controller * This signal should be handled by a USB specific power sequence * in order to reset the Hub when USB bus is powered down. */ - usb-hub { + hog-0 { gpio-hog; gpios = ; output-high; @@ -370,121 +43,6 @@ }; }; -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "", "", "", "", - "PIN_47", /* GPIOAO_4 */ - "", "", - "PIN_45", /* GPIOAO_7 */ - "PIN_46", /* GPIOAO_8 */ - "PIN_44", /* GPIOAO_9 */ - "PIN_42", /* GPIOAO_10 */ - "", - /* GPIOE */ - "", "", ""; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - &ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; linux,rc-map-name = "rc-odroid"; }; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <200000000>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/arch/arm/dts/meson-sm1-odroid-hc4.dts b/arch/arm/dts/meson-sm1-odroid-hc4.dts new file mode 100644 index 0000000000..f3f953225b --- /dev/null +++ b/arch/arm/dts/meson-sm1-odroid-hc4.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Dongjin Kim + */ + +/dts-v1/; + +#include "meson-sm1-odroid.dtsi" + +/ { + compatible = "hardkernel,odroid-hc4", "amlogic,sm1"; + model = "Hardkernel ODROID-HC4"; + + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-min-state = <0>; + cooling-max-state = <3>; + cooling-levels = <0 120 170 220>; + pwms = <&pwm_cd 1 40000 0>; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + + led-red { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ + p12v_0: regulator-p12v_0 { + compatible = "regulator-fixed"; + regulator-name = "P12V_0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ + p12v_1: regulator-p12v_1 { + compatible = "regulator-fixed"; + regulator-name = "P12V_1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + sound { + model = "ODROID-HC4"; + }; +}; + +&cpu_thermal { + cooling-maps { + map { + trip = <&cpu_passive>; + cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&ir { + linux,rc-map-name = "rc-odroid"; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + status = "okay"; + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + +&pcie { + status = "okay"; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; +}; + +&pwm_cd { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_d_x6_pins>; +}; + +&sd_emmc_c { + status = "disabled"; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + +&usb { + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; +}; + +&usb2_phy0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/meson-sm1-odroid.dtsi b/arch/arm/dts/meson-sm1-odroid.dtsi new file mode 100644 index 0000000000..fd0ad85c16 --- /dev/null +++ b/arch/arm/dts/meson-sm1-odroid.dtsi @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Dongjin Kim + */ + +#include "meson-sm1.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v>; + + enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + + gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&main_12v>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + vddcpu: regulator-vddcpu { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the microUSB port power enable */ + gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + gpio-line-names = + /* GPIOZ */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* GPIOH */ + "", "", "", "", "", + "PIN_36", /* GPIOH_5 */ + "PIN_26", /* GPIOH_6 */ + "PIN_32", /* GPIOH_7 */ + "", + /* BOOT */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* GPIOC */ + "", "", "", "", "", "", "", "", + /* GPIOA */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", + "PIN_27", /* GPIOA_14 */ + "PIN_28", /* GPIOA_15 */ + /* GPIOX */ + "PIN_16", /* GPIOX_0 */ + "PIN_18", /* GPIOX_1 */ + "PIN_22", /* GPIOX_2 */ + "PIN_11", /* GPIOX_3 */ + "PIN_13", /* GPIOX_4 */ + "PIN_7", /* GPIOX_5 */ + "PIN_33", /* GPIOX_6 */ + "PIN_15", /* GPIOX_7 */ + "PIN_19", /* GPIOX_8 */ + "PIN_21", /* GPIOX_9 */ + "PIN_24", /* GPIOX_10 */ + "PIN_23", /* GPIOX_11 */ + "PIN_8", /* GPIOX_12 */ + "PIN_10", /* GPIOX_13 */ + "PIN_29", /* GPIOX_14 */ + "PIN_31", /* GPIOX_15 */ + "PIN_12", /* GPIOX_16 */ + "PIN_3", /* GPIOX_17 */ + "PIN_5", /* GPIOX_18 */ + "PIN_35"; /* GPIOX_19 */ +}; + +&gpio_ao { + gpio-line-names = + /* GPIOAO */ + "", "", "", "", + "PIN_47", /* GPIOAO_4 */ + "", "", + "PIN_45", /* GPIOAO_7 */ + "PIN_46", /* GPIOAO_8 */ + "PIN_44", /* GPIOAO_9 */ + "PIN_42", /* GPIOAO_10 */ + "", + /* GPIOE */ + "", "", ""; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <200000000>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_pwr_en>; +}; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; + diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts index 5ab139a34c..2194a77897 100644 --- a/arch/arm/dts/meson-sm1-sei610.dts +++ b/arch/arm/dts/meson-sm1-sei610.dts @@ -101,20 +101,20 @@ }; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - led-bluetooth { + led-1 { label = "sei610:blue:bt"; gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; default-state = "off"; }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - power { + led-2 { label = "sei610:red:power"; pwms = <&pwm_AO_ab 0 30518 0>; max-brightness = <255>; @@ -220,7 +220,7 @@ sound { compatible = "amlogic,axg-sound-card"; - model = "SM1-SEI610"; + model = "SEI610"; audio-aux-devs = <&tdmout_a>, <&tdmout_b>, <&tdmin_a>, <&tdmin_b>; audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi index 71317f5aad..3d8b1f4f20 100644 --- a/arch/arm/dts/meson-sm1.dtsi +++ b/arch/arm/dts/meson-sm1.dtsi @@ -130,7 +130,7 @@ opp-microvolt = <790000>; }; - opp-1512000000 { + opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <800000>; }; @@ -401,6 +401,16 @@ status = "disabled"; }; + toacodec: audio-controller@740 { + compatible = "amlogic,sm1-toacodec", + "amlogic,g12a-toacodec"; + reg = <0x0 0x740 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOACODEC"; + resets = <&clkc_audio AUD_RESET_TOACODEC>; + status = "disabled"; + }; + tohdmitx: audio-controller@744 { compatible = "amlogic,sm1-tohdmitx", "amlogic,g12a-tohdmitx"; diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index fd1f938c38..93752ea107 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -70,7 +70,31 @@ #define CLKID_HIFI_PLL 69 #define CLKID_PCIE_CML_EN0 79 #define CLKID_PCIE_CML_EN1 80 -#define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 +#define CLKID_VPU_0_SEL 92 +#define CLKID_VPU_0 93 +#define CLKID_VPU_1_SEL 95 +#define CLKID_VPU_1 96 +#define CLKID_VPU 97 +#define CLKID_VAPB_0_SEL 99 +#define CLKID_VAPB_0 100 +#define CLKID_VAPB_1_SEL 102 +#define CLKID_VAPB_1 103 +#define CLKID_VAPB_SEL 104 +#define CLKID_VAPB 105 +#define CLKID_VCLK 106 +#define CLKID_VCLK2 107 +#define CLKID_VCLK_DIV1 122 +#define CLKID_VCLK_DIV2 123 +#define CLKID_VCLK_DIV4 124 +#define CLKID_VCLK_DIV6 125 +#define CLKID_VCLK_DIV12 126 +#define CLKID_VCLK2_DIV1 127 +#define CLKID_VCLK2_DIV2 128 +#define CLKID_VCLK2_DIV4 129 +#define CLKID_VCLK2_DIV6 130 +#define CLKID_VCLK2_DIV12 131 +#define CLKID_CTS_ENCL 133 +#define CLKID_VDIN_MEAS 136 #endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 40d49940d8..a93b58c5e1 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -147,5 +147,7 @@ #define CLKID_SPICC1_SCLK 261 #define CLKID_NNA_AXI_CLK 264 #define CLKID_NNA_CORE_CLK 267 +#define CLKID_MIPI_DSI_PXCLK_SEL 269 +#define CLKID_MIPI_DSI_PXCLK 270 #endif /* __G12A_CLKC_H */ From c7c085858616152fcab804bd8c14350ce181d241 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:01 +0200 Subject: [PATCH 016/228] usb: dwc3: meson-gxl: add AXG compatible Upstream Linux uses the "amlogic,meson-axg-usb-ctrl" for AXG SoCs. This adds it to the compatible list for this driver. Reported-by: Vyacheslav Bocharov Signed-off-by: Neil Armstrong Tested-by: Vyacheslav Bocharov --- drivers/usb/dwc3/dwc3-meson-gxl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 7c26290c15..6c6d463203 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -409,6 +409,7 @@ static int dwc3_meson_gxl_remove(struct udevice *dev) } static const struct udevice_id dwc3_meson_gxl_ids[] = { + { .compatible = "amlogic,meson-axg-usb-ctrl" }, { .compatible = "amlogic,meson-gxl-usb-ctrl" }, { .compatible = "amlogic,meson-gxm-usb-ctrl" }, { } From 535dcb55a5d38f69e619abef97a5643d70e3f88f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:02 +0200 Subject: [PATCH 017/228] ARM: meson: keep HW order for MMC devices Since Linux commmit [1], the order is fixed with aliases, in order to keep the MMC device order, set it back to HW order in U-Boot dtsi files. [1] ab547c4fb39f ("arm64: dts: amlogic: Assign a fixed index to mmc devices") Signed-off-by: Neil Armstrong --- arch/arm/dts/meson-g12-common-u-boot.dtsi | 7 +++++++ arch/arm/dts/meson-gx-u-boot.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index 38fd3d3feb..b1f60b15c9 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -5,6 +5,13 @@ */ / { + /* Keep HW order from U-boot */ + aliases { + /delete-property/ mmc0; + /delete-property/ mmc1; + /delete-property/ mmc2; + }; + soc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi index 17d2cb95c1..fb6952f1d8 100644 --- a/arch/arm/dts/meson-gx-u-boot.dtsi +++ b/arch/arm/dts/meson-gx-u-boot.dtsi @@ -5,6 +5,13 @@ */ / { + /* Keep HW order from U-boot */ + aliases { + /delete-property/ mmc0; + /delete-property/ mmc1; + /delete-property/ mmc2; + }; + soc { u-boot,dm-pre-reloc; }; From 3da675a93bee1ecbd652d98ce85ef58140d4c215 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:03 +0200 Subject: [PATCH 018/228] ARM: meson-axg: remove local USB nodes Drop the local USB nodes after Linux 5.14 sync. Signed-off-by: Neil Armstrong --- arch/arm/dts/meson-axg-s400-u-boot.dtsi | 8 ---- arch/arm/dts/meson-axg-u-boot.dtsi | 62 ------------------------- 2 files changed, 70 deletions(-) delete mode 100644 arch/arm/dts/meson-axg-u-boot.dtsi diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi index 2c4b06f140..334650d610 100644 --- a/arch/arm/dts/meson-axg-s400-u-boot.dtsi +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi @@ -3,8 +3,6 @@ * Copyright (c) 2017 Amlogic, Inc. All rights reserved. */ -#include "meson-axg-u-boot.dtsi" - /* wifi module */ &sd_emmc_b { status = "disabled"; @@ -15,12 +13,6 @@ status = "okay"; }; -&usb { - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usb_pwr>; -}; - &usb2_phy1 { phy-supply = <&vcc_5v>; }; diff --git a/arch/arm/dts/meson-axg-u-boot.dtsi b/arch/arm/dts/meson-axg-u-boot.dtsi deleted file mode 100644 index cb1c71e78c..0000000000 --- a/arch/arm/dts/meson-axg-u-boot.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre, SAS. - * Author: Neil Armstrong - */ - -/ { - soc { - usb: usb@ffe09080 { - compatible = "amlogic,meson-gxl-usb-ctrl"; - reg = <0x0 0xffe09080 0x0 0x20>; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - }; -}; - -&apb { - usb2_phy1: phy@9020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x9020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; -}; From f485e9dfa75597c7876ffbe97c91b4f6828f4135 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:04 +0200 Subject: [PATCH 019/228] configs: meson64: add SCSI boot target Add SCSI target to be able to boot from the SATA disks on the Odroid HC4 using an on-board AHCI PCIe controller. Signed-off-by: Neil Armstrong Signed-off-by: Mark Kettenis --- include/configs/meson64.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index b779363b2b..cb202d5555 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -62,6 +62,12 @@ #define BOOT_TARGET_NVME(func) #endif +#ifdef CONFIG_CMD_SCSI + #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0) +#else + #define BOOT_TARGET_SCSI(func) +#endif + #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(ROMUSB, romusb, na) \ @@ -70,6 +76,7 @@ func(MMC, mmc, 2) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_NVME(func) \ + BOOT_TARGET_SCSI(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #endif From d565a35dbd0662de31770e4f132b7a4a337d0ade Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:05 +0200 Subject: [PATCH 020/228] distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot The SCSI device can be a PCIe adapter, so run pcie enum if enabled. Signed-off-by: Mark Kettenis Signed-off-by: Neil Armstrong --- include/config_distro_bootcmd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 750e9e04e8..3f724aa10f 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -226,6 +226,7 @@ "fi\0" \ \ "scsi_boot=" \ + BOOTENV_RUN_PCI_ENUM \ BOOTENV_RUN_SCSI_INIT \ BOOTENV_SHARED_BLKDEV_BODY(scsi) #define BOOTENV_DEV_SCSI BOOTENV_DEV_BLKDEV From a4b553e31b33f759e8207710c10cada4c3aca33a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:06 +0200 Subject: [PATCH 021/228] ARM: amlogic: add support for Odroid-HC4 device The Odroid-HC4 is a variant of the Odroid-C4 board but with a PCIe-SATA bridge instead of the USB3 ports. [narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: Neil Armstrong --- arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi | 23 +++++ board/amlogic/odroid-n2/MAINTAINERS | 1 + configs/odroid-hc4_defconfig | 93 +++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi create mode 100644 configs/odroid-hc4_defconfig diff --git a/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi b/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi new file mode 100644 index 0000000000..963bf96b25 --- /dev/null +++ b/arch/arm/dts/meson-sm1-odroid-hc4-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include "meson-sm1-u-boot.dtsi" + +ðmac { + snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +}; + +/* SARADC is needed for proper board variant detection */ +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +&tflash_vdd { + gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; +}; diff --git a/board/amlogic/odroid-n2/MAINTAINERS b/board/amlogic/odroid-n2/MAINTAINERS index 77f7746346..43724e6fdd 100644 --- a/board/amlogic/odroid-n2/MAINTAINERS +++ b/board/amlogic/odroid-n2/MAINTAINERS @@ -5,5 +5,6 @@ L: u-boot-amlogic@groups.io F: board/amlogic/odroid-n2/ F: configs/odroid-n2_defconfig F: configs/odroid-c4_defconfig +F: configs/odroid-hc4_defconfig F: doc/board/amlogic/odroid-n2.rst F: doc/board/amlogic/odroid-c4.rst diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig new file mode 100644 index 0000000000..917d95c9c1 --- /dev/null +++ b/configs/odroid-hc4_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="odroid-n2" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4" +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" odroid-hc4" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_AHCI=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SATA=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MESON_G12A=y +CONFIG_PCI=y +CONFIG_PCIE_DW_MESON=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y From 76bb02780206b521801b739a81add87a887bce62 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:07 +0200 Subject: [PATCH 022/228] doc: boards: amlogic: update for Odroid HC4 Add documentation bits for the Odroid-HC4. Signed-off-by: Neil Armstrong --- doc/board/amlogic/index.rst | 2 +- doc/board/amlogic/odroid-c4.rst | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 8da7afddb4..af12f94fde 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -18,7 +18,7 @@ This matrix concerns the actual source code version. | Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | | | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L | | | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | -| | P201 | LibreTech-AC v2 | | | | | | +| | P201 | LibreTech-AC v2 | | | | | Odroid-HC4 | +-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ | UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ diff --git a/doc/board/amlogic/odroid-c4.rst b/doc/board/amlogic/odroid-c4.rst index 5a5a8688b8..f66d60a54d 100644 --- a/doc/board/amlogic/odroid-c4.rst +++ b/doc/board/amlogic/odroid-c4.rst @@ -17,6 +17,9 @@ Co. Ltd with the following specifications: - UART serial - Infrared receiver +The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands +applies for HC4. + Schematics are available on the manufacturer website. U-Boot compilation From 2c9269b14bce771069888c9447b0984f44d2dbdf Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:08 +0200 Subject: [PATCH 023/228] ARM: meson: add Beelink GS-King X board The Beelink GS-King X is a variant of the GS King boards but with an internal USB to SATA bridge and advanced audio features. [narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: Neil Armstrong --- arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi | 7 ++ board/amlogic/beelink-s922x/MAINTAINERS | 1 + configs/beelink-gsking-x_defconfig | 71 ++++++++++++++++++++ doc/board/amlogic/index.rst | 2 +- 4 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi create mode 100644 configs/beelink-gsking-x_defconfig diff --git a/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi b/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi new file mode 100644 index 0000000000..236f2468dc --- /dev/null +++ b/arch/arm/dts/meson-g12b-gsking-x-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-g12-common-u-boot.dtsi" diff --git a/board/amlogic/beelink-s922x/MAINTAINERS b/board/amlogic/beelink-s922x/MAINTAINERS index 7f223df4ae..47b622765a 100644 --- a/board/amlogic/beelink-s922x/MAINTAINERS +++ b/board/amlogic/beelink-s922x/MAINTAINERS @@ -5,5 +5,6 @@ L: u-boot-amlogic@groups.io F: board/amlogic/beelink-s922x/ F: configs/beelink-gtking_defconfig F: configs/beelink-gtkingpro_defconfig +F: configs/beelink-gsking-x_defconfig F: doc/board/amlogic/beelink-gtking.rst F: doc/board/amlogic/beelink-gtkingpro.rst diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig new file mode 100644 index 0000000000..54ac1c9315 --- /dev/null +++ b/configs/beelink-gsking-x_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="beelink-s922x" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x" +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" beelink" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MESON_G12A=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index af12f94fde..de1a9ce284 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -18,7 +18,7 @@ This matrix concerns the actual source code version. | Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | | | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L | | | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | -| | P201 | LibreTech-AC v2 | | | | | Odroid-HC4 | +| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 | +-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ | UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ From fe8b4c10804aef88ba00f5b9eeace80810f2ded9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Sep 2021 09:37:09 +0200 Subject: [PATCH 024/228] ARM: amlogic: add Banana Pi M5 Banana Pi BPI-M5 is a credit card format SBC with the following features: - Amlogic S905X3 quad core Cortex-A55 - Mali-G31 GPU - 4GB LPDDR4 - 16GB eMMC flash - 4 USB 3.0 - 1 GbE ethernet - HDMI output - 2x LEDS - SDCard - 2.5mm Jack with Stereo Audio + CVBS - Infrared Received - ADC Button - GPIO Button - 40 pins header + 3pins debug header [narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: Neil Armstrong --- .../arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi | 13 ++++ board/amlogic/u200/MAINTAINERS | 1 + configs/bananapi-m5_defconfig | 74 +++++++++++++++++++ doc/board/amlogic/index.rst | 1 + 4 files changed, 89 insertions(+) create mode 100644 arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi create mode 100644 configs/bananapi-m5_defconfig diff --git a/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi b/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi new file mode 100644 index 0000000000..a86fdb5668 --- /dev/null +++ b/arch/arm/dts/meson-sm1-bananapi-m5-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include "meson-sm1-u-boot.dtsi" + +ðmac { + snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +}; diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS index 8c23f9a7d3..655cf64a3d 100644 --- a/board/amlogic/u200/MAINTAINERS +++ b/board/amlogic/u200/MAINTAINERS @@ -4,4 +4,5 @@ S: Maintained L: u-boot-amlogic@groups.io F: board/amlogic/u200/ F: configs/u200_defconfig +F: configs/bananapi-m5_defconfig F: doc/board/amlogic/u200.rst diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig new file mode 100644 index 0000000000..7ca14a5f6a --- /dev/null +++ b/configs/bananapi-m5_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5" +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING="bpi-m5" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_MMC_MESON_GX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MESON_G12A=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index de1a9ce284..2913ab281a 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -19,6 +19,7 @@ This matrix concerns the actual source code version. | | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L | | | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | | | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 | +| | | | | | | | BananaPi-M5 | +-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ | UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | +-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ From 15eda54676058226fac7c642db03f3f533026522 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Mon, 20 Sep 2021 11:40:14 +0300 Subject: [PATCH 025/228] ARM: amlogic: add JetHub common config header JetHub devices uses its own boot sequence with "rescue" button Signed-off-by: Vyacheslav Bocharov Signed-off-by: Neil Armstrong --- include/configs/jethub.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 include/configs/jethub.h diff --git a/include/configs/jethub.h b/include/configs/jethub.h new file mode 100644 index 0000000000..35f85095ac --- /dev/null +++ b/include/configs/jethub.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for JetHome devices + * Copyright (C) 2021 Vyacheslav Bocharov + * Author: Vyacheslav Bocharov + */ + +#ifndef __JETHUB_CONFIG_H +#define __JETHUB_CONFIG_H + +#if defined(CONFIG_MESON_AXG) +#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ + "bootcmd_rescue=" \ + "if gpio input 10; then " \ + "run bootcmd_usb0;" \ + "fi;\0" +#else +#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ + "bootcmd_rescue=" \ + "if test \"${userbutton}\" = \"true\"; then " \ + "run bootcmd_mmc0; " \ + "fi;\0" +#endif + +#define BOOTENV_DEV_NAME_RESCUE(devtypeu, devtypel, instance) \ + "rescue " + +#ifndef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(RESCUE, rescue, na) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#endif + +#include + +#endif /* __JETHUB_CONFIG_H */ From de19baef6843275ef6e18f99cade9220841bb218 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Mon, 20 Sep 2021 11:40:15 +0300 Subject: [PATCH 026/228] ARM: amlogic: add JetHub D1/H1 device support Add support for new home automation devices. JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller with the following features: - DIN Rail Mounting case - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz - no video out - 512Mb/1GB DDR3 - 8/16GB eMMC flash - 1 x USB 2.0 - 1 x 10/100Mbps ethernet - WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE 802.11a/b/g/n/ac, Bluetooth 4.2. - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support. - 2 x gpio LEDS - GPIO user Button - 1 x 1-Wire - 2 x RS-485 - 4 x dry contact digital GPIO inputs - 3 x relay GPIO outputs - DC source with a voltage of 9 to 56 V / Passive POE JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller with the following features: - Square plastic case - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz - no video out - 1GB DDR3 - 8/16GB eMMC flash - 2 x USB 2.0 - 1 x 10/100Mbps ethernet - WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0. - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support. - MicroSD 2.x/3.x/4.x DS/HS cards. - 1 x gpio LED - ADC user Button - DC source 5V microUSB with serial console Patches from: - JetHub H1 https://lore.kernel.org/r/20210915085715.1134940-4-adeep@lexina.in https://git.kernel.org/amlogic/c/abfaae24ecf3e7f00508b60fa05e2b6789b8f607 - JetHub D1 https://lore.kernel.org/r/20210915085715.1134940-5-adeep@lexina.in https://git.kernel.org/amlogic/c/8e279fb2903990cc6296ec56b3b80b2f854b6c79 Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong [narmstrong: removed unused variable value] Signed-off-by: Neil Armstrong --- arch/arm/dts/Makefile | 2 + .../arm/dts/meson-axg-jethome-jethub-j100.dts | 361 ++++++++++++++++++ .../meson-gxl-s905w-jethome-jethub-j80.dts | 241 ++++++++++++ board/amlogic/jethub-j80/MAINTAINERS | 9 + board/amlogic/jethub-j80/Makefile | 6 + board/amlogic/jethub-j80/jethub-j80.c | 67 ++++ configs/jethub_j100_defconfig | 63 +++ configs/jethub_j80_defconfig | 71 ++++ 8 files changed, 820 insertions(+) create mode 100644 arch/arm/dts/meson-axg-jethome-jethub-j100.dts create mode 100644 arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts create mode 100644 board/amlogic/jethub-j80/MAINTAINERS create mode 100644 board/amlogic/jethub-j80/Makefile create mode 100644 board/amlogic/jethub-j80/jethub-j80.c create mode 100644 configs/jethub_j100_defconfig create mode 100644 configs/jethub_j80_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c251853ea..c21bbde5d6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -169,10 +169,12 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-libretech-cc-v2.dtb \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxl-s905d-libretech-pc.dtb \ + meson-gxl-s905w-jethome-jethub-j80.dtb \ meson-gxm-khadas-vim2.dtb \ meson-gxm-s912-libretech-pc.dtb \ meson-gxm-wetek-core2.dtb \ meson-axg-s400.dtb \ + meson-axg-jethome-jethub-j100.dtb \ meson-g12a-u200.dtb \ meson-g12a-sei510.dtb \ meson-g12b-gtking.dtb \ diff --git a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts b/arch/arm/dts/meson-axg-jethome-jethub-j100.dts new file mode 100644 index 0000000000..5783732dc6 --- /dev/null +++ b/arch/arm/dts/meson-axg-jethome-jethub-j100.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Vyacheslav Bocharov + * Copyright (c) 2020 JetHome + * Author: Aleksandr Kazantsev + * Author: Alexey Shevelkin + * Author: Vyacheslav Bocharov + */ + +/dts-v1/; + +#include "meson-axg.dtsi" +#include +#include + +/ { + compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg"; + model = "JetHome JetHub J100"; + aliases { + serial0 = &uart_AO; /* Console */ + serial1 = &uart_AO_B; /* External UART (Wireless Module) */ + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 1024MB RAM */ + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + reserved-memory { + linux,cma { + size = <0x0 0x400000>; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v>; + regulator-always-on; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + usb_pwr: regulator-usb_pwr { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&scpi_sensors 0>; + trips { + cpu_passive: cpu-passive { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cpu_hot: cpu-hot { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + cpu_critical: cpu-critical { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + onewire { + compatible = "w1-gpio"; + gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>; + #gpio-cells = <1>; + }; +}; + +&efuse { + sn: sn@32 { + reg = <0x32 0x20>; + }; + + eth_mac: eth_mac@0 { + reg = <0x0 0x6>; + }; + + bt_mac: bt_mac@6 { + reg = <0x6 0x6>; + }; + + wifi_mac: wifi_mac@c { + reg = <0xc 0x6>; + }; + + bid: bid@12 { + reg = <0x12 0x20>; + }; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_x_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */ + eth_phy0: ethernet-phy@0 { + /* compatible = "ethernet-phy-id0243.0c54";*/ + max-speed = <100>; + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* Internal I2C bus (on CPU module) */ +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_z_pins>; + pinctrl-names = "default"; + + /* RTC */ + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; +}; + +/* Peripheral I2C bus (on motherboard) */ +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; + pinctrl-names = "default"; +}; + +&pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_x20_pins>; + pinctrl-names = "default"; +}; + +/* wifi module */ +&sd_emmc_b { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr104; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* emmc storage */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* UART Bluetooth */ +&uart_B { + status = "okay"; + pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; + }; +}; + +/* UART Console */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +/* UART Wireless module */ +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + phy-supply = <&usb_pwr>; +}; + +&spicc1 { + status = "okay"; + pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>; + pinctrl-names = "default"; +}; + +&gpio { + gpio-line-names = + "", "", "", "", "", // 0 - 4 + "", "", "", "", "", // 5 - 9 + "UserButton", "", "", "", "", // 10 - 14 + "", "", "", "", "", // 15 - 19 + "", "", "", "", "", // 20 - 24 + "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29 + "Output1", "", "", "", "", // 30 - 34 + "", "ZigBeeBOOT", "", "", "", // 35 - 39 + "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44 + "Input2", "Input1", "", "", "", // 45 - 49 + "", "", "", "", "", // 50 - 54 + "", "", "", "", "", // 55 - 59 + "", "", "", "", "", // 60 - 64 + "", "", "", "", "", // 65 - 69 + "", "", "", "", "", // 70 - 74 + "", "", "", "", "", // 75 - 79 + "", "", "", "", "", // 80 - 84 + "", ""; // 85-86 +}; + +&cpu0 { + #cooling-cells = <2>; +}; + +&cpu1 { + #cooling-cells = <2>; +}; + +&cpu2 { + #cooling-cells = <2>; +}; + +&cpu3 { + #cooling-cells = <2>; +}; diff --git a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts new file mode 100644 index 0000000000..6eafb90869 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Vyacheslav Bocharov + * Copyright (c) 2020 JetHome + * Author: Aleksandr Kazantsev + * Author: Alexey Shevelkin + * Author: Vyacheslav Bocharov + */ + +/dts-v1/; + +#include "meson-gxl.dtsi" + +/ { + compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl"; + model = "JetHome JetHub J80"; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + reserved-memory { + linux,cma { + size = <0x0 0x1000000>; + }; + }; + + aliases { + serial0 = &uart_AO; /* Console */ + serial1 = &uart_A; /* Bluetooth */ + serial2 = &uart_AO_B; /* Wireless module 1 */ + serial3 = &uart_C; /* Wireless module 2 */ + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +&efuse { + bt_mac: bt_mac@6 { + reg = <0x6 0x6>; + }; + + wifi_mac: wifi_mac@C { + reg = <0xc 0x6>; + }; +}; + +&sn { + reg = <0x32 0x20>; +}; + +ð_mac { + reg = <0x0 0x6>; +}; + +&bid { + reg = <0x12 0x20>; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* Console UART */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +/* S905W only has access to its internal PHY */ +ðmac { + status = "okay"; + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&internal_phy { + status = "okay"; + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&uart_C { + status = "okay"; + pinctrl-0 = <&uart_c_pins>; + pinctrl-names = "default"; +}; + +&uart_AO_B { + status = "okay"; + pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&i2c_B { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_b_pins>; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; +}; diff --git a/board/amlogic/jethub-j80/MAINTAINERS b/board/amlogic/jethub-j80/MAINTAINERS new file mode 100644 index 0000000000..459e9f89da --- /dev/null +++ b/board/amlogic/jethub-j80/MAINTAINERS @@ -0,0 +1,9 @@ +JetHome JetHub +M: Vyacheslav Bocharov +S: Maintained +L: u-boot-amlogic@groups.io +F: board/amlogic/jethub-j80/ +F: configs/jethub_j80_defconfig +F: configs/jethub_j100_defconfig +F: doc/board/amlogic/jethub-j80.rst +F: doc/board/amlogic/jethub-j100.rst diff --git a/board/amlogic/jethub-j80/Makefile b/board/amlogic/jethub-j80/Makefile new file mode 100644 index 0000000000..a727a4b222 --- /dev/null +++ b/board/amlogic/jethub-j80/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2021 Vyacheslav Bocharov +# Author: Vyacheslav Bocharov + +obj-y := jethub-j80.o diff --git a/board/amlogic/jethub-j80/jethub-j80.c b/board/amlogic/jethub-j80/jethub-j80.c new file mode 100644 index 0000000000..185880de13 --- /dev/null +++ b/board/amlogic/jethub-j80/jethub-j80.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Vyacheslav Bocharov + * Author: Vyacheslav Bocharov + * Author: Neil Armstrong + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EFUSE_SN_OFFSET 50 +#define EFUSE_SN_SIZE 32 +#define EFUSE_MAC_OFFSET 0 +#define EFUSE_MAC_SIZE 6 +#define EFUSE_USID_OFFSET 18 +#define EFUSE_USID_SIZE 32 + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + char serial[EFUSE_SN_SIZE]; + char usid[EFUSE_USID_SIZE]; + ssize_t len; + unsigned int adcval; + int ret; + + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); + else + meson_generate_serial_ethaddr(); + } + + if (!env_get("serial")) { + len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, + EFUSE_SN_SIZE); + if (len == EFUSE_SN_SIZE) + env_set("serial", serial); + } + + if (!env_get("usid")) { + len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid, + EFUSE_USID_SIZE); + if (len == EFUSE_USID_SIZE) + env_set("usid", usid); + } + + ret = adc_channel_single_shot("adc@8680", 0, &adcval); + if (adcval < 3000) + env_set("userbutton", "true"); + else + env_set("userbutton", "false"); + + return 0; +} diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig new file mode 100644 index 0000000000..533f251855 --- /dev/null +++ b/configs/jethub_j100_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="jethub" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100" +CONFIG_MESON_AXG=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" jethubj100" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPIO=y +CONFIG_RANDOM_UUID=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_REGULATOR=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD_UBI=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_AXG=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF8563=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_GXL=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig new file mode 100644 index 0000000000..ad6bec0c43 --- /dev/null +++ b/configs/jethub_j80_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="jethub-j80" +CONFIG_SYS_CONFIG_NAME="jethub" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" +CONFIG_MESON_GXL=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" jethubj80" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_RANDOM_UUID=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_RTC=y +CONFIG_CMD_REGULATOR=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD_UBI=y +CONFIG_PHY_MESON_GXL=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_MDIO_MUX_MMIOREG=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF8563=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_GXL=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y From 2ae382285bc527084bf5c22bdf16aae7c7017df6 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Mon, 20 Sep 2021 11:40:16 +0300 Subject: [PATCH 027/228] ARM: amlogic: add JetHub D1/H1 docs Fix doc/board/amlogic/index.rst: - Add S905W to S905X column. - Add JetHub devices to the corresponding columns. - Fix tabs to spaces for table alignment Add doc/board/amlogic files: - jethub-j100.rst - jethub-j80.rst Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong --- doc/board/amlogic/index.rst | 128 +++++++++++++++--------------- doc/board/amlogic/jethub-j100.rst | 108 +++++++++++++++++++++++++ doc/board/amlogic/jethub-j80.rst | 97 ++++++++++++++++++++++ 3 files changed, 270 insertions(+), 63 deletions(-) create mode 100644 doc/board/amlogic/jethub-j100.rst create mode 100644 doc/board/amlogic/jethub-j80.rst diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 2913ab281a..c18f1b7e71 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -10,69 +10,69 @@ An up-do-date matrix is also available on: http://linux-meson.com This matrix concerns the actual source code version. -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 | -| | | S805X | S905D | | S905D2 | A311D | S905D3 | -| | | | | | S905Y2 | | | -+===============================+===========+=================+==============+============+============+=============+==============+ -| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | -| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L | -| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | -| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 | -| | | | | | | | BananaPi-M5 | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Infrared Decoder | No | No | No | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| SPI (CC) | No | No | No | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| NAND | No | No | No | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| CEC | No | No | No | *N/A* | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| Thermal Sensor | No | No | No | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| LCD/LVDS Output | No | *N/A* | No | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ -| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** | -+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+ ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 | +| | | S805X | S905D | | S905D2 | A311D | S905D3 | +| | | S905W | | | S905Y2 | | | ++===============================+===========+=================+==============+=============+============+=============+==============+ +| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | +| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L | +| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | +| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 | +| | | JetHub J80 | | | | | BananaPi-M5 | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Infrared Decoder | No | No | No | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| SPI (CC) | No | No | No | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| NAND | No | No | No | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| CEC | No | No | No | *N/A* | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| Thermal Sensor | No | No | No | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| LCD/LVDS Output | No | *N/A* | No | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ +| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** | ++-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ Board Documentation ------------------- @@ -82,6 +82,8 @@ Board Documentation beelink-gtking beelink-gtkingpro + jethub-j100 + jethub-j80 khadas-vim2 khadas-vim3l khadas-vim3 diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst new file mode 100644 index 0000000000..58602787d3 --- /dev/null +++ b/doc/board/amlogic/jethub-j100.rst @@ -0,0 +1,108 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for JetHub J100 +======================= + +JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation +controller manufactured by JetHome with the following specifications: + + - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz + - no video out + - 512Mb/1GB DDR3 + - 8/16GB eMMC flash + - 1 x USB 2.0 + - 1 x 10/100Mbps ethernet + - WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE + 802.11a/b/g/n/ac, Bluetooth 4.2. + - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output + power and Zigbee 3.0 support. + - 2 x gpio LEDS + - GPIO user Button + - 1 x 1-Wire + - 2 x RS-485 + - 4 x dry contact digital GPIO inputs + - 3 x relay GPIO outputs + - DC source with a voltage of 9 to 56 V / Passive POE + - DIN Rail Mounting case + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make jethub_j100_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain binaries +from the git tree published by the board vendor: + +.. code-block:: bash + + $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot + $ cd jethub-u-boot + $ export FIPDIR=$PWD + +Go back to mainline U-boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/j100/bl2.bin fip/ + $ cp $FIPDIR/j100/acs.bin fip/ + $ cp $FIPDIR/j100/bl21.bin fip/ + $ cp $FIPDIR/j100/bl30.bin fip/ + $ cp $FIPDIR/j100/bl301.bin fip/ + $ cp $FIPDIR/j100/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + $ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + $ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + $ $FIPDIR/j100/aml_encrypt_axg --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc --level v3 + +and then write the image to eMMC with: + +.. code-block:: bash + + $ DEV=/dev/your_emmc_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/doc/board/amlogic/jethub-j80.rst b/doc/board/amlogic/jethub-j80.rst new file mode 100644 index 0000000000..6b7bdc78b1 --- /dev/null +++ b/doc/board/amlogic/jethub-j80.rst @@ -0,0 +1,97 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for JetHub J80 +====================== + +JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation +controller manufactured by JetHome with the following specifications: + + - Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz + - No video out + - 1GB DDR3 + - 8/16GB eMMC flash + - 2 x USB 2.0 + - 1 x 10/100Mbps ethernet + - SDIO WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0. + - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output + power and Zigbee 3.0 support. + - MicroSD 2.x/3.x/4.x DS/HS cards. + - 1 x gpio LED + - ADC user Button + - DC source 5V microUSB + - Square plastic case + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make jethub_j80_defconfig + $ make + +Image creation +-------------- + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain binaries +from the git tree published by the board vendor: + +.. code-block:: bash + + $ git clone https://github.com/jethome-ru/jethub-aml-tools jethub-u-boot + $ cd jethub-u-boot + $ export FIPDIR=$PWD + +Go back to mainline U-Boot source tree then : + +.. code-block:: bash + + $ mkdir fip + + $ cp $FIPDIR/j80/bl2.bin fip/ + $ cp $FIPDIR/j80/acs.bin fip/ + $ cp $FIPDIR/j80/bl21.bin fip/ + $ cp $FIPDIR/j80/bl30.bin fip/ + $ cp $FIPDIR/j80/bl301.bin fip/ + $ cp $FIPDIR/j80/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4 + $ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/j80/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD/eMMC with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 From 8ee224bfe48713f50f71f136ad695dfee23189e4 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 15 Sep 2021 01:46:56 +0000 Subject: [PATCH 028/228] ARM: dts: sort Amlogic Makefile section Alpha sort the Amlogic dtb list (same as the kernel). Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong --- arch/arm/dts/Makefile | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c21bbde5d6..9ad46fa84f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -158,31 +158,31 @@ dtb-$(CONFIG_ARCH_S5P4418) += \ s5p4418-nanopi2.dtb dtb-$(CONFIG_ARCH_MESON) += \ + meson-axg-s400.dtb \ + meson-axg-jethome-jethub-j100.dtb \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-odroidc2.dtb \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-p200.dtb \ meson-gxbb-p201.dtb \ - meson-gxl-s905x-p212.dtb \ meson-gxl-s805x-libretech-ac.dtb \ - meson-gxl-s905x-libretech-cc.dtb \ - meson-gxl-s905x-libretech-cc-v2.dtb \ - meson-gxl-s905x-khadas-vim.dtb \ meson-gxl-s905d-libretech-pc.dtb \ meson-gxl-s905w-jethome-jethub-j80.dtb \ + meson-gxl-s905x-khadas-vim.dtb \ + meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-libretech-cc-v2.dtb \ + meson-gxl-s905x-p212.dtb \ meson-gxm-khadas-vim2.dtb \ meson-gxm-s912-libretech-pc.dtb \ meson-gxm-wetek-core2.dtb \ - meson-axg-s400.dtb \ - meson-axg-jethome-jethub-j100.dtb \ - meson-g12a-u200.dtb \ meson-g12a-sei510.dtb \ + meson-g12a-u200.dtb \ + meson-g12b-a311d-khadas-vim3.dtb \ meson-g12b-gtking.dtb \ meson-g12b-gtking-pro.dtb \ meson-g12b-gsking-x.dtb \ meson-g12b-odroid-n2.dtb \ meson-g12b-odroid-n2-plus.dtb \ - meson-g12b-a311d-khadas-vim3.dtb \ meson-sm1-bananapi-m5.dtb \ meson-sm1-khadas-vim3l.dtb \ meson-sm1-odroid-c4.dtb \ From b1463cbb5402d9b971228efc20cccaac3a840636 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 15 Sep 2021 01:46:57 +0000 Subject: [PATCH 029/228] ARM: dts: add support for Radxa Zero Import the initial dts queued for Linux 5.16.y Signed-off-by: Christian Hewitt Signed-off-by: Neil Armstrong --- arch/arm/dts/Makefile | 1 + .../arm/dts/meson-g12a-radxa-zero-u-boot.dtsi | 7 + arch/arm/dts/meson-g12a-radxa-zero.dts | 405 ++++++++++++++++++ 3 files changed, 413 insertions(+) create mode 100644 arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi create mode 100644 arch/arm/dts/meson-g12a-radxa-zero.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9ad46fa84f..b8a382d153 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -175,6 +175,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxm-khadas-vim2.dtb \ meson-gxm-s912-libretech-pc.dtb \ meson-gxm-wetek-core2.dtb \ + meson-g12a-radxa-zero.dtb \ meson-g12a-sei510.dtb \ meson-g12a-u200.dtb \ meson-g12b-a311d-khadas-vim3.dtb \ diff --git a/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi b/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi new file mode 100644 index 0000000000..236f2468dc --- /dev/null +++ b/arch/arm/dts/meson-g12a-radxa-zero-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-g12-common-u-boot.dtsi" diff --git a/arch/arm/dts/meson-g12a-radxa-zero.dts b/arch/arm/dts/meson-g12a-radxa-zero.dts new file mode 100644 index 0000000000..e3bb6df42f --- /dev/null +++ b/arch/arm/dts/meson-g12a-radxa-zero.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre SAS. All rights reserved. + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" +#include +#include + +/ { + compatible = "radxa,zero", "amlogic,g12a"; + model = "Radxa Zero"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + cvbs-connector { + status = "disabled"; + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + hdmi_pw: regulator-hdmi_pw { + compatible = "regulator-fixed"; + regulator-name = "HDMI_PW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ao_5v>; + regulator-always-on; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ao_5v>; + regulator-always-on; + }; + + vddcpu: regulator-vddcpu { + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&ao_5v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "RADXA-ZERO"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&arb { + status = "okay"; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&hdmi_pw>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "disabled"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; From e294f64b7167279cf5277b962fed21a34af374de Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 15 Sep 2021 01:46:58 +0000 Subject: [PATCH 030/228] boards: amlogic: add Radxa Zero defconfig Add a defconfig for the Radxa Zero SBC, using an Amlogic S905Y2 chip. Signed-off-by: Christian Hewitt [narmstrong: updated u200 MAINTAINERS & add missing CONFIG_SYS_LOAD_ADDR from defconfig] Signed-off-by: Neil Armstrong --- board/amlogic/u200/MAINTAINERS | 1 + configs/radxa-zero_defconfig | 65 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 configs/radxa-zero_defconfig diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS index 655cf64a3d..73c73b1591 100644 --- a/board/amlogic/u200/MAINTAINERS +++ b/board/amlogic/u200/MAINTAINERS @@ -5,4 +5,5 @@ L: u-boot-amlogic@groups.io F: board/amlogic/u200/ F: configs/u200_defconfig F: configs/bananapi-m5_defconfig +F: configs/radxa-zero_defconfig F: doc/board/amlogic/u200.rst diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig new file mode 100644 index 0000000000..91457f5eb7 --- /dev/null +++ b/configs/radxa-zero_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero" +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" radxa-zero" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_ETH=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_OF_LIBFDT_OVERLAY=y From 506fd30740081541d672ec2651cd23734899af76 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 15 Sep 2021 01:46:59 +0000 Subject: [PATCH 031/228] doc: boards: amlogic: update for Radxa Zero Add documentation bits for the Radxa Zero Signed-off-by: Christian Hewitt [narmstrong: updated u200 MAINTAINERS] Signed-off-by: Neil Armstrong --- board/amlogic/u200/MAINTAINERS | 1 + doc/board/amlogic/index.rst | 3 +- doc/board/amlogic/radxa-zero.rst | 74 ++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 doc/board/amlogic/radxa-zero.rst diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS index 73c73b1591..a259d12886 100644 --- a/board/amlogic/u200/MAINTAINERS +++ b/board/amlogic/u200/MAINTAINERS @@ -7,3 +7,4 @@ F: configs/u200_defconfig F: configs/bananapi-m5_defconfig F: configs/radxa-zero_defconfig F: doc/board/amlogic/u200.rst +F: doc/board/amlogic/radxa-zero.rst diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index c18f1b7e71..189b1efe2b 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -17,7 +17,7 @@ This matrix concerns the actual source code version. +===============================+===========+=================+==============+=============+============+=============+==============+ | Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 | | | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L | -| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 | +| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 | | | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 | | | | JetHub J80 | | | | | BananaPi-M5 | +-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+ @@ -98,6 +98,7 @@ Board Documentation p201 p212 q200 + radxa-zero s400 sei510 sei610 diff --git a/doc/board/amlogic/radxa-zero.rst b/doc/board/amlogic/radxa-zero.rst new file mode 100644 index 0000000000..423403f3c7 --- /dev/null +++ b/doc/board/amlogic/radxa-zero.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Radxa Zero +===================== + +Radxa Zero is a small form factor SBC based on the Amlogic S905Y2 +chipset that ships in a number of RAM/eMMC configurations: + +Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436 +wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB +eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac). + +- Amlogic S905Y2 quad-core Cortex-A53 +- Mali G31-MP2 GPU +- HDMI 2.1 output (micro) +- 1x USB 2.0 port - Type C (OTG) +- 1x USB 3.0 port - Type C (Host) +- 1x micro SD Card slot +- 40 Pin GPIO header + +Schematics are available on the manufacturer website: + +https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf + +U-Boot compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make radxa-zero_defconfig + $ make + +Image creation +-------------- + +Amlogic does not provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +git trees published by the board vendor: + +.. code-block:: bash + + $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git + $ git clone https://github.com/radxa/fip.git + + $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev + $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools + + $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz + $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt + + $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf- + $ export ARCH=arm + $ cd u-boot + $ make radxa-zero_defconfig + $ make + + $ cp u-boot.bin ../fip/radxa-zero/bl33.bin + $ cd ../fip/radxa-zero + $ make + +This will generate: + +.. code-block:: bash + + $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl + +Then write the image to SD with: + +.. code-block:: bash + + $ DEV=/dev/your_sd_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 From b703dcb0fe5d296bb55a8932147d9f754625b739 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 2 Sep 2021 12:02:06 +0200 Subject: [PATCH 032/228] arm: stm32: Disable ATAGs support These platforms never had to support an ATAGs-based Linux Kernel, so remove the options. Cc: Marek Vasut Signed-off-by: Tom Rini Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard Reviewed-by: Alexandru Gagniuc --- include/configs/stm32f429-discovery.h | 5 ----- include/configs/stm32f429-evaluation.h | 5 ----- include/configs/stm32f469-discovery.h | 5 ----- include/configs/stm32f746-disco.h | 5 ----- include/configs/stm32h743-disco.h | 5 ----- include/configs/stm32h743-eval.h | 5 ----- include/configs/stm32h750-art-pi.h | 5 ----- include/configs/stm32mp1.h | 5 ----- 8 files changed, 40 deletions(-) diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 9d029fbcc6..dbbce49475 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -27,11 +27,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (2 << 20) diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index fefdb2dd15..29a41e8067 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -29,11 +29,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index ba9f05a61b..b9b932c651 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -29,11 +29,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 08d050adfa..b72b989c2c 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -36,11 +36,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index 6e10dbdfe9..e5bb08eec7 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 268d39c7ad..89169f85d5 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index 3fd5461167..a9006e224a 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index b372838be8..fb4e4fb0bc 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -33,11 +33,6 @@ #define CONFIG_LOADADDR 0xc2000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. From e69c4143e82b848ba769e841930132f7548b5d23 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 2 Sep 2021 12:02:07 +0200 Subject: [PATCH 033/228] board: stm32: Remove the bi_boot_params initialization The stm32 platforms never had to support an ATAGs-based Linux Kernel, so remove the bi_boot_params initialization. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard Tested-by: Alexandru Gagniuc --- board/dhelectronics/dh_stm32mp1/board.c | 3 --- board/engicam/stm32mp1/stm32mp1.c | 3 --- board/st/stm32f429-discovery/stm32f429-discovery.c | 2 -- board/st/stm32f429-evaluation/stm32f429-evaluation.c | 2 -- board/st/stm32f469-discovery/stm32f469-discovery.c | 2 -- board/st/stm32f746-disco/stm32f746-disco.c | 2 -- board/st/stm32h743-disco/stm32h743-disco.c | 1 - board/st/stm32h743-eval/stm32h743-eval.c | 1 - board/st/stm32h750-art-pi/stm32h750-art-pi.c | 1 - board/st/stm32mp1/stm32mp1.c | 3 --- 10 files changed, 20 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d7c1857c16..765b54a4a4 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -590,9 +590,6 @@ static void board_init_fmc2(void) /* board dependent setup after realloc */ int board_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; - if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) gpio_hog_probe_all(); diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index 8bf9c9c67d..20d8603c78 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -40,9 +40,6 @@ int checkboard(void) /* board dependent setup after realloc */ int board_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; - if (IS_ENABLED(CONFIG_DM_REGULATOR)) regulators_enable_boot_on(_DEBUG); diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 46fcf907fc..5a50e98dd0 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -53,8 +53,6 @@ u32 get_board_rev(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - return 0; } diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 3b6df1f3ab..cf3056163c 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -47,8 +47,6 @@ u32 get_board_rev(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - return 0; } diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index c5df9b0d9c..056c9dff2a 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -47,8 +47,6 @@ u32 get_board_rev(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - return 0; } diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index efa38a0e26..2543e2a5f8 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -122,8 +122,6 @@ int board_late_init(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - #ifdef CONFIG_ETH_DESIGNWARE const char *phy_mode; int node; diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 4091d5f9fd..e493786f11 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -43,6 +43,5 @@ u32 get_board_rev(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; return 0; } diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 4091d5f9fd..e493786f11 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -43,6 +43,5 @@ u32 get_board_rev(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; return 0; } diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 5785b2e575..bec26465d2 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -53,6 +53,5 @@ int board_late_init(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; return 0; } diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 032f08d795..1bceb41494 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -646,9 +646,6 @@ static void board_ev1_init(void) /* board dependent setup after realloc */ int board_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; - if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) gpio_hog_probe_all(); From 5b4fa85d6501e77bd6ed8e5fd1e527927f9f947d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 14 Sep 2021 14:31:16 +0200 Subject: [PATCH 034/228] phy: stm32-usbphyc: use connector for vbus-supply with phy-stm32-usbphyc The vbus-supply is an optional property of sub-node connector node. and no more in the usb phyc node (in first proposed binding). This regulator for USB VBUS may be needed for host mode. See the latest kernel binding for details in Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml. usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; }; }; Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/phy/phy-stm32-usbphyc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 02d859a039..c206efd28d 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -339,7 +339,7 @@ static int stm32_usbphyc_probe(struct udevice *dev) { struct stm32_usbphyc *usbphyc = dev_get_priv(dev); struct reset_ctl reset; - ofnode node; + ofnode node, connector; int i, ret; usbphyc->base = dev_read_addr(dev); @@ -395,10 +395,12 @@ static int stm32_usbphyc_probe(struct udevice *dev) return ret; } - ret = stm32_usbphyc_get_regulator(node, "vbus-supply", - &usbphyc_phy->vbus); - if (ret) - usbphyc_phy->vbus = NULL; + usbphyc_phy->vbus = NULL; + connector = ofnode_find_subnode(node, "connector"); + if (ofnode_valid(connector)) { + ret = stm32_usbphyc_get_regulator(connector, "vbus-supply", + &usbphyc_phy->vbus); + } node = dev_read_next_subnode(node); } From 5d81616fb8f30f9ea16d2f32ab7365296f2ae886 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 14 Sep 2021 14:31:17 +0200 Subject: [PATCH 035/228] phy: stm32-usbphyc: stm32: usbphyc: add protection on phy sub-node Add protection on presence and order of the phy node sub node by using the mandatory reg information. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/phy/phy-stm32-usbphyc.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index c206efd28d..9c1dcfae52 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -340,7 +340,7 @@ static int stm32_usbphyc_probe(struct udevice *dev) struct stm32_usbphyc *usbphyc = dev_get_priv(dev); struct reset_ctl reset; ofnode node, connector; - int i, ret; + int ret; usbphyc->base = dev_read_addr(dev); if (usbphyc->base == FDT_ADDR_T_NONE) @@ -378,14 +378,18 @@ static int stm32_usbphyc_probe(struct udevice *dev) return ret; } - /* - * parse all PHY subnodes in order to populate regulator associated - * to each PHY port - */ - node = dev_read_first_subnode(dev); - for (i = 0; i < MAX_PHYS; i++) { - struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i; + /* parse all PHY subnodes to populate regulator associated to each PHY port */ + dev_for_each_subnode(node, dev) { + fdt_addr_t phy_id; + struct stm32_usbphyc_phy *usbphyc_phy; + phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE); + if (phy_id >= MAX_PHYS) { + dev_err(dev, "invalid reg value %lx for %s\n", + phy_id, ofnode_get_name(node)); + return -ENOENT; + } + usbphyc_phy = usbphyc->phys + phy_id; usbphyc_phy->init = false; usbphyc_phy->powered = false; ret = stm32_usbphyc_get_regulator(node, "phy-supply", @@ -401,8 +405,6 @@ static int stm32_usbphyc_probe(struct udevice *dev) ret = stm32_usbphyc_get_regulator(connector, "vbus-supply", &usbphyc_phy->vbus); } - - node = dev_read_next_subnode(node); } /* Check if second port has to be used for host controller */ From 2d0808161b2b07a21119c2037c088dae1ab80c0a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 Oct 2021 13:48:08 +0200 Subject: [PATCH 036/228] Revert "configs: stm32mp1: only support SD card after NOR in bootcmd_stm32mp" This reverts commit d5d726d3cc47691ace3c68fa31147ad104aaf579, which breaks boards which ship with multiple SD/eMMC sockets. This stm32mp1.h config is not used only by the ST reference boards, but all the other STM32MP1 based boards in U-Boot, so changes to this stm32mp1.h cannot break the other boards. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- include/configs/stm32mp1.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index fb4e4fb0bc..2dab1db6bb 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -115,7 +115,7 @@ * for serial/usb: execute the stm32prog command * for mmc boot (eMMC, SD card), boot only on the same device * for nand or spi-nand boot, boot with on ubifs partition on UBI partition - * for nor boot, use SD card = mmc0 + * for nor boot, use the default order */ #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ "echo \"Boot over ${boot_device}${boot_instance}!\";" \ @@ -128,8 +128,6 @@ "if test ${boot_device} = nand ||" \ " test ${boot_device} = spi-nand ;" \ "then env set boot_targets ubifs0; fi;" \ - "if test ${boot_device} = nor;" \ - "then env set boot_targets mmc0; fi;" \ "run distro_bootcmd;" \ "fi;\0" From cc30ea584ef8f3533448dd75716e8a4d28c9e495 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:05:52 +0200 Subject: [PATCH 037/228] Convert CONFIG_STM32_FLASH to Kconfig This converts the CONFIG_STM32_FLASH to Kconfig by using tools/moveconfig.py Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32f429-discovery_defconfig | 1 + configs/stm32f429-evaluation_defconfig | 1 + configs/stm32f469-discovery_defconfig | 1 + configs/stm32f746-disco_defconfig | 1 + configs/stm32f769-disco_defconfig | 1 + drivers/mtd/Kconfig | 7 +++++++ include/configs/stm32f429-discovery.h | 2 -- include/configs/stm32f429-evaluation.h | 2 -- include/configs/stm32f469-discovery.h | 2 -- include/configs/stm32f746-disco.h | 2 -- scripts/config_whitelist.txt | 1 - 11 files changed, 12 insertions(+), 9 deletions(-) diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index b0dcb38b3b..a84c297228 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -26,3 +26,4 @@ CONFIG_ENV_ADDR=0x8040000 # CONFIG_NET is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index b614182b4f..a15a68cee7 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -26,3 +26,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set CONFIG_ARM_PL180_MMCI=y CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 7960618d46..0b33e0b3c8 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -28,6 +28,7 @@ CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_PINCTRL_FULL is not set diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 05d7ec2d79..f13d714230 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -43,6 +43,7 @@ CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 40f94ac772..2706d41956 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -42,6 +42,7 @@ CONFIG_ARM_PL180_MMCI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_STM32_FLASH=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index b303fabe0f..ed69ea114e 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -109,6 +109,13 @@ config HBMC_AM654 This is the driver for HyperBus controller on TI's AM65x and other SoCs +config STM32_FLASH + bool "STM32 MCU Flash driver" + depends on ARCH_STM32 + help + This is the driver of embedded flash for some STMicroelectronics + STM32 MCU. + source "drivers/mtd/nand/Kconfig" source "drivers/mtd/spi/Kconfig" diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index dbbce49475..9b040a0ca3 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -23,8 +23,6 @@ #define CONFIG_RED_LED 110 #define CONFIG_GREEN_LED 109 -#define CONFIG_STM32_FLASH - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 29a41e8067..3b6223d737 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_STM32_FLASH - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index b9b932c651..6a0fa02451 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_STM32_FLASH - #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index b72b989c2c..247191a475 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_STM32_FLASH - #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) #define CONFIG_DW_ALTDESCRIPTOR diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a9c2380d17..ce02cb33ef 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1423,7 +1423,6 @@ CONFIG_STACKBASE CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STD_DEVICES_SETTINGS -CONFIG_STM32_FLASH CONFIG_STV0991 CONFIG_STV0991_HZ CONFIG_STV0991_HZ_CLOCK From 454994727d0937bb232f339cfd01bd78ca722828 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:23:41 +0200 Subject: [PATCH 038/228] configs: Move some usb config in defconfig Using the tools moveconfig.py to move the following config in the defconfig files: CONFIG_USB_HOST_ETHER CONFIG_USB_ETHER_ASIX CONFIG_USB_ETHER_MCS7830 CONFIG_USB_ETHER_SMSC95XX These option are already migrated since the commit f58ad98a621c ("usb: net: migrate USB Ethernet adapters to Kconfig") and the commit ae3584498bf8 ("usb: net: migrate CONFIG_USB_HOST_ETHER to Kconfig"). Signed-off-by: Patrick Delaunay Reviewed-by: Mark Kettenis Reviewed-by: Ian Ray Reviewed-by: Patrice Chotard --- configs/dh_imx6_defconfig | 2 ++ configs/kp_imx6q_tpc_defconfig | 2 ++ configs/mx53ppd_defconfig | 4 ++++ configs/stih410-b2260_defconfig | 4 ++++ include/configs/dh_imx6.h | 2 -- include/configs/kp_imx6q_tpc.h | 2 -- include/configs/mx53ppd.h | 4 ---- include/configs/stih410-b2260.h | 5 ----- 8 files changed, 12 insertions(+), 13 deletions(-) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index ce966420f8..a1206d238e 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -98,6 +98,8 @@ CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="dh" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 96c1061683..63c7b38755 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -79,5 +79,7 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 4a8fa34c27..f879133e94 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -69,6 +69,10 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 071dac96af..3ce7ca1eb7 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -50,6 +50,10 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x483 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index d9be1c38c4..0198126de5 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -58,8 +58,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 749e880f36..7216939265 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -30,8 +30,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b1e6a5638b..c9fecc3f9b 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -23,10 +23,6 @@ #define CONFIG_REVISION_TAG /* USB Configs */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 -#define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 33b34ee0cd..f35d26aa2e 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -65,11 +65,6 @@ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 -#define CONFIG_USB_ETHER_SMSC95XX - /* NET Configs */ #endif /* __CONFIG_H */ From c7f85e1f61dd4862787f08a4e5ec4e47a58b05e6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 6 Oct 2021 17:16:23 +0200 Subject: [PATCH 039/228] stm32f429: move CONFIG_BOOTCOMMAND in defconfig Move CONFIG_BOOTCOMMAND defined in Kconfig in the board defconfig. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32f429-discovery_defconfig | 1 + include/configs/stm32f429-discovery.h | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index a84c297228..06e4631d9f 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -10,6 +10,7 @@ CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_BOOTCOMMAND="run bootcmd_romfs" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 9b040a0ca3..d0ef18779f 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -29,9 +29,6 @@ #define CONFIG_SYS_MALLOC_LEN (2 << 20) -#define CONFIG_BOOTCOMMAND \ - "run bootcmd_romfs" - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ From 20a3969d33b1957e72a0e40b1bc9bcaf2623cd4e Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 6 Oct 2021 18:10:32 +0200 Subject: [PATCH 040/228] stv0991: remove specific CONFIG_STV0991 configs Remove the following STV0991 specific configs: - CONFIG_STV0991 (never used, only defined in CONFIG_SYS_EXTRA_OPTIONS) - CONFIG_STV0991_HZ (replaced by generic CONFIG_SYS_HZ) - CONFIG_STV0991_HZ_CLOCK (replaced by generic CONFIG_SYS_HZ_CLOCK) This patch allows to reduce the file config_whitelist.txt. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/cpu/armv7/stv0991/timer.c | 6 +++--- arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 4 ++-- configs/stv0991_defconfig | 1 - scripts/config_whitelist.txt | 3 --- 4 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 07033acb5c..67764ccf66 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) +#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff; rndoff = (usec % 10) ? 1 : 0; @@ -110,5 +110,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - return CONFIG_STV0991_HZ; + return CONFIG_SYS_HZ; } diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index cd27472ad7..f1d5667c32 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,7 +36,7 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_STV0991_HZ 1000 -#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) #endif diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 7fe5f99f4d..f516272844 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -10,7 +10,6 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x30000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="stv0991" -CONFIG_SYS_EXTRA_OPTIONS="STV0991" CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ce02cb33ef..a0eb1aaf2a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1423,9 +1423,6 @@ CONFIG_STACKBASE CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STD_DEVICES_SETTINGS -CONFIG_STV0991 -CONFIG_STV0991_HZ -CONFIG_STV0991_HZ_CLOCK CONFIG_SXNI855T CONFIG_SYSFS CONFIG_SYSMGR_ISWGRP_HANDOFF From b0e763b7b880494e0b5e96ba2ea5accc9f178926 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 6 Oct 2021 18:49:47 +0200 Subject: [PATCH 041/228] pm9263: Remove unused CONFIG_USER_LOWLEVEL_INIT Remove the latest reference of CONFIG_USER_LOWLEVEL_INIT in code Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/configs/pm9263.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index e825270de8..8d11759aa0 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -145,7 +145,6 @@ #define CONFIG_INITRD_TAG 1 #undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_USER_LOWLEVEL_INIT 1 /* * Hardware drivers diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a0eb1aaf2a..23ebeef775 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3410,7 +3410,6 @@ CONFIG_USB_TUSB_OMAP_DMA CONFIG_USB_ULPI_TIMEOUT CONFIG_USB_XHCI_EXYNOS CONFIG_USB_XHCI_OMAP -CONFIG_USER_LOWLEVEL_INIT CONFIG_USE_INTERRUPT CONFIG_USE_ONENAND_BOARD_INIT CONFIG_UTBIPAR_INIT_TBIPA From 646a1522478a30889354a378b2617b4c08d2c9fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 23 Sep 2021 11:07:18 +0200 Subject: [PATCH 042/228] arm: a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal possible size for allocated 128 MiB PCIe window. PCIe IO size in that commit was unchanged. Armada 3720 PCIe controller supports 32-bit IO space mapping so it is possible to assign more than 64 KiB if address space for IO. Currently controller has assigned 127 MiB + 64 KiB memory and therefore there is 960 KiB of unused memory. So assign it to IO space by increasing IO window from 64 KiB to 1 MiB. Signed-off-by: Pali Rohár Fixes: 079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB") Reviewed-by: Stefan Roese --- arch/arm/dts/armada-37xx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 2615b8c748..fec34609cf 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -335,14 +335,14 @@ /* * The 128 MiB address range [0xe8000000-0xf0000000] is * dedicated for PCIe and can be assigned to 8 windows - * with size a power of two. Use one 64 KiB window for + * with size a power of two. Use one 1 MiB window for * IO at the end and the remaining seven windows * (totaling 127 MiB) for MEM. */ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */ - 0x81000000 0 0xefff0000 - 0 0xefff0000 0 0x10000>; /* Port 0 IO*/ + 0x81000000 0 0xeff00000 + 0 0xeff00000 0 0x100000>; /* Port 0 IO*/ }; }; }; From 4adb16b29a31590f536b72e635370aff73732b4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 16:11:55 +0200 Subject: [PATCH 043/228] phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 2 +- drivers/phy/marvell/comphy_a3700.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 06822d1d12..504f4b2bb1 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) * 6. Enable the output of 100M/125M/500M clock */ reg_set16(phy_addr(PCIE, MISC_REG0), - 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); + 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF); /* * 7. Enable TX diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 8748c6c84a..23c8ffbff4 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr) #define MISC_REG0 0x4f #define rb_clk100m_125m_en BIT(4) +#define rb_txdclk_2x_sel BIT(6) #define rb_clk500m_en BIT(7) #define rb_ref_clk_sel BIT(10) From 4ca474d3067ba7278c6a5f94ff4340ca5a07ca0a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 16:11:56 +0200 Subject: [PATCH 044/228] phy: marvell: a3700: Fix configuring polarity invert bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit phy_txd_inv or phy_rxd_inv needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406 Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 504f4b2bb1..69cd63edb1 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -230,9 +230,13 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) */ if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); + else + reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv); if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); + else + reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv); /* * 11. Release SW reset @@ -467,9 +471,13 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) */ if (invert & COMPHY_POLARITY_TXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); + else + usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane); if (invert & COMPHY_POLARITY_RXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); + else + usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane); /* * 10. Set max speed generation to USB3.0 5Gbps @@ -839,9 +847,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) */ if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); + else + reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv); if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); + else + reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv); /* * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 From 021a98a2d6512bf59581675a997d659b18c09306 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 16:11:57 +0200 Subject: [PATCH 045/228] phy: marvell: a3700: Return correct error code when power up fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 69cd63edb1..047c8bb045 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -594,24 +594,30 @@ static int comphy_usb2_power_up(u8 usb32) rb_usb2phy_pllcal_done, /* value */ rb_usb2phy_pllcal_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (!ret) + if (!ret) { printf("Failed to end USB2 PLL calibration\n"); + goto out; + } /* Assert impedance calibration done */ ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32), rb_usb2phy_impcal_done, /* value */ rb_usb2phy_impcal_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (!ret) + if (!ret) { printf("Failed to end USB2 impedance calibration\n"); + goto out; + } /* Assert squetch calibration done */ ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32), rb_usb2phy_sqcal_done, /* value */ rb_usb2phy_sqcal_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (!ret) + if (!ret) { printf("Failed to end USB2 unknown calibration\n"); + goto out; + } /* Assert PLL is ready */ ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32), @@ -619,9 +625,12 @@ static int comphy_usb2_power_up(u8 usb32) rb_usb2phy_pll_ready, /* mask */ POLL_32B_REG); /* 32bit */ - if (!ret) + if (!ret) { printf("Failed to lock USB2 PLL\n"); + goto out; + } +out: debug_exit(); return ret; @@ -873,8 +882,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) rb_pll_ready_tx | rb_pll_ready_rx, /* value */ rb_pll_ready_tx | rb_pll_ready_rx, /* mask */ POLL_32B_REG); /* 32bit */ - if (!ret) + if (!ret) { printf("Failed to lock PLL for SGMII PHY %d\n", lane); + goto out; + } /* * 21. Set COMPHY input port PIN_TX_IDLE=0 @@ -895,14 +906,17 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) rb_rx_init_done, /* value */ rb_rx_init_done, /* mask */ POLL_32B_REG); /* 32bit */ - if (!ret) + if (!ret) { printf("Failed to init RX of SGMII PHY %d\n", lane); + goto out; + } /* * Restore saved selector. */ reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF); +out: debug_exit(); return ret; From cfd4a8ad0f205be4270c382a1a2ce2701b2ddde7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:14 +0200 Subject: [PATCH 046/228] arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace magic register offsets by macros to make code more readable. Add comments about what this code is doing. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- .../serdes/a38x/high_speed_env_spec.c | 37 +++++++++++++------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index bb7d24b4b7..7b4710501d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1721,31 +1721,44 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, reg_data &= ~0x4000; reg_write(SOC_CONTROL_REG1, reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x6c)); + /* Set Maximum Link Width to X1 or X4 */ + reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG)); reg_data &= ~0x3f0; if (is_pex_by1 == 1) reg_data |= 0x10; else reg_data |= 0x40; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), + reg_write(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG), reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x6c)); + /* Set Maximum Link Speed to 5 GT/s */ + reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG)); reg_data &= ~0xf; reg_data |= 0x2; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), + reg_write(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CAPABILITY_REG), reg_data); - reg_data = - reg_read(((PEX_IF_REGS_BASE(pex_idx)) + - 0x70)); + /* + * Set Common Clock Configuration to indicates + * that both devices on the link use a + * distributed common reference clock. + */ + reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CTRL_STAT_REG)); reg_data &= ~0x40; reg_data |= 0x40; - reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70), + reg_write(PEX_CFG_DIRECT_ACCESS( + pex_idx, + PEX_LINK_CTRL_STAT_REG), reg_data); } From eb5d31645e1160345389d68b263d72112f5b9c46 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:15 +0200 Subject: [PATCH 047/228] arm: mvebu: a38x: serdes: Remove duplicate macro SOC_CTRL_REG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SoC Control 1 Register (offset 0x18204) is already defined by macro SOC_CONTROL_REG1. Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c code and remove the other definition. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 4 ++-- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 4 ---- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index adef3331a7..717bcfb29c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -49,7 +49,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); } - tmp = reg_read(SOC_CTRL_REG); + tmp = reg_read(SOC_CONTROL_REG1); tmp &= ~0x03; for (idx = 0; idx < count; idx++) { @@ -79,7 +79,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) } } - reg_write(SOC_CTRL_REG, tmp); + reg_write(SOC_CONTROL_REG1, tmp); /* Support gen1/gen2 */ DEBUG_INIT_FULL_S("Support gen1/gen2\n"); diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index 3f30b6bf97..a882d24208 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -14,10 +14,6 @@ /* PCI Express Control and Status Registers */ #define MAX_PEX_BUSSES 256 -#define MISC_REGS_OFFSET 0x18200 -#define MV_MISC_REGS_BASE MISC_REGS_OFFSET -#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) - #define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \ (0x40000 + ((if) - 1) * 0x4000) : \ 0x80000) From 2d5f51f680be9461f87f0c99b55c68ad68633078 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:16 +0200 Subject: [PATCH 048/228] arm: mvebu: a38x: serdes: Add comments for hws_pex_config() code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add comments to understand what this magic code is doing. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index 717bcfb29c..0eb31d589c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -42,6 +42,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) continue; } + /* Set Device/Port Type to RootComplex */ pex_idx = serdes_type - PEX0; tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); tmp &= ~(0xf << 20); @@ -122,12 +123,18 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) } next_busno++; + + /* + * Read maximum link speed. It must be 0x2 (5.0 GT/s) as this + * value was set in serdes_power_up_ctrl() function. + */ temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS (pex_idx, PEX_LINK_CAPABILITY_REG))); temp_pex_reg &= 0xf; if (temp_pex_reg != 0x2) continue; + /* Read negotiated link speed */ temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( pex_idx, PEX_LINK_CTRL_STAT_REG)) & @@ -155,6 +162,7 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) continue; } + /* Find start of the PCI Express Capability registers */ while ((pex_config_read(pex_idx, first_busno, 0, 0, addr) & 0xff) != 0x10) { addr = (pex_config_read(pex_idx, first_busno, 0, @@ -173,11 +181,15 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx)); DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); tmp &= ~(BIT(0) | BIT(1)); - tmp |= BIT(1); + tmp |= BIT(1); /* Force Target Link Speed to 5.0 GT/s */ tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */ reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); + /* + * Enable Auto Speed change. When set, link will issue link + * speed change to max possible link speed. + */ tmp = reg_read(PEX_CTRL_REG(pex_idx)); DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp); tmp |= BIT(10); From 3bedbcc3aa1865de3de55ca1abfa8d06d33df3b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:17 +0200 Subject: [PATCH 049/228] arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register are read-only SAR registers and are initialized according to current mode configured by PCIe controller. Changing PCIe controller mode (from Root Complex mode to Endpoint mode or the other way) is possible via PCI Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This has to be done in PCIe controller driver (in our case pci_mvebu.c). Note that default mode is Root Complex. Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are platform specific and overwriting them does not make sense. They are set by PCIe controller according to current SerDes configuration. For A38x it is 5.0 GT/s if SerDes supports appropriate speed. Maximum Link Width bits of PCIe Root Port Link Capabilities Register are read-only SAR registers, but unfortunately if this is not set correctly here, then access PCI config space of the endpoint card behind this Root Port does not work. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 22 ---------- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 4 ++ .../serdes/a38x/high_speed_env_spec.c | 40 +++++++------------ 3 files changed, 19 insertions(+), 47 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index 0eb31d589c..7c18df8113 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -28,28 +28,6 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n"); - for (idx = 0; idx < count; idx++) { - serdes_type = serdes_map[idx].serdes_type; - /* configuration for PEX only */ - if ((serdes_type != PEX0) && (serdes_type != PEX1) && - (serdes_type != PEX2) && (serdes_type != PEX3)) - continue; - - if ((serdes_type != PEX0) && - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { - /* for PEX by4 - relevant for the first port only */ - continue; - } - - /* Set Device/Port Type to RootComplex */ - pex_idx = serdes_type - PEX0; - tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); - tmp &= ~(0xf << 20); - tmp |= (0x4 << 20); - reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); - } - tmp = reg_read(SOC_CONTROL_REG1); tmp &= ~0x03; diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index a882d24208..5d70166fc5 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -6,8 +6,12 @@ #ifndef _CTRL_PEX_H #define _CTRL_PEX_H +#include #include "high_speed_env_spec.h" +/* Direct access to PEX0 Root Port's PCIe Capability structure */ +#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) + /* Sample at Reset */ #define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4)) diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 7b4710501d..c089479a9b 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1712,7 +1712,7 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, (serdes_mode == PEX_END_POINT_X1); pex_idx = serdes_type - PEX0; - if ((is_pex_by1 == 1) || (serdes_type == PEX0)) { + if (serdes_type == PEX0) { /* For PEX by 4, init only the PEX 0 */ reg_data = reg_read(SOC_CONTROL_REG1); if (is_pex_by1 == 1) @@ -1721,30 +1721,20 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, reg_data &= ~0x4000; reg_write(SOC_CONTROL_REG1, reg_data); - /* Set Maximum Link Width to X1 or X4 */ - reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CAPABILITY_REG)); - reg_data &= ~0x3f0; - if (is_pex_by1 == 1) - reg_data |= 0x10; - else - reg_data |= 0x40; - reg_write(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CAPABILITY_REG), - reg_data); - - /* Set Maximum Link Speed to 5 GT/s */ - reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CAPABILITY_REG)); - reg_data &= ~0xf; - reg_data |= 0x2; - reg_write(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CAPABILITY_REG), - reg_data); + /* + * Set Maximum Link Width to X1 or X4 in Root + * Port's PCIe Link Capability register. + * This register is read-only but if is not set + * correctly then access to PCI config space of + * endpoint card behind this Root Port does not + * work. + */ + reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET + + PCI_EXP_LNKCAP); + reg_data &= ~PCI_EXP_LNKCAP_MLW; + reg_data |= (is_pex_by1 ? 1 : 4) << 4; + reg_write(PEX0_RP_PCIE_CFG_OFFSET + + PCI_EXP_LNKCAP, reg_data); /* * Set Common Clock Configuration to indicates From 3fc8b90d68e1524275a126d659dc31d8b1246772 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:18 +0200 Subject: [PATCH 050/228] arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling Common Clock Configuration bit in PCIe Root Port Link Control Register should not be done unconditionally. It is enabled by operating system as part of ASPM. Also after enabling Common Clock Configuration it is required to do more work, like retraining link. Some cards may be broken due to this incomplete Common Clock Configuration and some cards are broken and do not support ASPM at all. Remove this incomplete code for Common Clock Configuration. It really should not be done in SerDes code as it is not related to SerDes, but to PCIe subsystem. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- .../mach-mvebu/serdes/a38x/high_speed_env_spec.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index c089479a9b..d2bc3ab25c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1735,21 +1735,6 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, reg_data |= (is_pex_by1 ? 1 : 4) << 4; reg_write(PEX0_RP_PCIE_CFG_OFFSET + PCI_EXP_LNKCAP, reg_data); - - /* - * Set Common Clock Configuration to indicates - * that both devices on the link use a - * distributed common reference clock. - */ - reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CTRL_STAT_REG)); - reg_data &= ~0x40; - reg_data |= 0x40; - reg_write(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CTRL_STAT_REG), - reg_data); } CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ)); From db5ea818ce8fed95931169bbc487a64e959552d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:19 +0200 Subject: [PATCH 051/228] arm: mvebu: a38x: serdes: Don't overwrite PCI device ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI device ID is part of the PCIe controller SoC / revision. For Root Complex mode (which is the default and the only mode supported currently by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device. If there is some issue with this device ID, it should be set / updated by PCIe controller driver (pci_mvebu.c), as this register resides in address space of the controller. It shouldn't be done in SerDes initialization code. In the worst case (a specific board for example) it could be done via U-Boot's weak function board_pex_config(). But it should not be overwritten globally for all A38x devices. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 27 ---------------------- 1 file changed, 27 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index 7c18df8113..a7e45a5550 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -186,33 +186,6 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) (": Link upgraded to Gen2 based on client capabilities\n"); } - /* Update pex DEVICE ID */ - ctrl_mode = sys_env_model_get(); - - for (idx = 0; idx < count; idx++) { - serdes_type = serdes_map[idx].serdes_type; - /* configuration for PEX only */ - if ((serdes_type != PEX0) && (serdes_type != PEX1) && - (serdes_type != PEX2) && (serdes_type != PEX3)) - continue; - - if ((serdes_type != PEX0) && - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { - /* for PEX by4 - relevant for the first port only */ - continue; - } - - pex_idx = serdes_type - PEX0; - dev_id = reg_read(PEX_CFG_DIRECT_ACCESS - (pex_idx, PEX_DEVICE_AND_VENDOR_ID)); - dev_id &= 0xffff; - dev_id |= ((ctrl_mode << 16) & 0xffff0000); - reg_write(PEX_CFG_DIRECT_ACCESS - (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id); - } - DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4); - return MV_OK; } From 177ee6c77ed5de8f3a2c468d24a92b22d73b2239 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:20 +0200 Subject: [PATCH 052/228] arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code is trying to parse PCIe config space of PCIe card connected on the other end of link and then is trying to force 5.0 GT/s speed via Target Link Speed bits in PCIe Root Port Link Control 2 Register on the local part of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in Link Capabilities Register. The code is incorrect for more reasons: - Accessing config space of an endpoint card cannot be done immediately. If the PCIe link is not up, reading vendor/device ID registers will return all ones. - Parsing is incomplete, so it can cause issues even for working cards. Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from 2.5 GT/s to 5.0 GT/s autonomously when it is supported. Most importantly, this code does not change link speed at all, since because after updating Target Link Speed bits on PCIe Root Port Link Control 2 Register, it is required to retrain the link, and the code for that is completely missing. The code was probably needed for making buggy endpoint cards work. Such a workaround, though, should be implemented via PCIe subsystem (via quirks, for example), as buggy cards could also affect other PCIe controllers. Note that this code is fully unrelated to a38x SerDes code and really should not have been included in SerDes initialization. Usage of magic constants without names and comments made this SerDes code hard to read and understand. Remove this PCIe application code from low level SerDes code. As this code is configuring only 5.0 GT/s part, in the worst case, it could leave buggy cards at the initial speed of 2.5 GT/s (if somehow before this change they could have been "upgraded" to 5.0 GT/s speed even with missing link retraining). Compliant cards which just need longer initialization should work better after this change. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 128 +-------------------- 1 file changed, 1 insertion(+), 127 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index a7e45a5550..0445b43def 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -21,10 +21,8 @@ __weak void board_pex_config(void) int hws_pex_config(const struct serdes_map *serdes_map, u8 count) { - u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg, - temp_reg, addr, dev_id, ctrl_mode; enum serdes_type serdes_type; - u32 idx; + u32 idx, tmp; DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n"); @@ -60,132 +58,8 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) reg_write(SOC_CONTROL_REG1, tmp); - /* Support gen1/gen2 */ - DEBUG_INIT_FULL_S("Support gen1/gen2\n"); - board_pex_config(); - next_busno = 0; - mdelay(150); - - for (idx = 0; idx < count; idx++) { - serdes_type = serdes_map[idx].serdes_type; - DEBUG_INIT_FULL_S(" serdes_type=0x"); - DEBUG_INIT_FULL_D(serdes_type, 8); - DEBUG_INIT_FULL_S("\n"); - DEBUG_INIT_FULL_S(" idx=0x"); - DEBUG_INIT_FULL_D(idx, 8); - DEBUG_INIT_FULL_S("\n"); - - /* Configuration for PEX only */ - if ((serdes_type != PEX0) && (serdes_type != PEX1) && - (serdes_type != PEX2) && (serdes_type != PEX3)) - continue; - - if ((serdes_type != PEX0) && - ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) || - (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) { - /* for PEX by4 - relevant for the first port only */ - continue; - } - - pex_idx = serdes_type - PEX0; - tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx)); - - first_busno = next_busno; - if ((tmp & 0x7f) != 0x7e) { - DEBUG_INIT_S("PCIe, Idx "); - DEBUG_INIT_D(pex_idx, 1); - DEBUG_INIT_S(": detected no link\n"); - continue; - } - - next_busno++; - - /* - * Read maximum link speed. It must be 0x2 (5.0 GT/s) as this - * value was set in serdes_power_up_ctrl() function. - */ - temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS - (pex_idx, PEX_LINK_CAPABILITY_REG))); - temp_pex_reg &= 0xf; - if (temp_pex_reg != 0x2) - continue; - - /* Read negotiated link speed */ - temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CTRL_STAT_REG)) & - 0xf0000) >> 16; - - /* Check if the link established is GEN1 */ - DEBUG_INIT_FULL_S - ("Checking if the link established is gen1\n"); - if (temp_reg != 0x1) - continue; - - pex_local_bus_num_set(pex_idx, first_busno); - pex_local_dev_num_set(pex_idx, 1); - DEBUG_INIT_FULL_S("PCIe, Idx "); - DEBUG_INIT_FULL_D(pex_idx, 1); - - DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n"); - /* link is Gen1, check the EP capability */ - addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff; - DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4); - if (addr == 0xff) { - DEBUG_INIT_FULL_C - ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.", - pex_idx, 1); - continue; - } - - /* Find start of the PCI Express Capability registers */ - while ((pex_config_read(pex_idx, first_busno, 0, 0, addr) - & 0xff) != 0x10) { - addr = (pex_config_read(pex_idx, first_busno, 0, - 0, addr) & 0xff00) >> 8; - } - - /* Check for Gen2 and above */ - if ((pex_config_read(pex_idx, first_busno, 0, 0, - addr + 0xc) & 0xf) < 0x2) { - DEBUG_INIT_S("PCIe, Idx "); - DEBUG_INIT_D(pex_idx, 1); - DEBUG_INIT_S(": remains Gen1\n"); - continue; - } - - tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx)); - DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); - tmp &= ~(BIT(0) | BIT(1)); - tmp |= BIT(1); /* Force Target Link Speed to 5.0 GT/s */ - tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */ - reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); - DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); - - /* - * Enable Auto Speed change. When set, link will issue link - * speed change to max possible link speed. - */ - tmp = reg_read(PEX_CTRL_REG(pex_idx)); - DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp); - tmp |= BIT(10); - reg_write(PEX_CTRL_REG(pex_idx), tmp); - DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp); - - /* - * We need to wait 10ms before reading the PEX_DBG_STATUS_REG - * in order not to read the status of the former state - */ - mdelay(10); - - DEBUG_INIT_S("PCIe, Idx "); - DEBUG_INIT_D(pex_idx, 1); - DEBUG_INIT_S - (": Link upgraded to Gen2 based on client capabilities\n"); - } - return MV_OK; } From 28c935b5ee3ab8d437f28df739c0ea1027db6b5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:21 +0200 Subject: [PATCH 053/228] arm: mvebu: a38x: serdes: Remove unused PCIe macros and functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unused PCIe functions from SerDes code. They are unused and are duplicated either from generic PCIe code or from pci_mvebu.c. Remove also unused PCIe macros from SerDes code. They are just obfuscated variants of standards macros in include/pci.h or in pci_mvebu.c. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 128 --------------------- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 60 ---------- 2 files changed, 188 deletions(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c index 0445b43def..55c3f9ca39 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c @@ -62,131 +62,3 @@ int hws_pex_config(const struct serdes_map *serdes_map, u8 count) return MV_OK; } - -int pex_local_bus_num_set(u32 pex_if, u32 bus_num) -{ - u32 pex_status; - - DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n"); - - if (bus_num >= MAX_PEX_BUSSES) { - DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n", - bus_num, 4); - return MV_BAD_PARAM; - } - - pex_status = reg_read(PEX_STATUS_REG(pex_if)); - pex_status &= ~PXSR_PEX_BUS_NUM_MASK; - pex_status |= - (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; - reg_write(PEX_STATUS_REG(pex_if), pex_status); - - return MV_OK; -} - -int pex_local_dev_num_set(u32 pex_if, u32 dev_num) -{ - u32 pex_status; - - DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n"); - - pex_status = reg_read(PEX_STATUS_REG(pex_if)); - pex_status &= ~PXSR_PEX_DEV_NUM_MASK; - pex_status |= - (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; - reg_write(PEX_STATUS_REG(pex_if), pex_status); - - return MV_OK; -} - -/* - * pex_config_read - Read from configuration space - * - * DESCRIPTION: - * This function performs a 32 bit read from PEX configuration space. - * It supports both type 0 and type 1 of Configuration Transactions - * (local and over bridge). In order to read from local bus segment, use - * bus number retrieved from pex_local_bus_num_get(). Other bus numbers - * will result configuration transaction of type 1 (over bridge). - * - * INPUT: - * pex_if - PEX interface number. - * bus - PEX segment bus number. - * dev - PEX device number. - * func - Function number. - * reg_offs - Register offset. - * - * OUTPUT: - * None. - * - * RETURN: - * 32bit register data, 0xffffffff on error - */ -u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off) -{ - u32 pex_data = 0; - u32 local_dev, local_bus; - u32 pex_status; - - pex_status = reg_read(PEX_STATUS_REG(pex_if)); - local_dev = - ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS); - local_bus = - ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS); - - /* - * In PCI Express we have only one device number - * and this number is the first number we encounter - * else that the local_dev - * spec pex define return on config read/write on any device - */ - if (bus == local_bus) { - if (local_dev == 0) { - /* - * if local dev is 0 then the first number we encounter - * after 0 is 1 - */ - if ((dev != 1) && (dev != local_dev)) - return MV_ERROR; - } else { - /* - * if local dev is not 0 then the first number we - * encounter is 0 - */ - if ((dev != 0) && (dev != local_dev)) - return MV_ERROR; - } - } - - /* Creating PEX address to be passed */ - pex_data = (bus << PXCAR_BUS_NUM_OFFS); - pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS); - pex_data |= (func << PXCAR_FUNC_NUM_OFFS); - /* Legacy register space */ - pex_data |= (reg_off & PXCAR_REG_NUM_MASK); - /* Extended register space */ - pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >> - PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); - pex_data |= PXCAR_CONFIG_EN; - - /* Write the address to the PEX configuration address register */ - reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data); - - /* - * In order to let the PEX controller absorbed the address - * of the read transaction we perform a validity check that - * the address was written - */ - if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if))) - return MV_ERROR; - - /* Cleaning Master Abort */ - reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND), - PXSAC_MABORT); - /* Read the Data returned in the PEX Data register */ - pex_data = reg_read(PEX_CFG_DATA_REG(pex_if)); - - DEBUG_INIT_FULL_C(" --> ", pex_data, 4); - - return pex_data; -} diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index 5d70166fc5..55a4c267c4 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -12,28 +12,6 @@ /* Direct access to PEX0 Root Port's PCIe Capability structure */ #define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) -/* Sample at Reset */ -#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4)) - -/* PCI Express Control and Status Registers */ -#define MAX_PEX_BUSSES 256 - -#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \ - (0x40000 + ((if) - 1) * 0x4000) : \ - 0x80000) -#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if)) -#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60) -#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90) -#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00) -#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04) -#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64) -#define PEX_LINK_CAPABILITY_REG 0x6c -#define PEX_LINK_CTRL_STAT_REG 0x70 -#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) - /* PEX_CAPABILITIES_REG fields */ #define PCIE0_ENABLE_OFFS 0 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) @@ -44,45 +22,7 @@ #define PCIE3_ENABLE_OFFS 3 #define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS) -/* Controller revision info */ -#define PEX_DEVICE_AND_VENDOR_ID 0x000 -#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg)) - -/* PCI Express Configuration Address Register */ -#define PXCAR_REG_NUM_OFFS 2 -#define PXCAR_REG_NUM_MAX 0x3f -#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \ - PXCAR_REG_NUM_OFFS) -#define PXCAR_FUNC_NUM_OFFS 8 -#define PXCAR_FUNC_NUM_MAX 0x7 -#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \ - PXCAR_FUNC_NUM_OFFS) -#define PXCAR_DEVICE_NUM_OFFS 11 -#define PXCAR_DEVICE_NUM_MAX 0x1f -#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \ - PXCAR_DEVICE_NUM_OFFS) -#define PXCAR_BUS_NUM_OFFS 16 -#define PXCAR_BUS_NUM_MAX 0xff -#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \ - PXCAR_BUS_NUM_OFFS) -#define PXCAR_EXT_REG_NUM_OFFS 24 -#define PXCAR_EXT_REG_NUM_MAX 0xf - -#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8) -#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc) - -#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS) - -#define PXCAR_CONFIG_EN BIT(31) -#define PEX_STATUS_AND_COMMAND 0x004 -#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */ - int hws_pex_config(const struct serdes_map *serdes_map, u8 count); -int pex_local_bus_num_set(u32 pex_if, u32 bus_num); -int pex_local_dev_num_set(u32 pex_if, u32 dev_num); -u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off); - void board_pex_config(void); #endif From de7293043329c6d230b7f81861867c6a645f4dc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 22:59:22 +0200 Subject: [PATCH 054/228] arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index 55a4c267c4..64193d5288 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -12,7 +12,7 @@ /* Direct access to PEX0 Root Port's PCIe Capability structure */ #define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) -/* PEX_CAPABILITIES_REG fields */ +/* SOC_CONTROL_REG1 fields */ #define PCIE0_ENABLE_OFFS 0 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) #define PCIE1_ENABLE_OFFS 1 From 6b2771cb19623f7028085e47a52e30813130f61e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 26 Sep 2021 00:54:41 +0200 Subject: [PATCH 055/228] arm: a37xx: pci: Fix pcie_advk_link_up() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Aardvark reports Disabled and Hot Reset LTSSM states as values >= 0x20. Link is not up in these states, so fix pcie_advk_link_up() function. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index cf6e30f936..741e0431e1 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -145,6 +145,7 @@ #define LTSSM_SHIFT 24 #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 +#define LTSSM_DISABLED 0x20 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ @@ -569,7 +570,7 @@ static int pcie_advk_link_up(struct pcie_advk *pcie) val = advk_readl(pcie, CFG_REG); ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; - return ltssm_state >= LTSSM_L0; + return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED; } /** From cb056005dc674fb5fce89d2b7bdc37594b180b68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 26 Sep 2021 00:54:42 +0200 Subject: [PATCH 056/228] arm: a37xx: pci: Add support for accessing PCI Bridge on root bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Aardvark does not have a real PCIe Root Port device on the root bus. Instead it has PCIe registers of PCIe Root Port device mapped in internal Aardvark memory space starting at offset 0xc0. The PCIe Root Port itself is normally available as a PCI Bridge device on the root bus with bus number zero. Aardvark instead has the configuration registers of this PCI Bridge at offset 0x00 of Aardvark's memory space, but the class code of this device is Mass Storage Controller (0x010400), instead of PCI Bridge (0x600400), which causes U-Boot to fail to recognize it as a P2P Bridge Add a hook into the pcie_advk_read_config() / pcie_advk_write_config() functions to redirect access for root bus from PIO transfer to this internal Aardvark memory space. This will allow U-Boot to access configuration space of this PCI Bridge which represents PCIe Root Port. Redirect access to PCI Bridge registers in range 0x10 - 0x34 to driver's internal buffer (cfgcache[]). This is because at those addresses Aardvark has different registers, incompatible with config space of a PCI Bridge. Redirect access to PCI Bridge register PCI_ROM_ADDRESS1 (0x38) to Aardvark internal address for that register (0x30). When reading PCI Bridge register PCI_HEADER_TYPE, set it explicitly to value Type 1 (PCI_HEADER_TYPE_BRIDGE) as PCI Bridge must be of Type 1. When writing to PCI_PRIMARY_BUS or PCI_SECONDARY_BUS registers on this PCI Bridge, correctly update driver's first_busno and sec_busno variables, so that pcie_advk_addr_valid() function can check if address of any device behind the root bus is valid and that PIO transfers are started with correct config type (1 vs 0), which is required for accessing devices behind some PCI bridge after the root bus. U-Boot's PCI_PNP code sets primary and secondary bus numbers as relative to the configured bus number of the root bus. This is done so that U-Boot can support multiple PCIe host bridges or multiple root port buses, when internal bus numbers are different. Now that root bus is available, update code in pcie_advk_read_config() and pcie_advk_write_config() functions to correctly calculate real Aardvark bus number of the target device from U-Boot's bus number as: busno = PCI_BUS(bdf) - dev_seq(bus) Stefan: Small fix of header masking as suggested by Pali. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 147 +++++++++++++++++++++++++++++++------ 1 file changed, 126 insertions(+), 21 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 741e0431e1..082fdc3b74 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -39,6 +39,8 @@ #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) +#define PCIE_CORE_DEV_REV_REG 0x8 +#define PCIE_CORE_EXP_ROM_BAR_REG 0x30 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) @@ -163,7 +165,7 @@ #define PCIE_CONFIG_WR_TYPE1 0xb /* PCI_BDF shifts 8bit, so we need extra 4bit shift */ -#define PCIE_BDF(dev) (dev << 4) +#define PCIE_BDF(b, d, f) (PCI_BDF(b, d, f) << 4) #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) @@ -188,13 +190,17 @@ * first_busno stores the bus number of the PCIe root-port * number which may vary depending on the PCIe setup * (PEX switches etc). + * @sec_busno: sec_busno stores the bus number for the device behind + * the PCIe root-port * @device: The pointer to PCI uclass device. */ struct pcie_advk { void *base; int first_busno; + int sec_busno; struct udevice *dev; struct gpio_desc reset_gpio; + u32 cfgcache[0x34 - 0x10]; }; static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) @@ -210,22 +216,30 @@ static inline uint advk_readl(struct pcie_advk *pcie, uint reg) /** * pcie_advk_addr_valid() - Check for valid bus address * + * @pcie: Pointer to the PCI bus + * @busno: Bus number of PCI device + * @dev: Device number of PCI device + * @func: Function number of PCI device * @bdf: The PCI device to access - * @first_busno: Bus number of the PCIe controller root complex * - * Return: 1 on valid, 0 on invalid + * Return: true on valid, false on invalid */ -static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno) +static bool pcie_advk_addr_valid(struct pcie_advk *pcie, + int busno, u8 dev, u8 func) { - /* - * In PCIE-E only a single device (0) can exist - * on the local bus. Beyound the local bus, there might be - * a Switch and everything is possible. - */ - if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0)) - return 0; + /* On the primary (local) bus there is only one PCI Bridge */ + if (busno == pcie->first_busno && (dev != 0 || func != 0)) + return false; - return 1; + /* + * In PCI-E only a single device (0) can exist on the secondary bus. + * Beyond the secondary bus, there might be a Switch and anything is + * possible. + */ + if (busno == pcie->sec_busno && dev != 0) + return false; + + return true; } /** @@ -355,20 +369,55 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + int busno = PCI_BUS(bdf) - dev_seq(bus); int retry_count; bool allow_crs; + ulong data; uint reg; int ret; dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); - if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) { + if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) { dev_dbg(pcie->dev, "- out of range\n"); *valuep = pci_get_ff(size); return 0; } + /* + * The configuration space of the PCI Bridge on primary (local) bus is + * not accessible via PIO transfers like all other PCIe devices. PCI + * Bridge config registers are available directly in Aardvark memory + * space starting at offset zero. Moreover PCI Bridge registers in the + * range 0x10 - 0x34 are not available and register 0x38 (Expansion ROM + * Base Address) is at offset 0x30. + * We therefore read configuration space content of the primary PCI + * Bridge from our virtual cache. + */ + if (busno == pcie->first_busno) { + if (offset >= 0x10 && offset < 0x34) + data = pcie->cfgcache[(offset - 0x10) / 4]; + else if ((offset & ~3) == PCI_ROM_ADDRESS1) + data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); + else + data = advk_readl(pcie, offset & ~3); + + if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) { + /* + * Change Header Type of PCI Bridge device to Type 1 + * (0x01, used by PCI Bridges) because hardwired value + * is Type 0 (0x00, used by Endpoint devices). + */ + data &= ~0x007f0000; + data |= PCI_HEADER_TYPE_BRIDGE << 16; + } + + *valuep = pci_conv_32_to_size(data, offset, size); + + return 0; + } + /* * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and @@ -396,14 +445,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, /* Program the control register */ reg = advk_readl(pcie, PIO_CTRL); reg &= ~PIO_CTRL_TYPE_MASK; - if (PCI_BUS(bdf) == pcie->first_busno) + if (busno == pcie->sec_busno) reg |= PCIE_CONFIG_RD_TYPE0; else reg |= PCIE_CONFIG_RD_TYPE1; advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset); + reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); @@ -491,7 +540,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + int busno = PCI_BUS(bdf) - dev_seq(bus); int retry_count; + ulong data; uint reg; int ret; @@ -500,11 +551,41 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value); - if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) { + if (!pcie_advk_addr_valid(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) { dev_dbg(pcie->dev, "- out of range\n"); return 0; } + /* + * As explained in pcie_advk_read_config(), for the configuration + * space of the primary PCI Bridge, we write the content into virtual + * cache. + */ + if (busno == pcie->first_busno) { + if (offset >= 0x10 && offset < 0x34) { + data = pcie->cfgcache[(offset - 0x10) / 4]; + data = pci_conv_size_to_32(data, value, offset, size); + pcie->cfgcache[(offset - 0x10) / 4] = data; + } else if ((offset & ~3) == PCI_ROM_ADDRESS1) { + data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); + data = pci_conv_size_to_32(data, value, offset, size); + advk_writel(pcie, data, PCIE_CORE_EXP_ROM_BAR_REG); + } else { + data = advk_readl(pcie, offset & ~3); + data = pci_conv_size_to_32(data, value, offset, size); + advk_writel(pcie, data, offset & ~3); + } + + if (offset == PCI_PRIMARY_BUS) + pcie->first_busno = data & 0xff; + + if (offset == PCI_SECONDARY_BUS || + (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) + pcie->sec_busno = (data >> 8) & 0xff; + + return 0; + } + if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, "Previous PIO read/write transfer is still running\n"); @@ -514,14 +595,14 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, /* Program the control register */ reg = advk_readl(pcie, PIO_CTRL); reg &= ~PIO_CTRL_TYPE_MASK; - if (PCI_BUS(bdf) == pcie->first_busno) + if (busno == pcie->sec_busno) reg |= PCIE_CONFIG_WR_TYPE0; else reg |= PCIE_CONFIG_WR_TYPE1; advk_writel(pcie, reg, PIO_CTRL); /* Program the address registers */ - reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset); + reg = PCIE_BDF(busno, PCI_DEV(bdf), PCI_FUNC(bdf)) | PCIE_CONF_REG(offset); advk_writel(pcie, reg, PIO_ADDR_LS); advk_writel(pcie, 0, PIO_ADDR_MS); dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg); @@ -590,14 +671,14 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie) /* check if the link is up or not */ for (retries = 0; retries < LINK_MAX_RETRIES; retries++) { if (pcie_advk_link_up(pcie)) { - printf("PCIE-%d: Link up\n", pcie->first_busno); + printf("PCIe: Link up\n"); return 0; } udelay(LINK_WAIT_TIMEOUT); } - printf("PCIE-%d: Link down\n", pcie->first_busno); + printf("PCIe: Link down\n"); return -ETIMEDOUT; } @@ -716,6 +797,25 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) */ advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); + /* + * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), + * because default value is Mass Storage Controller (0x010400), causing + * U-Boot to fail to recognize it as P2P Bridge. + * + * Note that this Aardvark PCI Bridge does not have a compliant Type 1 + * Configuration Space and it even cannot be accessed via Aardvark's + * PCI config space access method. Something like config space is + * available in internal Aardvark registers starting at offset 0x0 + * and is reported as Type 0. In range 0x10 - 0x34 it has totally + * different registers. So our driver reports Header Type as Type 1 and + * for the above mentioned range redirects access to the virtual + * cfgcache[] buffer, which avoids changing internal Aardvark registers. + */ + reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); + reg &= ~0xffffff00; + reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | @@ -857,9 +957,14 @@ static int pcie_advk_probe(struct udevice *dev) dev_warn(dev, "PCIE Reset on GPIO support is missing\n"); } - pcie->first_busno = dev_seq(dev); pcie->dev = pci_get_controller(dev); + /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */ + pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] = + PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8); + pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = + PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); + return pcie_advk_setup_hw(pcie); } From 95e101e86ae9d4dbc29ab82bcf1cfa8820a7ba4a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 26 Sep 2021 00:54:43 +0200 Subject: [PATCH 057/228] arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that PCI Bridge is working for the PCIe Root Port, U-Boot's PCI_PNP code automatically enables memory access and bus mastering when needed. We do not need to enable it when setting the HW up. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 082fdc3b74..2481cbea52 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -910,12 +910,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) if (pcie_advk_wait_for_link(pcie)) return -ENXIO; - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); - reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | - PCIE_CORE_CMD_IO_ACCESS_EN | - PCIE_CORE_CMD_MEM_IO_REQ_EN; - advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); - return 0; } From 1d7ad68559e2238d42730c7de0a3d5e159d72cdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 26 Sep 2021 00:54:44 +0200 Subject: [PATCH 058/228] arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 26 ++++++++++++++++++++++---- include/pci.h | 4 ++++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 2481cbea52..591bc8b48c 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -41,6 +41,7 @@ #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) #define PCIE_CORE_DEV_REV_REG 0x8 #define PCIE_CORE_EXP_ROM_BAR_REG 0x30 +#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) @@ -201,6 +202,7 @@ struct pcie_advk { struct udevice *dev; struct gpio_desc reset_gpio; u32 cfgcache[0x34 - 0x10]; + bool cfgcrssve; }; static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) @@ -413,6 +415,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, data |= PCI_HEADER_TYPE_BRIDGE << 16; } + if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) { + /* CRSSVE bit is stored only in cache */ + if (pcie->cfgcrssve) + data |= PCI_EXP_RTCTL_CRSSVE; + } + + if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + + (PCI_EXP_RTCAP & ~3)) { + /* CRS is emulated below, so set CRSVIS capability */ + data |= PCI_EXP_RTCAP_CRSVIS << 16; + } + *valuep = pci_conv_32_to_size(data, offset, size); return 0; @@ -423,13 +437,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and * only when CRSSVE bit in Root Port PCIe device is enabled. In all * other error PCIe Root Complex must return all-ones. - * Aardvark HW does not have Root Port PCIe device and U-Boot does not - * implement emulation of this device. + * * U-Boot currently does not support handling of CRS return value for * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. - * Therefore disable returning CRS response for now. + * So it means that pcie->cfgcrssve is false. But the code is prepared + * for returning CRS, so that if U-Boot does support CRS in the future, + * it will work for Aardvark. */ - allow_crs = false; + allow_crs = pcie->cfgcrssve; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, @@ -583,6 +598,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) pcie->sec_busno = (data >> 8) & 0xff; + if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) + pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE; + return 0; } diff --git a/include/pci.h b/include/pci.h index 11009a2f78..797f224e2f 100644 --- a/include/pci.h +++ b/include/pci.h @@ -495,6 +495,10 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_RTCTL 28 /* Root Control */ +#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ +#define PCI_EXP_RTCAP 30 /* Root Capabilities */ +#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ From 96a3c989dc936d51bfd825fa4396a12600dacaa4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 26 Sep 2021 00:54:45 +0200 Subject: [PATCH 059/228] arm: a37xx: pci: Cosmetic change MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update indentation in driver's private structure. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 591bc8b48c..3f714cd564 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -196,13 +196,13 @@ * @device: The pointer to PCI uclass device. */ struct pcie_advk { - void *base; - int first_busno; - int sec_busno; - struct udevice *dev; - struct gpio_desc reset_gpio; - u32 cfgcache[0x34 - 0x10]; - bool cfgcrssve; + void *base; + int first_busno; + int sec_busno; + struct udevice *dev; + struct gpio_desc reset_gpio; + u32 cfgcache[0x34 - 0x10]; + bool cfgcrssve; }; static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) From 8247c90e92377afbc4c6366848e56ff8c9295ffc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 26 Sep 2021 00:54:46 +0200 Subject: [PATCH 060/228] arm: a37xx: pci: Update private structure documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There were several changes for this structure but the documentation was not changed at the time. Fix this. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 3f714cd564..38eff495ab 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -186,14 +186,15 @@ /** * struct pcie_advk - Advk PCIe controller state * - * @reg_base: The base address of the register space. - * @first_busno: This driver supports multiple PCIe controllers. - * first_busno stores the bus number of the PCIe root-port - * number which may vary depending on the PCIe setup - * (PEX switches etc). - * @sec_busno: sec_busno stores the bus number for the device behind - * the PCIe root-port - * @device: The pointer to PCI uclass device. + * @base: The base address of the register space. + * @first_busno: Bus number of the PCIe root-port. + * This may vary depending on the PCIe setup. + * @sec_busno: Bus number for the device behind the PCIe root-port. + * @dev: The pointer to PCI uclass device. + * @reset_gpio: GPIO descriptor for PERST. + * @cfgcache: Buffer for emulation of PCIe Root Port's PCI Bridge registers + * that are not available on Aardvark. + * @cfgcrssve: For CRSSVE emulation. */ struct pcie_advk { void *base; From cf47a8cf8f7e53018bff9952183b7cbf45b07c30 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 3 Oct 2021 11:53:45 +0200 Subject: [PATCH 061/228] arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig, as this was removed from mach/config.h in a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig"). Signed-off-by: Stefan Roese Fixes: a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig") Cc: Tom Rini Cc: Marek Behún Cc: Pali Rohár Tested-by: Pali Rohár --- arch/arm/mach-mvebu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 087643725e..54dff9986b 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -11,6 +11,7 @@ config ARMADA_32BIT select SPL_DM if SPL select SPL_DM_SEQ_ALIAS if SPL select SPL_OF_CONTROL if SPL + select SPL_SKIP_LOWLEVEL_INIT select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL select TRANSLATION_OFFSET From cfb7102d8d901e9bdc7a6c109b341de7ae84256d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 4 Oct 2021 15:12:53 +0200 Subject: [PATCH 062/228] arm: mvebu: dts: m801: correct CP1 pinctrl Current CP1 pinctrl that is set on the Puzzle M801 is incorrect. CP1 pins are only used for the SMI bus and the MSS I2C, all other pins are just GPIO-s. Due to this being set completely wrong, the pinctrl was actually ended up being hardcoded in the board_early_init_f() step so that SMI would work. That is obviously not the right thing to do, so convert the register hex values that were being written to individual pin modes and set it in the DTS. Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does not get probed without an consumer. Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support") Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- arch/arm/dts/armada-8040-puzzle-m801.dts | 36 ++++++++++-------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 510fb84d5a..9e714c33e9 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -243,6 +243,9 @@ &cp1_mdio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_smi_pins>; + cp1_ge_phy0: ethernet-phy@3 { reg = <1>; }; @@ -292,33 +295,24 @@ /* * MPP Bus: * [0-5] TDM - * [6,7] CP1_UART 0 - * [8] CP1 10G SFP LOS - * [9] CP1 10G PHY RESET - * [10] CP1 10G SFP TX Disable - * [11] CP1 10G SFP Mode - * [12] SPI1 CS1n - * [13] SPI1 MISO (TDM and SPI ROM shared) - * [14] SPI1 CS0n - * [15] SPI1 MOSI (TDM and SPI ROM shared) - * [16] SPI1 CLK (TDM and SPI ROM shared) - * [24] CP1 2.5G SFP TX Disable - * [26] CP0 10G SFP TX Fault - * [27] CP0 10G SFP Mode - * [28] CP0 10G SFP LOS - * [29] CP0 10G SFP TX Disable - * [30] USB Over current indication - * [31] 10G Port 0 phy reset + * [27-28] SMI + * [29-30] CP1 MSS I2C + * [6-26, 31] GPIO * [32-62] = 0xff: Keep default CP1_shared_pins: */ /* 0 1 2 3 4 5 6 7 8 9 */ - pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 - 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff - 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 - 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 + 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + cp1_smi_pins: cp1-smi-pins { + marvell,pins = < 27 28 >; + marvell,function = <8>; + }; }; &ap_spi0 { From bdce2124aceca9857518220704069d97210ba939 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 4 Oct 2021 15:12:54 +0200 Subject: [PATCH 063/228] arm: mvebu: mvebu_armada-8k: drop Puzzle M801 early init code Since the CP1 pinctrl is not properly set in the DTS, there is no need for setting the pinctrl by writing hardcoded values to the MPP registers. So, drop the code relating to that. Fixes: 87c220d0 ("arm: mvebu: mvebu_armada-8k: Add support for initializing iEi Puzzle-M801 networking") Signed-off-by: Robert Marko Reviewed-by: Stefan Roese --- board/Marvell/mvebu_armada-8k/board.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c index 7da5d9f96b..77c7dd7ab0 100644 --- a/board/Marvell/mvebu_armada-8k/board.c +++ b/board/Marvell/mvebu_armada-8k/board.c @@ -35,17 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_IO_REG_CL ((1 << I2C_IO_REG_0_USB_H0_CL) | \ (1 << I2C_IO_REG_0_USB_H1_CL)) -/* - * Information specific to the iEi Puzzle-M801 board. - */ - -/* Internal configuration registers */ -#define CP1_CONF_REG_BASE 0xf4440000 -#define CONF_REG_MPP0 0x0 -#define CONF_REG_MPP1 0x4 -#define CONF_REG_MPP2 0x8 -#define CONF_REG_MPP3 0xC - static int usb_enabled = 0; /* Board specific xHCI dis-/enable code */ @@ -153,14 +142,7 @@ int board_xhci_enable(fdt_addr_t base) int board_early_init_f(void) { - /* Initialize some platform specific memory locations */ - if (of_machine_is_compatible("marvell,armada8040-puzzle-m801")) { - /* MPP setup */ - writel(0x00444444, CP1_CONF_REG_BASE + CONF_REG_MPP0); - writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP1); - writel(0x00000000, CP1_CONF_REG_BASE + CONF_REG_MPP2); - writel(0x08888000, CP1_CONF_REG_BASE + CONF_REG_MPP3); - } + /* Nothing to do yet */ return 0; } From 1ead6c20bd5fb8ea2f6afffb81dde91ea54bf54a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 7 Oct 2021 21:39:23 +1300 Subject: [PATCH 064/228] ARM: mvebu: x530: Remove custom kwbimage.cfg Commit ca1a4c863232 ("mvebu: select boot device at SoC level") made it unnecessary for the A385 boards to have their own kwbimage.cfg but as the x530 was in flight at the time it was added with it's own kwbimage.cfg. Remove the custom kwbimage.cfg as the SoC level file is suitable. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- board/alliedtelesis/x530/kwbimage.cfg | 12 ------------ 1 file changed, 12 deletions(-) delete mode 100644 board/alliedtelesis/x530/kwbimage.cfg diff --git a/board/alliedtelesis/x530/kwbimage.cfg b/board/alliedtelesis/x530/kwbimage.cfg deleted file mode 100644 index f58d388825..0000000000 --- a/board/alliedtelesis/x530/kwbimage.cfg +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2017 Allied Telesis Labs -# - -# Armada XP uses version 1 image format -VERSION 1 - -# Boot Media configurations -BOOT_FROM spi - -# Binary Header (bin_hdr) with DDR3 training code -BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 From 81b2445af4005cad6f1edef8b30ff1bb82ff8f80 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Aug 2021 11:16:40 +0200 Subject: [PATCH 065/228] spi: stm32: Add ofdata_to_platdata() callback Parse DT in ofdata_to_platdata() callback instead of probe(). Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- drivers/spi/stm32_spi.c | 224 +++++++++++++++++++++++----------------- 1 file changed, 132 insertions(+), 92 deletions(-) diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index bd8514033d..fe5419e851 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -97,11 +97,14 @@ #define SPI_SIMPLEX_RX 2 #define SPI_HALF_DUPLEX 3 -struct stm32_spi_priv { +struct stm32_spi_plat { void __iomem *base; struct clk clk; struct reset_ctl rst_ctl; struct gpio_desc cs_gpios[MAX_CS_COUNT]; +}; + +struct stm32_spi_priv { ulong bus_clk_rate; unsigned int fifo_size; unsigned int cur_bpw; @@ -115,28 +118,32 @@ struct stm32_spi_priv { bool cs_high; }; -static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv) +static void stm32_spi_write_txfifo(struct udevice *bus) { + struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; + while ((priv->tx_len > 0) && - (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) { + (readl(base + STM32_SPI_SR) & SPI_SR_TXP)) { u32 offs = priv->cur_xferlen - priv->tx_len; if (priv->tx_len >= sizeof(u32) && IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) { const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs); - writel(*tx_buf32, priv->base + STM32_SPI_TXDR); + writel(*tx_buf32, base + STM32_SPI_TXDR); priv->tx_len -= sizeof(u32); } else if (priv->tx_len >= sizeof(u16) && IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) { const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs); - writew(*tx_buf16, priv->base + STM32_SPI_TXDR); + writew(*tx_buf16, base + STM32_SPI_TXDR); priv->tx_len -= sizeof(u16); } else { const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs); - writeb(*tx_buf8, priv->base + STM32_SPI_TXDR); + writeb(*tx_buf8, base + STM32_SPI_TXDR); priv->tx_len -= sizeof(u8); } } @@ -144,9 +151,12 @@ static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv) log_debug("%d bytes left\n", priv->tx_len); } -static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) +static void stm32_spi_read_rxfifo(struct udevice *bus) { - u32 sr = readl(priv->base + STM32_SPI_SR); + struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; + u32 sr = readl(base + STM32_SPI_SR); u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; while ((priv->rx_len > 0) && @@ -158,7 +168,7 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) { u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs); - *rx_buf32 = readl(priv->base + STM32_SPI_RXDR); + *rx_buf32 = readl(base + STM32_SPI_RXDR); priv->rx_len -= sizeof(u32); } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) && (priv->rx_len >= sizeof(u16) || @@ -166,38 +176,38 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) (rxplvl >= 2 || priv->cur_bpw > 8)))) { u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs); - *rx_buf16 = readw(priv->base + STM32_SPI_RXDR); + *rx_buf16 = readw(base + STM32_SPI_RXDR); priv->rx_len -= sizeof(u16); } else { u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs); - *rx_buf8 = readb(priv->base + STM32_SPI_RXDR); + *rx_buf8 = readb(base + STM32_SPI_RXDR); priv->rx_len -= sizeof(u8); } - sr = readl(priv->base + STM32_SPI_SR); + sr = readl(base + STM32_SPI_SR); rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; } log_debug("%d bytes left\n", priv->rx_len); } -static int stm32_spi_enable(struct stm32_spi_priv *priv) +static int stm32_spi_enable(void __iomem *base) { log_debug("\n"); /* Enable the SPI hardware */ - setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); + setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE); return 0; } -static int stm32_spi_disable(struct stm32_spi_priv *priv) +static int stm32_spi_disable(void __iomem *base) { log_debug("\n"); /* Disable the SPI hardware */ - clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); + clrbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE); return 0; } @@ -205,45 +215,48 @@ static int stm32_spi_disable(struct stm32_spi_priv *priv) static int stm32_spi_claim_bus(struct udevice *slave) { struct udevice *bus = dev_get_parent(slave); - struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; dev_dbg(slave, "\n"); /* Enable the SPI hardware */ - return stm32_spi_enable(priv); + return stm32_spi_enable(base); } static int stm32_spi_release_bus(struct udevice *slave) { struct udevice *bus = dev_get_parent(slave); - struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; dev_dbg(slave, "\n"); /* Disable the SPI hardware */ - return stm32_spi_disable(priv); + return stm32_spi_disable(base); } static void stm32_spi_stopxfer(struct udevice *dev) { - struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; u32 cr1, sr; int ret; dev_dbg(dev, "\n"); - cr1 = readl(priv->base + STM32_SPI_CR1); + cr1 = readl(base + STM32_SPI_CR1); if (!(cr1 & SPI_CR1_SPE)) return; /* Wait on EOT or suspend the flow */ - ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr, + ret = readl_poll_timeout(base + STM32_SPI_SR, sr, !(sr & SPI_SR_EOT), 100000); if (ret < 0) { if (cr1 & SPI_CR1_CSTART) { - writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1); - if (readl_poll_timeout(priv->base + STM32_SPI_SR, + writel(cr1 | SPI_CR1_CSUSP, base + STM32_SPI_CR1); + if (readl_poll_timeout(base + STM32_SPI_SR, sr, !(sr & SPI_SR_SUSP), 100000) < 0) dev_err(dev, "Suspend request timeout\n"); @@ -251,11 +264,12 @@ static void stm32_spi_stopxfer(struct udevice *dev) } /* clear status flags */ - setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL); + setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL); } static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) { + struct stm32_spi_plat *plat = dev_get_plat(dev); struct stm32_spi_priv *priv = dev_get_priv(dev); dev_dbg(dev, "cs=%d enable=%d\n", cs, enable); @@ -263,18 +277,20 @@ static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) if (cs >= MAX_CS_COUNT) return -ENODEV; - if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) + if (!dm_gpio_is_valid(&plat->cs_gpios[cs])) return -EINVAL; if (priv->cs_high) enable = !enable; - return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0); + return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0); } static int stm32_spi_set_mode(struct udevice *bus, uint mode) { struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; u32 cfg2_clrb = 0, cfg2_setb = 0; dev_dbg(bus, "mode=%d\n", mode); @@ -295,7 +311,7 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode) cfg2_clrb |= SPI_CFG2_LSBFRST; if (cfg2_clrb || cfg2_setb) - clrsetbits_le32(priv->base + STM32_SPI_CFG2, + clrsetbits_le32(base + STM32_SPI_CFG2, cfg2_clrb, cfg2_setb); if (mode & SPI_CS_HIGH) @@ -308,6 +324,8 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode) static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) { struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; u32 fthlv, half_fifo; /* data packet should not exceed 1/2 of fifo space */ @@ -321,7 +339,7 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) if (!fthlv) fthlv = 1; - clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV, + clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_FTHLV, (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT); return 0; @@ -330,6 +348,8 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) static int stm32_spi_set_speed(struct udevice *bus, uint hz) { struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; u32 mbrdiv; long div; @@ -353,7 +373,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz) if (!mbrdiv) return -EINVAL; - clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR, + clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_MBR, (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT); priv->cur_hz = hz; @@ -367,6 +387,8 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, struct udevice *bus = dev_get_parent(slave); struct dm_spi_slave_plat *slave_plat; struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; u32 sr; u32 ifcr = 0; u32 xferlen; @@ -376,7 +398,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, xferlen = bitlen / 8; if (xferlen <= SPI_CR2_TSIZE) - writel(xferlen, priv->base + STM32_SPI_CR2); + writel(xferlen, base + STM32_SPI_CR2); else return -EMSGSIZE; @@ -396,15 +418,15 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, priv->cur_xferlen = xferlen; /* Disable the SPI hardware to unlock CFG1/CFG2 registers */ - stm32_spi_disable(priv); + stm32_spi_disable(base); - clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM, + clrsetbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_COMM, mode << SPI_CFG2_COMM_SHIFT); stm32_spi_set_fthlv(bus, xferlen); /* Enable the SPI hardware */ - stm32_spi_enable(priv); + stm32_spi_enable(base); } dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n", @@ -416,12 +438,12 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, /* Be sure to have data in fifo before starting data transfer */ if (priv->tx_buf) - stm32_spi_write_txfifo(priv); + stm32_spi_write_txfifo(bus); - setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART); + setbits_le32(base + STM32_SPI_CR1, SPI_CR1_CSTART); while (1) { - sr = readl(priv->base + STM32_SPI_SR); + sr = readl(base + STM32_SPI_SR); if (sr & SPI_SR_OVR) { dev_err(bus, "Overrun: RX data lost\n"); @@ -433,7 +455,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, dev_warn(bus, "System too slow is limiting data throughput\n"); if (priv->rx_buf && priv->rx_len > 0) - stm32_spi_read_rxfifo(priv); + stm32_spi_read_rxfifo(bus); ifcr |= SPI_SR_SUSP; } @@ -443,23 +465,23 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, if (sr & SPI_SR_TXP) if (priv->tx_buf && priv->tx_len > 0) - stm32_spi_write_txfifo(priv); + stm32_spi_write_txfifo(bus); if (sr & SPI_SR_RXP) if (priv->rx_buf && priv->rx_len > 0) - stm32_spi_read_rxfifo(priv); + stm32_spi_read_rxfifo(bus); if (sr & SPI_SR_EOT) { if (priv->rx_buf && priv->rx_len > 0) - stm32_spi_read_rxfifo(priv); + stm32_spi_read_rxfifo(bus); break; } - writel(ifcr, priv->base + STM32_SPI_IFCR); + writel(ifcr, base + STM32_SPI_IFCR); } /* clear status flags */ - setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL); + setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL); stm32_spi_stopxfer(bus); if (flags & SPI_XFER_END) @@ -470,42 +492,72 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, static int stm32_spi_get_fifo_size(struct udevice *dev) { - struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; u32 count = 0; - stm32_spi_enable(priv); + stm32_spi_enable(base); - while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP) - writeb(++count, priv->base + STM32_SPI_TXDR); + while (readl(base + STM32_SPI_SR) & SPI_SR_TXP) + writeb(++count, base + STM32_SPI_TXDR); - stm32_spi_disable(priv); + stm32_spi_disable(base); dev_dbg(dev, "%d x 8-bit fifo size\n", count); return count; } +static int stm32_spi_of_to_plat(struct udevice *dev) +{ + struct stm32_spi_plat *plat = dev_get_plat(dev); + int ret; + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get registers base address\n"); + return -ENOENT; + } + + ret = clk_get_by_index(dev, 0, &plat->clk); + if (ret < 0) + return ret; + + ret = reset_get_by_index(dev, 0, &plat->rst_ctl); + if (ret < 0) + goto clk_err; + + ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios, + ARRAY_SIZE(plat->cs_gpios), 0); + if (ret < 0) { + dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret); + ret = -ENOENT; + goto clk_err; + } + + return 0; + +clk_err: + clk_free(&plat->clk); + + return ret; +} + static int stm32_spi_probe(struct udevice *dev) { + struct stm32_spi_plat *plat = dev_get_plat(dev); struct stm32_spi_priv *priv = dev_get_priv(dev); + void __iomem *base = plat->base; unsigned long clk_rate; int ret; unsigned int i; - priv->base = dev_remap_addr(dev); - if (!priv->base) - return -EINVAL; - /* enable clock */ - ret = clk_get_by_index(dev, 0, &priv->clk); + ret = clk_enable(&plat->clk); if (ret < 0) return ret; - ret = clk_enable(&priv->clk); - if (ret < 0) - return ret; - - clk_rate = clk_get_rate(&priv->clk); + clk_rate = clk_get_rate(&plat->clk); if (!clk_rate) { ret = -EINVAL; goto clk_err; @@ -514,46 +566,34 @@ static int stm32_spi_probe(struct udevice *dev) priv->bus_clk_rate = clk_rate; /* perform reset */ - ret = reset_get_by_index(dev, 0, &priv->rst_ctl); - if (ret < 0) - goto clk_err; - - reset_assert(&priv->rst_ctl); + reset_assert(&plat->rst_ctl); udelay(2); - reset_deassert(&priv->rst_ctl); - - ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios, - ARRAY_SIZE(priv->cs_gpios), 0); - if (ret < 0) { - dev_err(dev, "Can't get cs gpios: %d", ret); - goto reset_err; - } + reset_deassert(&plat->rst_ctl); priv->fifo_size = stm32_spi_get_fifo_size(dev); - priv->cur_mode = SPI_FULL_DUPLEX; priv->cur_xferlen = 0; priv->cur_bpw = SPI_DEFAULT_WORDLEN; - clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE, + clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE, priv->cur_bpw - 1); - for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) { - if (!dm_gpio_is_valid(&priv->cs_gpios[i])) + for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) { + if (!dm_gpio_is_valid(&plat->cs_gpios[i])) continue; - dm_gpio_set_dir_flags(&priv->cs_gpios[i], + dm_gpio_set_dir_flags(&plat->cs_gpios[i], GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); } /* Ensure I2SMOD bit is kept cleared */ - clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); + clrbits_le32(base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); /* * - SS input value high * - transmitter half duplex direction * - automatic communication suspend when RX-Fifo is full */ - setbits_le32(priv->base + STM32_SPI_CR1, + setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); /* @@ -562,40 +602,38 @@ static int stm32_spi_probe(struct udevice *dev) * SS input value is determined by the SSI bit * - keep control of all associated GPIOs */ - setbits_le32(priv->base + STM32_SPI_CFG2, + setbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR); return 0; -reset_err: - reset_free(&priv->rst_ctl); - clk_err: - clk_disable(&priv->clk); - clk_free(&priv->clk); + clk_disable(&plat->clk); + clk_free(&plat->clk); return ret; }; static int stm32_spi_remove(struct udevice *dev) { - struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; int ret; stm32_spi_stopxfer(dev); - stm32_spi_disable(priv); + stm32_spi_disable(base); - ret = reset_assert(&priv->rst_ctl); + ret = reset_assert(&plat->rst_ctl); if (ret < 0) return ret; - reset_free(&priv->rst_ctl); + reset_free(&plat->rst_ctl); - ret = clk_disable(&priv->clk); + ret = clk_disable(&plat->clk); if (ret < 0) return ret; - clk_free(&priv->clk); + clk_free(&plat->clk); return ret; }; @@ -618,7 +656,9 @@ U_BOOT_DRIVER(stm32_spi) = { .id = UCLASS_SPI, .of_match = stm32_spi_ids, .ops = &stm32_spi_ops, - .priv_auto = sizeof(struct stm32_spi_priv), + .of_to_plat = stm32_spi_of_to_plat, + .plat_auto = sizeof(struct stm32_spi_plat), + .priv_auto = sizeof(struct stm32_spi_priv), .probe = stm32_spi_probe, .remove = stm32_spi_remove, }; From 1fd9eb68d64845bf3db41cba6519741872fadd8e Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 3 Aug 2021 12:05:09 +0200 Subject: [PATCH 066/228] i2c: stm32f7: move driver data of each instance in a privdata Today all the I2C instance point on the same global variable stm32_i2c_setup according the compatible: i2c_priv->setup = pointer to the same driver data. This patch changes this driver data (stm32f7_setup and stm32mp15_setup) to a const struct and move the timing struct 'setup' as element of i2c privdata, initialized in stm32_ofdata_to_platdata() with the driver configuration data. This patch solves issues when several I2C instance have not the same clock source or not the same configuration: each timing setup is saved is the I2C privdata. Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- drivers/i2c/stm32f7_i2c.c | 53 ++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 26 deletions(-) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 7b04a09de0..b449084b5f 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -158,7 +158,6 @@ struct stm32_i2c_spec { * @fall_time: Fall time (ns) * @dnf: Digital filter coefficient (0-16) * @analog_filter: Analog filter delay (On/Off) - * @fmp_clr_offset: Fast Mode Plus clear register offset from set register */ struct stm32_i2c_setup { u32 speed_freq; @@ -167,6 +166,13 @@ struct stm32_i2c_setup { u32 fall_time; u8 dnf; bool analog_filter; +}; + +/** + * struct stm32_i2c_data - driver data for I2C configuration by compatible + * @fmp_clr_offset: Fast Mode Plus clear register offset from set register + */ +struct stm32_i2c_data { u32 fmp_clr_offset; }; @@ -201,7 +207,7 @@ struct stm32_i2c_timings { struct stm32_i2c_priv { struct stm32_i2c_regs *regs; struct clk clk; - struct stm32_i2c_setup *setup; + struct stm32_i2c_setup setup; u32 speed; struct regmap *regmap; u32 regmap_sreg; @@ -251,18 +257,11 @@ static const struct stm32_i2c_spec i2c_specs[] = { }, }; -static const struct stm32_i2c_setup stm32f7_setup = { - .rise_time = STM32_I2C_RISE_TIME_DEFAULT, - .fall_time = STM32_I2C_FALL_TIME_DEFAULT, - .dnf = STM32_I2C_DNF_DEFAULT, - .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, +static const struct stm32_i2c_data stm32f7_data = { + .fmp_clr_offset = 0x00, }; -static const struct stm32_i2c_setup stm32mp15_setup = { - .rise_time = STM32_I2C_RISE_TIME_DEFAULT, - .fall_time = STM32_I2C_FALL_TIME_DEFAULT, - .dnf = STM32_I2C_DNF_DEFAULT, - .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, +static const struct stm32_i2c_data stm32mp15_data = { .fmp_clr_offset = 0x40, }; @@ -745,7 +744,7 @@ static u32 get_lower_rate(u32 rate) static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, struct stm32_i2c_timings *timing) { - struct stm32_i2c_setup *setup = i2c_priv->setup; + struct stm32_i2c_setup *setup = &i2c_priv->setup; int ret = 0; setup->speed_freq = i2c_priv->speed; @@ -839,10 +838,11 @@ static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) writel(timing, ®s->timingr); /* Enable I2C */ - if (i2c_priv->setup->analog_filter) + if (i2c_priv->setup.analog_filter) clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); else setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); + setbits_le32(®s->cr1, STM32_I2C_CR1_PE); return 0; @@ -903,21 +903,23 @@ clk_free: static int stm32_of_to_plat(struct udevice *dev) { + const struct stm32_i2c_data *data; struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); u32 rise_time, fall_time; int ret; - i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); - if (!i2c_priv->setup) + data = (const struct stm32_i2c_data *)dev_get_driver_data(dev); + if (!data) return -EINVAL; - rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0); - if (rise_time) - i2c_priv->setup->rise_time = rise_time; + rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", + STM32_I2C_RISE_TIME_DEFAULT); - fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0); - if (fall_time) - i2c_priv->setup->fall_time = fall_time; + fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", + STM32_I2C_FALL_TIME_DEFAULT); + + i2c_priv->setup.dnf = STM32_I2C_DNF_DEFAULT; + i2c_priv->setup.analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE; /* Optional */ i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev, @@ -930,8 +932,7 @@ static int stm32_of_to_plat(struct udevice *dev) return ret; i2c_priv->regmap_sreg = fmp[1]; - i2c_priv->regmap_creg = fmp[1] + - i2c_priv->setup->fmp_clr_offset; + i2c_priv->regmap_creg = fmp[1] + data->fmp_clr_offset; i2c_priv->regmap_mask = fmp[2]; } @@ -944,8 +945,8 @@ static const struct dm_i2c_ops stm32_i2c_ops = { }; static const struct udevice_id stm32_i2c_of_match[] = { - { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, - { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_setup }, + { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, + { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data }, {} }; From 5d59bd553ba9ef73b93b50e7c1934cbb1613c104 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Aug 2021 12:05:10 +0200 Subject: [PATCH 067/228] arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32f746 Add i2c-analog-filter property in I2C nodes to enable analog filter feature. Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32f746.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index ba9b3cd03c..78facde2b5 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -313,6 +313,7 @@ clocks = <&rcc 1 CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -325,6 +326,7 @@ clocks = <&rcc 1 CLK_I2C2>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -337,6 +339,7 @@ clocks = <&rcc 1 CLK_I2C3>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; @@ -349,6 +352,7 @@ clocks = <&rcc 1 CLK_I2C4>; #address-cells = <1>; #size-cells = <0>; + i2c-analog-filter; status = "disabled"; }; From 2aaac1787a6a13e087bb75254d6430a4e1c947bf Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Aug 2021 12:05:11 +0200 Subject: [PATCH 068/228] arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32h743 Add i2c-analog-filter property in I2C nodes to enable analog filter feature. Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32h743.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index ed6857512f..dbfebf07f2 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -124,6 +124,7 @@ <32>; resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; clocks = <&rcc I2C1_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -136,6 +137,7 @@ <34>; resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; clocks = <&rcc I2C2_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -148,6 +150,7 @@ <73>; resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; clocks = <&rcc I2C3_CK>; + i2c-analog-filter; status = "disabled"; }; @@ -395,6 +398,7 @@ <96>; resets = <&rcc STM32H7_APB4_RESET(I2C4)>; clocks = <&rcc I2C4_CK>; + i2c-analog-filter; status = "disabled"; }; From 09599998919c6eab26c3dfd0fcd2f8a6a07cf75d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 3 Aug 2021 12:05:12 +0200 Subject: [PATCH 069/228] i2c: stm32f7: support DT binding i2c-analog-filter Replace driver internally coded enabling/disabling of the analog-filter with the DT binding "i2c-analog-filter". Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- drivers/i2c/stm32f7_i2c.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index b449084b5f..e71a0e0aa3 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -108,7 +108,6 @@ struct stm32_i2c_regs { #define STM32_I2C_DNF_DEFAULT 0 #define STM32_I2C_DNF_MAX 16 -#define STM32_I2C_ANALOG_FILTER_ENABLE 1 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ @@ -919,7 +918,7 @@ static int stm32_of_to_plat(struct udevice *dev) STM32_I2C_FALL_TIME_DEFAULT); i2c_priv->setup.dnf = STM32_I2C_DNF_DEFAULT; - i2c_priv->setup.analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE; + i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter"); /* Optional */ i2c_priv->regmap = syscon_regmap_lookup_by_phandle(dev, From 6bbb14f018d4e7f958bcdc04b92be412601c44f6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 3 Aug 2021 12:05:13 +0200 Subject: [PATCH 070/228] i2c: stm32f7: fix configuration of the digital filter The digital filter related computation are present in the driver however the programming of the filter within the IP is missing. The maximum value for the DNF is wrong and should be 15 instead of 16. Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- drivers/i2c/stm32f7_i2c.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index e71a0e0aa3..7e6c65fadc 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -45,6 +45,8 @@ struct stm32_i2c_regs { /* STM32 I2C control 1 */ #define STM32_I2C_CR1_ANFOFF BIT(12) +#define STM32_I2C_CR1_DNF_MASK GENMASK(11, 8) +#define STM32_I2C_CR1_DNF(n) (((n) & 0xf) << 8) #define STM32_I2C_CR1_ERRIE BIT(7) #define STM32_I2C_CR1_TCIE BIT(6) #define STM32_I2C_CR1_STOPIE BIT(5) @@ -106,7 +108,7 @@ struct stm32_i2c_regs { #define STM32_I2C_MAX_LEN 0xff #define STM32_I2C_DNF_DEFAULT 0 -#define STM32_I2C_DNF_MAX 16 +#define STM32_I2C_DNF_MAX 15 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ @@ -155,7 +157,7 @@ struct stm32_i2c_spec { * @clock_src: I2C clock source frequency (Hz) * @rise_time: Rise time (ns) * @fall_time: Fall time (ns) - * @dnf: Digital filter coefficient (0-16) + * @dnf: value of digital filter to apply * @analog_filter: Analog filter delay (On/Off) */ struct stm32_i2c_setup { @@ -842,6 +844,10 @@ static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) else setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); + /* Program the Digital Filter */ + clrsetbits_le32(®s->cr1, STM32_I2C_CR1_DNF_MASK, + STM32_I2C_CR1_DNF(i2c_priv->setup.dnf)); + setbits_le32(®s->cr1, STM32_I2C_CR1_PE); return 0; From 6338b458887021dbea718d7bee973569a2e62bf5 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 3 Aug 2021 12:05:14 +0200 Subject: [PATCH 071/228] i2c: stm32f7: add support for DNF i2c-digital-filter binding Add the support for the i2c-digital-filter binding, allowing to enable the digital filter via the device-tree and indicate its value in the DT Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- drivers/i2c/stm32f7_i2c.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 7e6c65fadc..2b2dae67a3 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -107,7 +107,6 @@ struct stm32_i2c_regs { #define STM32_I2C_MAX_LEN 0xff -#define STM32_I2C_DNF_DEFAULT 0 #define STM32_I2C_DNF_MAX 15 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ @@ -204,6 +203,7 @@ struct stm32_i2c_timings { * @regmap_sreg: register address for setting Fast Mode Plus bits * @regmap_creg: register address for clearing Fast Mode Plus bits * @regmap_mask: mask for Fast Mode Plus bits + * @dnf_dt: value of digital filter requested via dt */ struct stm32_i2c_priv { struct stm32_i2c_regs *regs; @@ -214,6 +214,7 @@ struct stm32_i2c_priv { u32 regmap_sreg; u32 regmap_creg; u32 regmap_mask; + u32 dnf_dt; }; static const struct stm32_i2c_spec i2c_specs[] = { @@ -684,6 +685,7 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, const struct stm32_i2c_spec *specs; struct stm32_i2c_timings *v, *_v; struct list_head solutions; + u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src); int ret; specs = get_specs(setup->speed_freq); @@ -701,6 +703,8 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, return -EINVAL; } + /* Analog and Digital Filters */ + setup->dnf = DIV_ROUND_CLOSEST(i2c_priv->dnf_dt, i2cclk); if (setup->dnf > STM32_I2C_DNF_MAX) { log_err("DNF out of bound %d/%d\n", setup->dnf, STM32_I2C_DNF_MAX); @@ -923,7 +927,10 @@ static int stm32_of_to_plat(struct udevice *dev) fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", STM32_I2C_FALL_TIME_DEFAULT); - i2c_priv->setup.dnf = STM32_I2C_DNF_DEFAULT; + i2c_priv->dnf_dt = dev_read_u32_default(dev, "i2c-digital-filter-width-ns", 0); + if (!dev_read_bool(dev, "i2c-digital-filter")) + i2c_priv->dnf_dt = 0; + i2c_priv->setup.analog_filter = dev_read_bool(dev, "i2c-analog-filter"); /* Optional */ From c31cf40096f9187d2f11e4ed4a102b9dd3ac98c2 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 3 Aug 2021 12:05:15 +0200 Subject: [PATCH 072/228] i2c: stm32f7: compute i2cclk only one time Compute i2cclk only one time in stm32_i2c_compute_timing() and remove setup parameter (accessible in i2c_priv). Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Reviewed-by: Patrice Chotard --- drivers/i2c/stm32f7_i2c.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 2b2dae67a3..c6ae65badb 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -507,14 +507,13 @@ static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, return 0; } -static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, +static int stm32_i2c_compute_solutions(u32 i2cclk, + struct stm32_i2c_setup *setup, const struct stm32_i2c_spec *specs, struct list_head *solutions) { struct stm32_i2c_timings *v; u32 p_prev = STM32_PRESC_MAX; - u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, - setup->clock_src); u32 af_delay_min, af_delay_max; u16 p, l, a; int sdadel_min, sdadel_max, scldel_min; @@ -582,7 +581,8 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, return ret; } -static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, +static int stm32_i2c_choose_solution(u32 i2cclk, + struct stm32_i2c_setup *setup, const struct stm32_i2c_spec *specs, struct list_head *solutions, struct stm32_i2c_timings *s) @@ -591,8 +591,6 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->speed_freq); u32 clk_error_prev = i2cbus; - u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, - setup->clock_src); u32 clk_min, clk_max; u32 af_delay_min; u32 dnf_delay; @@ -679,9 +677,9 @@ static const struct stm32_i2c_spec *get_specs(u32 rate) } static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, - struct stm32_i2c_setup *setup, struct stm32_i2c_timings *output) { + struct stm32_i2c_setup *setup = &i2c_priv->setup; const struct stm32_i2c_spec *specs; struct stm32_i2c_timings *v, *_v; struct list_head solutions; @@ -712,11 +710,11 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, } INIT_LIST_HEAD(&solutions); - ret = stm32_i2c_compute_solutions(setup, specs, &solutions); + ret = stm32_i2c_compute_solutions(i2cclk, setup, specs, &solutions); if (ret) goto exit; - ret = stm32_i2c_choose_solution(setup, specs, &solutions, output); + ret = stm32_i2c_choose_solution(i2cclk, setup, specs, &solutions, output); if (ret) goto exit; @@ -761,7 +759,7 @@ static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, } do { - ret = stm32_i2c_compute_timing(i2c_priv, setup, timing); + ret = stm32_i2c_compute_timing(i2c_priv, timing); if (ret) { log_debug("failed to compute I2C timings.\n"); if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) { From d901d76eca773ebbbdbbfc54ba0b40912a909cf0 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 1 Sep 2021 11:51:42 +0200 Subject: [PATCH 073/228] board: stm32mp1: Remove gpio_hog_probe_all() from board DM_GPIO_HOG flag has been replaced by GPIO_HOG flag since a while in commit 49b10cb49262 ("gpio: fixes for gpio-hog support"). And furthermore, gpio_hog_probe_all() is already called in board_r.c. So gpio_hog_probe() can be removed from stm32mp1.c. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- board/st/stm32mp1/stm32mp1.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 1bceb41494..28485e6123 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -646,9 +646,6 @@ static void board_ev1_init(void) /* board dependent setup after realloc */ int board_init(void) { - if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) - gpio_hog_probe_all(); - board_key_check(); if (board_is_ev1()) From 089e433e560f883b23c53b66ce3f8fb5a81bd431 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 1 Sep 2021 11:51:43 +0200 Subject: [PATCH 074/228] board: dh_stm32mp1: Remove gpio_hog_probe_all() from board DM_GPIO_HOG flag has been replaced by GPIO_HOG flag since a while in commit 49b10cb49262 ("gpio: fixes for gpio-hog support"). And furthermore, gpio_hog_probe_all() is already called in board_r.c. So gpio_hog_probe() can be removed from stm32mp1.c. Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Patrick Delaunay --- board/dhelectronics/dh_stm32mp1/board.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 765b54a4a4..957208cf5a 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -590,9 +590,6 @@ static void board_init_fmc2(void) /* board dependent setup after realloc */ int board_init(void) { - if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) - gpio_hog_probe_all(); - board_key_check(); #ifdef CONFIG_DM_REGULATOR From 930c887e0fb88dcf1907f268960330c17999b5a3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:06 -0600 Subject: [PATCH 075/228] lib: Add memdup() Add a function to duplicate a memory region, a little like strdup(). Signed-off-by: Simon Glass --- include/linux/string.h | 13 +++++++++++++ lib/string.c | 13 +++++++++++++ test/lib/string.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/include/linux/string.h b/include/linux/string.h index dd255f2163..3169c93796 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -129,6 +129,19 @@ extern void * memchr(const void *,int,__kernel_size_t); void *memchr_inv(const void *, int, size_t); #endif +/** + * memdup() - allocate a buffer and copy in the contents + * + * Note that this returns a valid pointer even if @len is 0 + * + * @src: data to copy in + * @len: number of bytes to copy + * @return allocated buffer with the copied contents, or NULL if not enough + * memory is available + * + */ +char *memdup(const void *src, size_t len); + unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); diff --git a/lib/string.c b/lib/string.c index ba176fb08f..78bd65c413 100644 --- a/lib/string.c +++ b/lib/string.c @@ -659,6 +659,19 @@ void * memscan(void * addr, int c, size_t size) } #endif +char *memdup(const void *src, size_t len) +{ + char *p; + + p = malloc(len); + if (!p) + return NULL; + + memcpy(p, src, len); + + return p; +} + #ifndef __HAVE_ARCH_STRSTR /** * strstr - Find the first substring in a %NUL terminated string diff --git a/test/lib/string.c b/test/lib/string.c index 64234bef36..5dcf4d6db0 100644 --- a/test/lib/string.c +++ b/test/lib/string.c @@ -23,6 +23,8 @@ /* Allow for copying up to 32 bytes */ #define BUFLEN (SWEEP + 33) +#define TEST_STR "hello" + /** * init_buffer() - initialize buffer * @@ -193,3 +195,33 @@ static int lib_memmove(struct unit_test_state *uts) } LIB_TEST(lib_memmove, 0); + +/** lib_memdup() - unit test for memdup() */ +static int lib_memdup(struct unit_test_state *uts) +{ + char buf[BUFLEN]; + size_t len; + char *p, *q; + + /* Zero size should do nothing */ + p = memdup(NULL, 0); + ut_assertnonnull(p); + free(p); + + p = memdup(buf, 0); + ut_assertnonnull(p); + free(p); + + strcpy(buf, TEST_STR); + len = sizeof(TEST_STR); + p = memdup(buf, len); + ut_asserteq_mem(p, buf, len); + + q = memdup(p, len); + ut_asserteq_mem(q, buf, len); + free(q); + free(p); + + return 0; +} +LIB_TEST(lib_memdup, 0); From 67bc59df05331eaac56cd0a00219d1386130aee2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:07 -0600 Subject: [PATCH 076/228] Add support for an owned buffer When passing a data buffer back from a function, it is not always clear who owns the buffer, i.e. who is responsible for freeing the memory used. An example of this is where multiple files are decompressed from the firmware image, using a temporary buffer for reading (since the compressed data has to live somewhere) and producing a temporary or permanent buffer with the resuilts. Where the firmware image can be memory-mapped, as on x86, the compressed data does not need to be buffered, but the complexity of having a buffer which is either allocated or not, makes the code hard to understand. Introduce a new 'abuf' which supports simple buffer operations: - encapsulating a buffer and its size - either allocated with malloc() or not - able to be reliably freed if necessary - able to be converted to an allocated buffer if needed This simple API makes it easier to deal with allocated and memory-mapped buffers. Signed-off-by: Simon Glass --- include/abuf.h | 159 +++++++++++++++++++++ lib/Makefile | 1 + lib/abuf.c | 109 +++++++++++++++ test/lib/Makefile | 1 + test/lib/abuf.c | 344 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 614 insertions(+) create mode 100644 include/abuf.h create mode 100644 lib/abuf.c create mode 100644 test/lib/abuf.c diff --git a/include/abuf.h b/include/abuf.h new file mode 100644 index 0000000000..d230f72806 --- /dev/null +++ b/include/abuf.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Handles a buffer that can be allocated and freed + * + * Copyright 2021 Google LLC + * Written by Simon Glass + */ + +#ifndef __ABUF_H +#define __ABUF_H + +#include + +/** + * struct abuf - buffer that can be allocated and freed + * + * This is useful for a block of data which may be allocated with malloc(), or + * not, so that it needs to be freed correctly when finished with. + * + * For now it has a very simple purpose. + * + * Using memset() to zero all fields is guaranteed to be equivalent to + * abuf_init(). + * + * @data: Pointer to data + * @size: Size of data in bytes + * @alloced: true if allocated with malloc(), so must be freed after use + */ +struct abuf { + void *data; + size_t size; + bool alloced; +}; + +static inline void *abuf_data(const struct abuf *abuf) +{ + return abuf->data; +} + +static inline size_t abuf_size(const struct abuf *abuf) +{ + return abuf->size; +} + +/** + * abuf_set() - set the (unallocated) data in a buffer + * + * This simply makes the abuf point to the supplied data, which must be live + * for the lifetime of the abuf. It is not alloced. + * + * Any existing data in the abuf is freed and the alloced member is set to + * false. + * + * @abuf: abuf to adjust + * @data: New contents of abuf + * @size: New size of abuf + */ +void abuf_set(struct abuf *abuf, void *data, size_t size); + +/** + * abuf_map_sysmem() - calls map_sysmem() to set up an abuf + * + * This is equivalent to abuf_set(abuf, map_sysmem(addr, size), size) + * + * Any existing data in the abuf is freed and the alloced member is set to + * false. + * + * @abuf: abuf to adjust + * @addr: Address to set the abuf to + * @size: New size of abuf + */ +void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size); + +/** + * abuf_realloc() - Change the size of a buffer + * + * This uses realloc() to change the size of the buffer, with the same semantics + * as that function. If the abuf is not currently alloced, then it will alloc + * it if the size needs to increase (i.e. set the alloced member to true) + * + * @abuf: abuf to adjust + * @new_size: new size in bytes. + * if 0, the abuf is freed + * if greater than the current size, the abuf is extended and the new + * space is not inited. The alloced member is set to true + * if less than the current size, the abuf is contracted and the data at + * the end is lost. If @new_size is 0, this sets the alloced member to + * false + * @return true if OK, false if out of memory + */ +bool abuf_realloc(struct abuf *abuf, size_t new_size); + +/** + * abuf_uninit_move() - Return the allocated contents and uninit the abuf + * + * This returns the abuf data to the caller, allocating it if necessary, so that + * the caller receives data that it can be sure will hang around. The caller is + * responsible for freeing the data. + * + * If the abuf has allocated data, it is returned. If the abuf has data but it + * is not allocated, then it is first allocated, then returned. + * + * If the abuf size is 0, this returns NULL + * + * The abuf is uninited as part of this, except if the allocation fails, in + * which NULL is returned and the abuf remains untouched. + * + * The abuf must be inited before this can be called. + * + * @abuf: abuf to uninit + * @sizep: if non-NULL, returns the size of the returned data + * @return data contents, allocated with malloc(), or NULL if the data could not + * be allocated, or the data size is 0 + */ +void *abuf_uninit_move(struct abuf *abuf, size_t *sizep); + +/** + * abuf_init_move() - Make abuf take over the management of an allocated region + * + * After this, @data must not be used. All access must be via the abuf. + * + * @abuf: abuf to init + * @data: Existing allocated buffer to place in the abuf + * @size: Size of allocated buffer + */ +void abuf_init_move(struct abuf *abuf, void *data, size_t size); + +/** + * abuf_init_set() - Set up a new abuf + * + * Inits a new abuf and sets up its (unallocated) data + * + * @abuf: abuf to set up + * @data: New contents of abuf + * @size: New size of abuf + */ +void abuf_init_set(struct abuf *abuf, void *data, size_t size); + +/** + * abuf_uninit() - Free any memory used by an abuf + * + * The buffer must be inited before this can be called. + * + * @abuf: abuf to uninit + */ +void abuf_uninit(struct abuf *abuf); + +/** + * abuf_init() - Set up a new abuf + * + * This initially has no data and alloced is set to false. This is equivalent to + * setting all fields to 0, e.g. with memset(), so callers can do that instead + * if desired. + * + * @abuf: abuf to set up + */ +void abuf_init(struct abuf *abuf); + +#endif diff --git a/lib/Makefile b/lib/Makefile index 962470f496..454396f101 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -134,6 +134,7 @@ obj-$(CONFIG_OID_REGISTRY) += oid_registry.o obj-$(CONFIG_SSCANF) += sscanf.o endif +obj-y += abuf.o obj-y += date.o obj-y += rtc-lib.o obj-$(CONFIG_LIB_ELF) += elf.o diff --git a/lib/abuf.c b/lib/abuf.c new file mode 100644 index 0000000000..4b17e0b8c0 --- /dev/null +++ b/lib/abuf.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Handles a buffer that can be allocated and freed + * + * Copyright 2021 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +void abuf_set(struct abuf *abuf, void *data, size_t size) +{ + abuf_uninit(abuf); + abuf->data = data; + abuf->size = size; +} + +void abuf_map_sysmem(struct abuf *abuf, ulong addr, size_t size) +{ + abuf_set(abuf, map_sysmem(addr, size), size); +} + +bool abuf_realloc(struct abuf *abuf, size_t new_size) +{ + void *ptr; + + if (!new_size) { + /* easy case, just need to uninit, freeing any allocation */ + abuf_uninit(abuf); + return true; + } else if (abuf->alloced) { + /* currently allocated, so need to reallocate */ + ptr = realloc(abuf->data, new_size); + if (!ptr) + return false; + abuf->data = ptr; + abuf->size = new_size; + return true; + } else if (new_size <= abuf->size) { + /* + * not currently alloced and new size is no larger. Just update + * it. Data is lost off the end if new_size < abuf->size + */ + abuf->size = new_size; + return true; + } else { + /* not currently allocated and new size is larger. Alloc and + * copy in data. The new space is not inited. + */ + ptr = memdup(abuf->data, new_size); + if (!ptr) + return false; + abuf->data = ptr; + abuf->size = new_size; + abuf->alloced = true; + return true; + } +} + +void *abuf_uninit_move(struct abuf *abuf, size_t *sizep) +{ + void *ptr; + + if (sizep) + *sizep = abuf->size; + if (!abuf->size) + return NULL; + if (abuf->alloced) { + ptr = abuf->data; + } else { + ptr = memdup(abuf->data, abuf->size); + if (!ptr) + return NULL; + } + /* Clear everything out so there is no record of the data */ + abuf_init(abuf); + + return ptr; +} + +void abuf_init_set(struct abuf *abuf, void *data, size_t size) +{ + abuf_init(abuf); + abuf_set(abuf, data, size); +} + +void abuf_init_move(struct abuf *abuf, void *data, size_t size) +{ + abuf_init_set(abuf, data, size); + abuf->alloced = true; +} + +void abuf_uninit(struct abuf *abuf) +{ + if (abuf->alloced) + free(abuf->data); + abuf_init(abuf); +} + +void abuf_init(struct abuf *abuf) +{ + abuf->data = NULL; + abuf->size = 0; + abuf->alloced = false; +} diff --git a/test/lib/Makefile b/test/lib/Makefile index 6fd0514251..d244bb431d 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -3,6 +3,7 @@ # (C) Copyright 2018 # Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc obj-y += cmd_ut_lib.o +obj-y += abuf.o obj-$(CONFIG_EFI_LOADER) += efi_device_path.o obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o obj-y += hexdump.o diff --git a/test/lib/abuf.c b/test/lib/abuf.c new file mode 100644 index 0000000000..086c9b2282 --- /dev/null +++ b/test/lib/abuf.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +static char test_data[] = "1234"; +#define TEST_DATA_LEN sizeof(test_data) + +/* Test abuf_set() */ +static int lib_test_abuf_set(struct unit_test_state *uts) +{ + struct abuf buf; + ulong start; + + start = ut_check_free(); + + abuf_init(&buf); + abuf_set(&buf, test_data, TEST_DATA_LEN); + ut_asserteq_ptr(test_data, buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(false, buf.alloced); + + /* Force it to allocate */ + ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN + 1)); + ut_assertnonnull(buf.data); + ut_asserteq(TEST_DATA_LEN + 1, buf.size); + ut_asserteq(true, buf.alloced); + + /* Now set it again, to force it to free */ + abuf_set(&buf, test_data, TEST_DATA_LEN); + ut_asserteq_ptr(test_data, buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(false, buf.alloced); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_abuf_set, 0); + +/* Test abuf_map_sysmem() */ +static int lib_test_abuf_map_sysmem(struct unit_test_state *uts) +{ + struct abuf buf; + ulong addr; + + abuf_init(&buf); + addr = 0x100; + abuf_map_sysmem(&buf, addr, TEST_DATA_LEN); + + ut_asserteq_ptr(map_sysmem(0x100, 0), buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(false, buf.alloced); + + return 0; +} +LIB_TEST(lib_test_abuf_map_sysmem, 0); + +/* Test abuf_realloc() */ +static int lib_test_abuf_realloc(struct unit_test_state *uts) +{ + struct abuf buf; + ulong start; + void *ptr; + + /* + * TODO: crashes on sandbox sometimes due to an apparent bug in + * realloc(). + */ + return 0; + + start = ut_check_free(); + + abuf_init(&buf); + + /* Allocate an empty buffer */ + ut_asserteq(true, abuf_realloc(&buf, 0)); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + /* Allocate a non-empty abuf */ + ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN)); + ut_assertnonnull(buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(true, buf.alloced); + ptr = buf.data; + + /* + * Make it smaller; the pointer should remain the same. Note this relies + * on knowledge of how U-Boot's realloc() works + */ + ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN - 1)); + ut_asserteq(TEST_DATA_LEN - 1, buf.size); + ut_asserteq(true, buf.alloced); + ut_asserteq_ptr(ptr, buf.data); + + /* + * Make it larger, forcing reallocation. Note this relies on knowledge + * of how U-Boot's realloc() works + */ + ut_asserteq(true, abuf_realloc(&buf, 0x1000)); + ut_assert(buf.data != ptr); + ut_asserteq(0x1000, buf.size); + ut_asserteq(true, buf.alloced); + + /* Free it */ + ut_asserteq(true, abuf_realloc(&buf, 0)); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_abuf_realloc, 0); + +/* Test handling of buffers that are too large */ +static int lib_test_abuf_large(struct unit_test_state *uts) +{ + struct abuf buf; + ulong start; + size_t size; + int delta; + void *ptr; + + /* + * This crashes at present due to trying to allocate more memory than + * available, which breaks something on sandbox. + */ + return 0; + + start = ut_check_free(); + + /* Try an impossible size */ + abuf_init(&buf); + ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN)); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + abuf_uninit(&buf); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + /* Start with a normal size then try to increase it, to check realloc */ + ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN)); + ut_assertnonnull(buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(true, buf.alloced); + ptr = buf.data; + delta = ut_check_delta(start); + ut_assert(delta > 0); + + /* try to increase it */ + ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN)); + ut_asserteq_ptr(ptr, buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(true, buf.alloced); + ut_asserteq(delta, ut_check_delta(start)); + + /* Check for memory leaks */ + abuf_uninit(&buf); + ut_assertok(ut_check_delta(start)); + + /* Start with a huge unallocated buf and try to move it */ + abuf_init(&buf); + abuf_map_sysmem(&buf, 0, CONFIG_SYS_MALLOC_LEN); + ut_asserteq(CONFIG_SYS_MALLOC_LEN, buf.size); + ut_asserteq(false, buf.alloced); + ut_assertnull(abuf_uninit_move(&buf, &size)); + + /* Check for memory leaks */ + abuf_uninit(&buf); + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_abuf_large, 0); + +/* Test abuf_uninit_move() */ +static int lib_test_abuf_uninit_move(struct unit_test_state *uts) +{ + void *ptr, *orig_ptr; + struct abuf buf; + size_t size; + ulong start; + int delta; + + start = ut_check_free(); + + /* + * TODO: crashes on sandbox sometimes due to an apparent bug in + * realloc(). + */ + return 0; + + /* Move an empty buffer */ + abuf_init(&buf); + ut_assertnull(abuf_uninit_move(&buf, &size)); + ut_asserteq(0, size); + ut_assertnull(abuf_uninit_move(&buf, NULL)); + + /* Move an unallocated buffer */ + abuf_set(&buf, test_data, TEST_DATA_LEN); + ut_assertok(ut_check_delta(start)); + ptr = abuf_uninit_move(&buf, &size); + ut_asserteq(TEST_DATA_LEN, size); + ut_asserteq_str(ptr, test_data); + ut_assertnonnull(ptr); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + /* Check that freeing it frees the only allocation */ + delta = ut_check_delta(start); + ut_assert(delta > 0); + free(ptr); + ut_assertok(ut_check_delta(start)); + + /* Move an allocated buffer */ + ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN)); + orig_ptr = buf.data; + strcpy(orig_ptr, test_data); + + delta = ut_check_delta(start); + ut_assert(delta > 0); + ptr = abuf_uninit_move(&buf, &size); + ut_asserteq(TEST_DATA_LEN, size); + ut_assertnonnull(ptr); + ut_asserteq_ptr(ptr, orig_ptr); + ut_asserteq_str(ptr, test_data); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + /* Check there was no new allocation */ + ut_asserteq(delta, ut_check_delta(start)); + + /* Check that freeing it frees the only allocation */ + free(ptr); + ut_assertok(ut_check_delta(start)); + + /* Move an unallocated buffer, without the size */ + abuf_set(&buf, test_data, TEST_DATA_LEN); + ut_assertok(ut_check_delta(start)); + ptr = abuf_uninit_move(&buf, NULL); + ut_asserteq_str(ptr, test_data); + + return 0; +} +LIB_TEST(lib_test_abuf_uninit_move, 0); + +/* Test abuf_uninit() */ +static int lib_test_abuf_uninit(struct unit_test_state *uts) +{ + struct abuf buf; + + /* Nothing in the buffer */ + abuf_init(&buf); + abuf_uninit(&buf); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + /* Not allocated */ + abuf_set(&buf, test_data, TEST_DATA_LEN); + abuf_uninit(&buf); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + return 0; +} +LIB_TEST(lib_test_abuf_uninit, 0); + +/* Test abuf_init_set() */ +static int lib_test_abuf_init_set(struct unit_test_state *uts) +{ + struct abuf buf; + + abuf_init_set(&buf, test_data, TEST_DATA_LEN); + ut_asserteq_ptr(test_data, buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(false, buf.alloced); + + return 0; +} +LIB_TEST(lib_test_abuf_init_set, 0); + +/* Test abuf_init_move() */ +static int lib_test_abuf_init_move(struct unit_test_state *uts) +{ + struct abuf buf; + void *ptr; + + /* + * TODO: crashes on sandbox sometimes due to an apparent bug in + * realloc(). + */ + return 0; + + ptr = strdup(test_data); + ut_assertnonnull(ptr); + + free(ptr); + + abuf_init_move(&buf, ptr, TEST_DATA_LEN); + ut_asserteq_ptr(ptr, abuf_data(&buf)); + ut_asserteq(TEST_DATA_LEN, abuf_size(&buf)); + ut_asserteq(true, buf.alloced); + + return 0; +} +LIB_TEST(lib_test_abuf_init_move, 0); + +/* Test abuf_init() */ +static int lib_test_abuf_init(struct unit_test_state *uts) +{ + struct abuf buf; + + buf.data = &buf; + buf.size = 123; + buf.alloced = true; + abuf_init(&buf); + ut_assertnull(buf.data); + ut_asserteq(0, buf.size); + ut_asserteq(false, buf.alloced); + + return 0; +} +LIB_TEST(lib_test_abuf_init, 0); From c45b7920db21c8e0be89b15ea034ff3e9edb8e1d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:08 -0600 Subject: [PATCH 077/228] compiler: Add a comment to host_build() This function should have a comment explaining what it does. Add one. Signed-off-by: Simon Glass --- include/compiler.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/compiler.h b/include/compiler.h index 27b9843497..67e52050b1 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -151,6 +151,11 @@ typedef unsigned long int uintptr_t; #define MEM_SUPPORT_64BIT_DATA 0 #endif +/** + * host_build() - check if we are building for the host + * + * @return true if building for the host, false if for a target + */ static inline bool host_build(void) { #ifdef USE_HOSTCC return true; From 94d0a2efc0315e2c5e3b62a7420292f0ce058079 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:09 -0600 Subject: [PATCH 078/228] zstd: Create a function for use from U-Boot The existing zstd API requires the same sequence of calls to perform its task. Create a helper for U-Boot, to avoid code duplication, as is done with other compression algorithms. Make use of of this from the image code. Note that the zstd code lacks a test in test/compression.c and this should be added by the maintainer. Signed-off-by: Simon Glass --- common/image.c | 50 +++++++--------------------------- include/linux/zstd.h | 11 ++++++++ lib/zstd/Makefile | 2 +- lib/zstd/zstd.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+), 42 deletions(-) create mode 100644 lib/zstd/zstd.c diff --git a/common/image.c b/common/image.c index 8ac57081fd..2437223018 100644 --- a/common/image.c +++ b/common/image.c @@ -22,6 +22,7 @@ #include #endif +#include #include #include @@ -527,50 +528,17 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, #ifndef USE_HOSTCC #if CONFIG_IS_ENABLED(ZSTD) case IH_COMP_ZSTD: { - size_t size = unc_len; - ZSTD_DStream *dstream; - ZSTD_inBuffer in_buf; - ZSTD_outBuffer out_buf; - void *workspace; - size_t wsize; + struct abuf in, out; - wsize = ZSTD_DStreamWorkspaceBound(image_len); - workspace = malloc(wsize); - if (!workspace) { - debug("%s: cannot allocate workspace of size %zu\n", __func__, - wsize); - return -1; + abuf_init_set(&in, image_buf, image_len); + abuf_init_set(&in, load_buf, unc_len); + ret = zstd_decompress(&in, &out); + if (ret < 0) { + printf("ZSTD decompression failed\n"); + return ret; } - dstream = ZSTD_initDStream(image_len, workspace, wsize); - if (!dstream) { - printf("%s: ZSTD_initDStream failed\n", __func__); - return ZSTD_getErrorCode(ret); - } - - in_buf.src = image_buf; - in_buf.pos = 0; - in_buf.size = image_len; - - out_buf.dst = load_buf; - out_buf.pos = 0; - out_buf.size = size; - - while (1) { - size_t ret; - - ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf); - if (ZSTD_isError(ret)) { - printf("%s: ZSTD_decompressStream error %d\n", __func__, - ZSTD_getErrorCode(ret)); - return ZSTD_getErrorCode(ret); - } - - if (in_buf.pos >= image_len || !ret) - break; - } - - image_len = out_buf.pos; + image_len = ret; break; } diff --git a/include/linux/zstd.h b/include/linux/zstd.h index 724f69350e..35ba4c90aa 100644 --- a/include/linux/zstd.h +++ b/include/linux/zstd.h @@ -1144,4 +1144,15 @@ size_t ZSTD_decompressBlock(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart, size_t blockSize); +struct abuf; + +/** + * zstd_decompress() - Decompress Zstandard data + * + * @in: Input buffer to decompress + * @out: Output buffer to hold the results (must be large enough) + * @return size of the decompressed data, or -ve on error + */ +int zstd_decompress(struct abuf *in, struct abuf *out); + #endif /* ZSTD_H */ diff --git a/lib/zstd/Makefile b/lib/zstd/Makefile index 33c1df48ec..1217089292 100644 --- a/lib/zstd/Makefile +++ b/lib/zstd/Makefile @@ -1,4 +1,4 @@ obj-y += zstd_decompress.o zstd_decompress-y := huf_decompress.o decompress.o \ - entropy_common.o fse_decompress.o zstd_common.o + entropy_common.o fse_decompress.o zstd_common.o zstd.o diff --git a/lib/zstd/zstd.c b/lib/zstd/zstd.c new file mode 100644 index 0000000000..bf9cd19cfa --- /dev/null +++ b/lib/zstd/zstd.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Google LLC + */ + +#define LOG_CATEGORY LOGC_BOOT + +#include +#include +#include +#include +#include + +int zstd_decompress(struct abuf *in, struct abuf *out) +{ + ZSTD_DStream *dstream; + ZSTD_inBuffer in_buf; + ZSTD_outBuffer out_buf; + void *workspace; + size_t wsize; + int ret; + + wsize = ZSTD_DStreamWorkspaceBound(abuf_size(in)); + workspace = malloc(wsize); + if (!workspace) { + debug("%s: cannot allocate workspace of size %zu\n", __func__, + wsize); + return -ENOMEM; + } + + dstream = ZSTD_initDStream(abuf_size(in), workspace, wsize); + if (!dstream) { + log_err("%s: ZSTD_initDStream failed\n", __func__); + ret = -EPERM; + goto do_free; + } + + in_buf.src = abuf_data(in); + in_buf.pos = 0; + in_buf.size = abuf_size(in); + + out_buf.dst = abuf_data(out); + out_buf.pos = 0; + out_buf.size = abuf_size(out); + + while (1) { + size_t res; + + res = ZSTD_decompressStream(dstream, &out_buf, &in_buf); + if (ZSTD_isError(res)) { + ret = ZSTD_getErrorCode(res); + log_err("ZSTD_decompressStream error %d\n", ret); + goto do_free; + } + + if (in_buf.pos >= abuf_size(in) || !res) + break; + } + + ret = out_buf.pos; +do_free: + free(workspace); + return ret; +} From 918adf8e07337719750c57be0939824247973b1e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:10 -0600 Subject: [PATCH 079/228] btrfs: Use U-Boot API for decompression Use the common function to avoid code duplication. Acked-by: Qu Wenruo Signed-off-by: Simon Glass --- fs/btrfs/compression.c | 51 +++++------------------------------------- 1 file changed, 5 insertions(+), 46 deletions(-) diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c index 23efefa199..7adfbb04a7 100644 --- a/fs/btrfs/compression.c +++ b/fs/btrfs/compression.c @@ -6,6 +6,7 @@ */ #include "btrfs.h" +#include #include #include #include @@ -136,54 +137,12 @@ static u32 decompress_zlib(const u8 *_cbuf, u32 clen, u8 *dbuf, u32 dlen) static u32 decompress_zstd(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) { - ZSTD_DStream *dstream; - ZSTD_inBuffer in_buf; - ZSTD_outBuffer out_buf; - void *workspace; - size_t wsize; - u32 res = -1; + struct abuf in, out; - wsize = ZSTD_DStreamWorkspaceBound(ZSTD_BTRFS_MAX_INPUT); - workspace = malloc(wsize); - if (!workspace) { - debug("%s: cannot allocate workspace of size %zu\n", __func__, - wsize); - return -1; - } + abuf_init_set(&in, (u8 *)cbuf, clen); + abuf_init_set(&out, dbuf, dlen); - dstream = ZSTD_initDStream(ZSTD_BTRFS_MAX_INPUT, workspace, wsize); - if (!dstream) { - printf("%s: ZSTD_initDStream failed\n", __func__); - goto err_free; - } - - in_buf.src = cbuf; - in_buf.pos = 0; - in_buf.size = clen; - - out_buf.dst = dbuf; - out_buf.pos = 0; - out_buf.size = dlen; - - while (1) { - size_t ret; - - ret = ZSTD_decompressStream(dstream, &out_buf, &in_buf); - if (ZSTD_isError(ret)) { - printf("%s: ZSTD_decompressStream error %d\n", __func__, - ZSTD_getErrorCode(ret)); - goto err_free; - } - - if (in_buf.pos >= clen || !ret) - break; - } - - res = out_buf.pos; - -err_free: - free(workspace); - return res; + return zstd_decompress(&in, &out); } u32 btrfs_decompress(u8 type, const char *c, u32 clen, char *d, u32 dlen) From b876eb87e91d6705ef946090af16175dfb5ce1f9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:11 -0600 Subject: [PATCH 080/228] image: Avoid switch default in image_decomp() At present this function is full of preprocessor macros. Adjust it to check for an unsupported algorithm after the switch(). This will allow us to drop the macros. Fix up the return-value path and an extra blank line while we are here. Signed-off-by: Simon Glass --- common/image.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/common/image.c b/common/image.c index 2437223018..1102483e0a 100644 --- a/common/image.c +++ b/common/image.c @@ -446,7 +446,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, void *load_buf, void *image_buf, ulong image_len, uint unc_len, ulong *load_end) { - int ret = 0; + int ret = -ENOSYS; *load_end = load; print_decomp_msg(comp, type, load == image_start); @@ -458,6 +458,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, */ switch (comp) { case IH_COMP_NONE: + ret = 0; if (load == image_start) break; if (image_len <= unc_len) @@ -539,22 +540,23 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, } image_len = ret; - break; } #endif /* CONFIG_ZSTD */ #endif - default: - printf("Unimplemented compression type %d\n", comp); - return -ENOSYS; } + if (ret == -ENOSYS) { + printf("Unimplemented compression type %d\n", comp); + return ret; + } + if (ret) + return ret; *load_end = load + image_len; - return ret; + return 0; } - #ifndef USE_HOSTCC #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) /** From 02ace2cd4942da507414b23645cd7bec99f23174 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:12 -0600 Subject: [PATCH 081/228] image: Update zstd to avoid reporting error twice The zstd implementation prints the error in image_decomp() which is incorrect and does not match other algorithms. Drop this and let the caller report the error. Signed-off-by: Simon Glass --- common/image.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/common/image.c b/common/image.c index 1102483e0a..62314a9f59 100644 --- a/common/image.c +++ b/common/image.c @@ -534,12 +534,10 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, abuf_init_set(&in, image_buf, image_len); abuf_init_set(&in, load_buf, unc_len); ret = zstd_decompress(&in, &out); - if (ret < 0) { - printf("ZSTD decompression failed\n"); - return ret; + if (ret >= 0) { + image_len = ret; + ret = 0; } - - image_len = ret; break; } #endif /* CONFIG_ZSTD */ From 5a4f10d71bfe2b7a5646cf1f96b298805b36df7a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:13 -0600 Subject: [PATCH 082/228] gzip: Avoid use of u64 The gzip API uses the u64 type in it, which is not available in the host build. This makes it impossible to include the header file. We could make this type available, but it seems unnecessary. Limiting the compression size to that of the 'unsigned long' type seems good enough. On 32-bit machines the limit then becomes 4GB, which likely exceeds available RAM anyway, therefore it should be sufficient. On 64-bit machines this is effectively u64 anyway. Update the header file and implementation to use 'ulong' instead of 'u64'. Add a definition of u32 for the cases that seem to need exactly that length. This should be safe enough. Signed-off-by: Simon Glass --- include/compiler.h | 3 +++ include/gzip.h | 8 ++++---- lib/gunzip.c | 28 ++++++++++++++-------------- 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/include/compiler.h b/include/compiler.h index 67e52050b1..6b0d3bf537 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -68,6 +68,9 @@ typedef uint32_t __u32; typedef unsigned int uint; typedef unsigned long ulong; +/* Define these on the host so we can build some target code */ +typedef __u32 u32; + #define uswap_16(x) \ ((((x) & 0xff00) >> 8) | \ (((x) & 0x00ff) << 8)) diff --git a/include/gzip.h b/include/gzip.h index 783acbb60d..cb4db3d70f 100644 --- a/include/gzip.h +++ b/include/gzip.h @@ -54,11 +54,11 @@ int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, * gzwrite_progress_finish called at end of loop to * indicate success (retcode=0) or failure */ -void gzwrite_progress_init(u64 expected_size); +void gzwrite_progress_init(ulong expected_size); -void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes); +void gzwrite_progress(int iteration, ulong bytes_written, ulong total_bytes); -void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize, +void gzwrite_progress_finish(int retcode, ulong totalwritten, ulong totalsize, u32 expected_crc, u32 calculated_crc); /** @@ -74,7 +74,7 @@ void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize, * @return 0 if OK, -1 on error */ int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf, - u64 startoffs, u64 szexpected); + ulong startoffs, ulong szexpected); /** * gzip()- Compress data into a buffer using the gzip algorithm diff --git a/lib/gunzip.c b/lib/gunzip.c index bee3b9261f..a8e498d98d 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -84,32 +84,32 @@ int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) #ifdef CONFIG_CMD_UNZIP __weak -void gzwrite_progress_init(u64 expectedsize) +void gzwrite_progress_init(ulong expectedsize) { putc('\n'); } __weak void gzwrite_progress(int iteration, - u64 bytes_written, - u64 total_bytes) + ulong bytes_written, + ulong total_bytes) { if (0 == (iteration & 3)) - printf("%llu/%llu\r", bytes_written, total_bytes); + printf("%lu/%lu\r", bytes_written, total_bytes); } __weak void gzwrite_progress_finish(int returnval, - u64 bytes_written, - u64 total_bytes, + ulong bytes_written, + ulong total_bytes, u32 expected_crc, u32 calculated_crc) { if (0 == returnval) { - printf("\n\t%llu bytes, crc 0x%08x\n", + printf("\n\t%lu bytes, crc 0x%08x\n", total_bytes, calculated_crc); } else { - printf("\n\tuncompressed %llu of %llu\n" + printf("\n\tuncompressed %lu of %lu\n" "\tcrcs == 0x%08x/0x%08x\n", bytes_written, total_bytes, expected_crc, calculated_crc); @@ -119,15 +119,15 @@ void gzwrite_progress_finish(int returnval, int gzwrite(unsigned char *src, int len, struct blk_desc *dev, unsigned long szwritebuf, - u64 startoffs, - u64 szexpected) + ulong startoffs, + ulong szexpected) { int i, flags; z_stream s; int r = 0; unsigned char *writebuf; unsigned crc = 0; - u64 totalfilled = 0; + ulong totalfilled = 0; lbaint_t blksperbuf, outblock; u32 expected_crc; u32 payload_size; @@ -142,7 +142,7 @@ int gzwrite(unsigned char *src, int len, } if (startoffs & (dev->blksz-1)) { - printf("%s: start offset %llu not a multiple of %lu\n", + printf("%s: start offset %lu not a multiple of %lu\n", __func__, startoffs, dev->blksz); return -1; } @@ -182,12 +182,12 @@ int gzwrite(unsigned char *src, int len, if (szexpected == 0) { szexpected = le32_to_cpu(szuncompressed); } else if (szuncompressed != (u32)szexpected) { - printf("size of %llx doesn't match trailer low bits %x\n", + printf("size of %lx doesn't match trailer low bits %x\n", szexpected, szuncompressed); return -1; } if (lldiv(szexpected, dev->blksz) > (dev->lba - outblock)) { - printf("%s: uncompressed size %llu exceeds device size\n", + printf("%s: uncompressed size %lu exceeds device size\n", __func__, szexpected); return -1; } From 458b30af66cd41ca8e6f8a52ea4c09cb50d3413d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:14 -0600 Subject: [PATCH 083/228] image: Update image_decomp() to avoid ifdefs Adjust this function so that preprocessor macros are not needed. With this, the host build uses more of the same header files as the target build. Rather than definining CONFIG_SYS_MALLOC_LEN, add a CONSERVE_MEMORY define, since that is the purpose of the value. This appears to have no impact on code size from a spot check of a few boards (snow, firefly-rk3288, boston32r2el, m53menlo). Signed-off-by: Simon Glass --- common/image.c | 159 ++++++++++++++++++-------------------- configs/sandbox_defconfig | 1 + 2 files changed, 76 insertions(+), 84 deletions(-) diff --git a/common/image.c b/common/image.c index 62314a9f59..e16d433b91 100644 --- a/common/image.c +++ b/common/image.c @@ -22,12 +22,9 @@ #include #endif -#include #include -#include #include -#include #include #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT @@ -43,13 +40,6 @@ #include #include -#include -#include -#include -#include -#include -#include - #ifdef CONFIG_CMD_BDI extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); @@ -61,7 +51,15 @@ DECLARE_GLOBAL_DATA_PTR; static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, int verify); #endif + +/* Set this if we have less than 4 MB of malloc() space */ +#if CONFIG_SYS_MALLOC_LEN < (4096 * 1024) +#define CONSERVE_MEMORY true #else +#define CONSERVE_MEMORY false +#endif + +#else /* USE_HOSTCC */ #include "mkimage.h" #include #include @@ -70,10 +68,23 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #ifndef __maybe_unused # define __maybe_unused /* unimplemented */ #endif + +#define CONSERVE_MEMORY false + #endif /* !USE_HOSTCC*/ -#include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include #ifndef CONFIG_SYS_BARGSIZE #define CONFIG_SYS_BARGSIZE 512 @@ -466,82 +477,62 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, else ret = -ENOSPC; break; -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(GZIP) - case IH_COMP_GZIP: { - ret = gunzip(load_buf, unc_len, image_buf, &image_len); + case IH_COMP_GZIP: + if (!host_build() && CONFIG_IS_ENABLED(GZIP)) + ret = gunzip(load_buf, unc_len, image_buf, &image_len); break; - } -#endif /* CONFIG_GZIP */ -#endif -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(BZIP2) - case IH_COMP_BZIP2: { - uint size = unc_len; + case IH_COMP_BZIP2: + if (!host_build() && CONFIG_IS_ENABLED(BZIP2)) { + uint size = unc_len; - /* - * If we've got less than 4 MB of malloc() space, - * use slower decompression algorithm which requires - * at most 2300 KB of memory. - */ - ret = BZ2_bzBuffToBuffDecompress(load_buf, &size, - image_buf, image_len, - CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); - image_len = size; - break; - } -#endif /* CONFIG_BZIP2 */ -#endif -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(LZMA) - case IH_COMP_LZMA: { - SizeT lzma_len = unc_len; - - ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, - image_buf, image_len); - image_len = lzma_len; - break; - } -#endif /* CONFIG_LZMA */ -#endif -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(LZO) - case IH_COMP_LZO: { - size_t size = unc_len; - - ret = lzop_decompress(image_buf, image_len, load_buf, &size); - image_len = size; - break; - } -#endif /* CONFIG_LZO */ -#endif -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(LZ4) - case IH_COMP_LZ4: { - size_t size = unc_len; - - ret = ulz4fn(image_buf, image_len, load_buf, &size); - image_len = size; - break; - } -#endif /* CONFIG_LZ4 */ -#endif -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(ZSTD) - case IH_COMP_ZSTD: { - struct abuf in, out; - - abuf_init_set(&in, image_buf, image_len); - abuf_init_set(&in, load_buf, unc_len); - ret = zstd_decompress(&in, &out); - if (ret >= 0) { - image_len = ret; - ret = 0; + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + ret = BZ2_bzBuffToBuffDecompress(load_buf, &size, + image_buf, image_len, CONSERVE_MEMORY, 0); + image_len = size; + } + break; + case IH_COMP_LZMA: + if (!host_build() && CONFIG_IS_ENABLED(LZMA)) { + SizeT lzma_len = unc_len; + + ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, + image_buf, image_len); + image_len = lzma_len; + } + break; + case IH_COMP_LZO: + if (!host_build() && CONFIG_IS_ENABLED(LZO)) { + size_t size = unc_len; + + ret = lzop_decompress(image_buf, image_len, load_buf, &size); + image_len = size; + } + break; + case IH_COMP_LZ4: + if (!host_build() && CONFIG_IS_ENABLED(LZ4)) { + size_t size = unc_len; + + ret = ulz4fn(image_buf, image_len, load_buf, &size); + image_len = size; + } + break; + case IH_COMP_ZSTD: + if (!host_build() && CONFIG_IS_ENABLED(ZSTD)) { + struct abuf in, out; + + abuf_init_set(&in, image_buf, image_len); + abuf_init_set(&in, load_buf, unc_len); + ret = zstd_decompress(&in, &out); + if (ret >= 0) { + image_len = ret; + ret = 0; + } } break; - } -#endif /* CONFIG_ZSTD */ -#endif } if (ret == -ENOSYS) { printf("Unimplemented compression type %d\n", comp); @@ -960,7 +951,7 @@ int get_table_entry_id(const table_entry_t *table, const table_entry_t *t; for (t = table; t->id >= 0; ++t) { -#ifdef CONFIG_NEEDS_MANUAL_RELOC +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) if (t->sname && strcasecmp(t->sname + gd->reloc_off, name) == 0) #else if (t->sname && strcasecmp(t->sname, name) == 0) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index f1067b9ada..d601677190 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -56,6 +56,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEM_SEARCH=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_UNZIP=y CONFIG_CMD_BIND=y CONFIG_CMD_DEMO=y CONFIG_CMD_GPIO=y From 41506ff5a51fb95896683bc8def8dbf53ef93de1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:15 -0600 Subject: [PATCH 084/228] image: Split board code out into its own file To avoid a large #ifdef in the image.c file, move the affected code into a separate file. Avoid any style fix-ups for easier review. Those are in the next patch. Signed-off-by: Simon Glass --- common/Makefile | 2 +- common/image-board.c | 925 +++++++++++++++++++++++++++++++++++++++++++ common/image.c | 925 +------------------------------------------ 3 files changed, 928 insertions(+), 924 deletions(-) create mode 100644 common/image-board.c diff --git a/common/Makefile b/common/Makefile index fb8173a5b8..e7839027b6 100644 --- a/common/Makefile +++ b/common/Makefile @@ -101,7 +101,7 @@ obj-y += malloc_simple.o endif endif -obj-y += image.o +obj-y += image.o image-board.o obj-$(CONFIG_$(SPL_TPL_)HASH) += hash.o obj-$(CONFIG_ANDROID_AB) += android_ab.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o image-android-dt.o diff --git a/common/image-board.c b/common/image-board.c new file mode 100644 index 0000000000..63cbf5f901 --- /dev/null +++ b/common/image-board.c @@ -0,0 +1,925 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Image code used by boards (and not host tools) + * + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE 512 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) +/** + * image_get_ramdisk - get and verify ramdisk image + * @rd_addr: ramdisk image start address + * @arch: expected ramdisk architecture + * @verify: checksum verification flag + * + * image_get_ramdisk() returns a pointer to the verified ramdisk image + * header. Routine receives image start address and expected architecture + * flag. Verification done covers data and header integrity and os/type/arch + * fields checking. + * + * returns: + * pointer to a ramdisk image header, if image was found and valid + * otherwise, return NULL + */ +static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, + int verify) +{ + const image_header_t *rd_hdr = (const image_header_t *)rd_addr; + + if (!image_check_magic(rd_hdr)) { + puts("Bad Magic Number\n"); + bootstage_error(BOOTSTAGE_ID_RD_MAGIC); + return NULL; + } + + if (!image_check_hcrc(rd_hdr)) { + puts("Bad Header Checksum\n"); + bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM); + return NULL; + } + + bootstage_mark(BOOTSTAGE_ID_RD_MAGIC); + image_print_contents(rd_hdr); + + if (verify) { + puts(" Verifying Checksum ... "); + if (!image_check_dcrc(rd_hdr)) { + puts("Bad Data CRC\n"); + bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM); + return NULL; + } + puts("OK\n"); + } + + bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM); + + if (!image_check_os(rd_hdr, IH_OS_LINUX) || + !image_check_arch(rd_hdr, arch) || + !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) { + printf("No Linux %s Ramdisk Image\n", + genimg_get_arch_name(arch)); + bootstage_error(BOOTSTAGE_ID_RAMDISK); + return NULL; + } + + return rd_hdr; +} +#endif + +/*****************************************************************************/ +/* Shared dual-format routines */ +/*****************************************************************************/ +ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */ +ulong image_save_addr; /* Default Save Address */ +ulong image_save_size; /* Default Save Size (in bytes) */ + +static int on_loadaddr(const char *name, const char *value, enum env_op op, + int flags) +{ + switch (op) { + case env_op_create: + case env_op_overwrite: + image_load_addr = hextoul(value, NULL); + break; + default: + break; + } + + return 0; +} +U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr); + +ulong env_get_bootm_low(void) +{ + char *s = env_get("bootm_low"); + if (s) { + ulong tmp = hextoul(s, NULL); + return tmp; + } + +#if defined(CONFIG_SYS_SDRAM_BASE) + return CONFIG_SYS_SDRAM_BASE; +#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) + return gd->bd->bi_dram[0].start; +#else + return 0; +#endif +} + +phys_size_t env_get_bootm_size(void) +{ + phys_size_t tmp, size; + phys_addr_t start; + char *s = env_get("bootm_size"); + if (s) { + tmp = (phys_size_t)simple_strtoull(s, NULL, 16); + return tmp; + } + + start = gd->ram_base; + size = gd->ram_size; + + if (start + size > gd->ram_top) + size = gd->ram_top - start; + + s = env_get("bootm_low"); + if (s) + tmp = (phys_size_t)simple_strtoull(s, NULL, 16); + else + tmp = start; + + return size - (tmp - start); +} + +phys_size_t env_get_bootm_mapsize(void) +{ + phys_size_t tmp; + char *s = env_get("bootm_mapsize"); + if (s) { + tmp = (phys_size_t)simple_strtoull(s, NULL, 16); + return tmp; + } + +#if defined(CONFIG_SYS_BOOTMAPSZ) + return CONFIG_SYS_BOOTMAPSZ; +#else + return env_get_bootm_size(); +#endif +} + +void memmove_wd(void *to, void *from, size_t len, ulong chunksz) +{ + if (to == from) + return; + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + if (to > from) { + from += len; + to += len; + } + while (len > 0) { + size_t tail = (len > chunksz) ? chunksz : len; + WATCHDOG_RESET(); + if (to > from) { + to -= tail; + from -= tail; + } + memmove(to, from, tail); + if (to < from) { + to += tail; + from += tail; + } + len -= tail; + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove(to, from, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ +} + +/** + * genimg_get_kernel_addr_fit - get the real kernel address and return 2 + * FIT strings + * @img_addr: a string might contain real image address + * @fit_uname_config: double pointer to a char, will hold pointer to a + * configuration unit name + * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage + * name + * + * genimg_get_kernel_addr_fit get the real kernel start address from a string + * which is normally the first argv of bootm/bootz + * + * returns: + * kernel start address + */ +ulong genimg_get_kernel_addr_fit(char * const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel) +{ + ulong kernel_addr; + + /* find out kernel image address */ + if (!img_addr) { + kernel_addr = image_load_addr; + debug("* kernel: default image load address = 0x%08lx\n", + image_load_addr); +#if CONFIG_IS_ENABLED(FIT) + } else if (fit_parse_conf(img_addr, image_load_addr, &kernel_addr, + fit_uname_config)) { + debug("* kernel: config '%s' from image at 0x%08lx\n", + *fit_uname_config, kernel_addr); + } else if (fit_parse_subimage(img_addr, image_load_addr, &kernel_addr, + fit_uname_kernel)) { + debug("* kernel: subimage '%s' from image at 0x%08lx\n", + *fit_uname_kernel, kernel_addr); +#endif + } else { + kernel_addr = hextoul(img_addr, NULL); + debug("* kernel: cmdline image address = 0x%08lx\n", + kernel_addr); + } + + return kernel_addr; +} + +/** + * genimg_get_kernel_addr() is the simple version of + * genimg_get_kernel_addr_fit(). It ignores those return FIT strings + */ +ulong genimg_get_kernel_addr(char * const img_addr) +{ + const char *fit_uname_config = NULL; + const char *fit_uname_kernel = NULL; + + return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config, + &fit_uname_kernel); +} + +/** + * genimg_get_format - get image format type + * @img_addr: image start address + * + * genimg_get_format() checks whether provided address points to a valid + * legacy or FIT image. + * + * New uImage format and FDT blob are based on a libfdt. FDT blob + * may be passed directly or embedded in a FIT image. In both situations + * genimg_get_format() must be able to dectect libfdt header. + * + * returns: + * image format type or IMAGE_FORMAT_INVALID if no image is present + */ +int genimg_get_format(const void *img_addr) +{ +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) + const image_header_t *hdr; + + hdr = (const image_header_t *)img_addr; + if (image_check_magic(hdr)) + return IMAGE_FORMAT_LEGACY; +#endif +#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT + if (fdt_check_header(img_addr) == 0) + return IMAGE_FORMAT_FIT; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + if (android_image_check_header(img_addr) == 0) + return IMAGE_FORMAT_ANDROID; +#endif + + return IMAGE_FORMAT_INVALID; +} + +/** + * fit_has_config - check if there is a valid FIT configuration + * @images: pointer to the bootm command headers structure + * + * fit_has_config() checks if there is a FIT configuration in use + * (if FTI support is present). + * + * returns: + * 0, no FIT support or no configuration found + * 1, configuration found + */ +int genimg_has_config(bootm_headers_t *images) +{ +#if IMAGE_ENABLE_FIT + if (images->fit_uname_cfg) + return 1; +#endif + return 0; +} + +/** + * boot_get_ramdisk - main ramdisk handling routine + * @argc: command argument count + * @argv: command argument list + * @images: pointer to the bootm images structure + * @arch: expected ramdisk architecture + * @rd_start: pointer to a ulong variable, will hold ramdisk start address + * @rd_end: pointer to a ulong variable, will hold ramdisk end + * + * boot_get_ramdisk() is responsible for finding a valid ramdisk image. + * Curently supported are the following ramdisk sources: + * - multicomponent kernel/ramdisk image, + * - commandline provided address of decicated ramdisk image. + * + * returns: + * 0, if ramdisk image was found and valid, or skiped + * rd_start and rd_end are set to ramdisk start/end addresses if + * ramdisk image is found and valid + * + * 1, if ramdisk image is found but corrupted, or invalid + * rd_start and rd_end are set to 0 if no ramdisk exists + */ +int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, + uint8_t arch, ulong *rd_start, ulong *rd_end) +{ + ulong rd_addr, rd_load; + ulong rd_data, rd_len; +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) + const image_header_t *rd_hdr; +#endif + void *buf; +#ifdef CONFIG_SUPPORT_RAW_INITRD + char *end; +#endif +#if IMAGE_ENABLE_FIT + const char *fit_uname_config = images->fit_uname_cfg; + const char *fit_uname_ramdisk = NULL; + ulong default_addr; + int rd_noffset; +#endif + const char *select = NULL; + + *rd_start = 0; + *rd_end = 0; + +#ifdef CONFIG_ANDROID_BOOT_IMAGE + /* + * Look for an Android boot image. + */ + buf = map_sysmem(images->os.start, 0); + if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) + select = (argc == 0) ? env_get("loadaddr") : argv[0]; +#endif + + if (argc >= 2) + select = argv[1]; + + /* + * Look for a '-' which indicates to ignore the + * ramdisk argument + */ + if (select && strcmp(select, "-") == 0) { + debug("## Skipping init Ramdisk\n"); + rd_len = rd_data = 0; + } else if (select || genimg_has_config(images)) { +#if IMAGE_ENABLE_FIT + if (select) { + /* + * If the init ramdisk comes from the FIT image and + * the FIT image address is omitted in the command + * line argument, try to use os FIT image address or + * default load address. + */ + if (images->fit_uname_os) + default_addr = (ulong)images->fit_hdr_os; + else + default_addr = image_load_addr; + + if (fit_parse_conf(select, default_addr, + &rd_addr, &fit_uname_config)) { + debug("* ramdisk: config '%s' from image at " + "0x%08lx\n", + fit_uname_config, rd_addr); + } else if (fit_parse_subimage(select, default_addr, + &rd_addr, &fit_uname_ramdisk)) { + debug("* ramdisk: subimage '%s' from image at " + "0x%08lx\n", + fit_uname_ramdisk, rd_addr); + } else +#endif + { + rd_addr = hextoul(select, NULL); + debug("* ramdisk: cmdline image address = " + "0x%08lx\n", + rd_addr); + } +#if IMAGE_ENABLE_FIT + } else { + /* use FIT configuration provided in first bootm + * command argument. If the property is not defined, + * quit silently. + */ + rd_addr = map_to_sysmem(images->fit_hdr_os); + rd_noffset = fit_get_node_from_config(images, + FIT_RAMDISK_PROP, rd_addr); + if (rd_noffset == -ENOENT) + return 0; + else if (rd_noffset < 0) + return 1; + } +#endif + + /* + * Check if there is an initrd image at the + * address provided in the second bootm argument + * check image type, for FIT images get FIT node. + */ + buf = map_sysmem(rd_addr, 0); + switch (genimg_get_format(buf)) { +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) + case IMAGE_FORMAT_LEGACY: + printf("## Loading init Ramdisk from Legacy " + "Image at %08lx ...\n", rd_addr); + + bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK); + rd_hdr = image_get_ramdisk(rd_addr, arch, + images->verify); + + if (rd_hdr == NULL) + return 1; + + rd_data = image_get_data(rd_hdr); + rd_len = image_get_data_size(rd_hdr); + rd_load = image_get_load(rd_hdr); + break; +#endif +#if IMAGE_ENABLE_FIT + case IMAGE_FORMAT_FIT: + rd_noffset = fit_image_load(images, + rd_addr, &fit_uname_ramdisk, + &fit_uname_config, arch, + IH_TYPE_RAMDISK, + BOOTSTAGE_ID_FIT_RD_START, + FIT_LOAD_OPTIONAL_NON_ZERO, + &rd_data, &rd_len); + if (rd_noffset < 0) + return 1; + + images->fit_hdr_rd = map_sysmem(rd_addr, 0); + images->fit_uname_rd = fit_uname_ramdisk; + images->fit_noffset_rd = rd_noffset; + break; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + android_image_get_ramdisk((void *)images->os.start, + &rd_data, &rd_len); + break; +#endif + default: +#ifdef CONFIG_SUPPORT_RAW_INITRD + end = NULL; + if (select) + end = strchr(select, ':'); + if (end) { + rd_len = hextoul(++end, NULL); + rd_data = rd_addr; + } else +#endif + { + puts("Wrong Ramdisk Image Format\n"); + rd_data = rd_len = rd_load = 0; + return 1; + } + } + } else if (images->legacy_hdr_valid && + image_check_type(&images->legacy_hdr_os_copy, + IH_TYPE_MULTI)) { + + /* + * Now check if we have a legacy mult-component image, + * get second entry data start address and len. + */ + bootstage_mark(BOOTSTAGE_ID_RAMDISK); + printf("## Loading init Ramdisk from multi component " + "Legacy Image at %08lx ...\n", + (ulong)images->legacy_hdr_os); + + image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len); + } else { + /* + * no initrd image + */ + bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK); + rd_len = rd_data = 0; + } + + if (!rd_data) { + debug("## No init Ramdisk\n"); + } else { + *rd_start = rd_data; + *rd_end = rd_data + rd_len; + } + debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n", + *rd_start, *rd_end); + + return 0; +} + +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH +/** + * boot_ramdisk_high - relocate init ramdisk + * @lmb: pointer to lmb handle, will be used for memory mgmt + * @rd_data: ramdisk data start address + * @rd_len: ramdisk data length + * @initrd_start: pointer to a ulong variable, will hold final init ramdisk + * start address (after possible relocation) + * @initrd_end: pointer to a ulong variable, will hold final init ramdisk + * end address (after possible relocation) + * + * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment + * variable and if requested ramdisk data is moved to a specified location. + * + * Initrd_start and initrd_end are set to final (after relocation) ramdisk + * start/end addresses if ramdisk image start and len were provided, + * otherwise set initrd_start and initrd_end set to zeros. + * + * returns: + * 0 - success + * -1 - failure + */ +int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, + ulong *initrd_start, ulong *initrd_end) +{ + char *s; + ulong initrd_high; + int initrd_copy_to_ram = 1; + + s = env_get("initrd_high"); + if (s) { + /* a value of "no" or a similar string will act like 0, + * turning the "load high" feature off. This is intentional. + */ + initrd_high = hextoul(s, NULL); + if (initrd_high == ~0) + initrd_copy_to_ram = 0; + } else { + initrd_high = env_get_bootm_mapsize() + env_get_bootm_low(); + } + + + debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n", + initrd_high, initrd_copy_to_ram); + + if (rd_data) { + if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + debug(" in-place initrd\n"); + *initrd_start = rd_data; + *initrd_end = rd_data + rd_len; + lmb_reserve(lmb, rd_data, rd_len); + } else { + if (initrd_high) + *initrd_start = (ulong)lmb_alloc_base(lmb, + rd_len, 0x1000, initrd_high); + else + *initrd_start = (ulong)lmb_alloc(lmb, rd_len, + 0x1000); + + if (*initrd_start == 0) { + puts("ramdisk - allocation error\n"); + goto error; + } + bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK); + + *initrd_end = *initrd_start + rd_len; + printf(" Loading Ramdisk to %08lx, end %08lx ... ", + *initrd_start, *initrd_end); + + memmove_wd((void *)*initrd_start, + (void *)rd_data, rd_len, CHUNKSZ); + +#ifdef CONFIG_MP + /* + * Ensure the image is flushed to memory to handle + * AMP boot scenarios in which we might not be + * HW cache coherent + */ + flush_cache((unsigned long)*initrd_start, + ALIGN(rd_len, ARCH_DMA_MINALIGN)); +#endif + puts("OK\n"); + } + } else { + *initrd_start = 0; + *initrd_end = 0; + } + debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n", + *initrd_start, *initrd_end); + + return 0; + +error: + return -1; +} +#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ + +int boot_get_setup(bootm_headers_t *images, uint8_t arch, + ulong *setup_start, ulong *setup_len) +{ +#if IMAGE_ENABLE_FIT + return boot_get_setup_fit(images, arch, setup_start, setup_len); +#else + return -ENOENT; +#endif +} + +#if IMAGE_ENABLE_FIT +#if defined(CONFIG_FPGA) +int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len) +{ + ulong tmp_img_addr, img_data, img_len; + void *buf; + int conf_noffset; + int fit_img_result; + const char *uname, *name; + int err; + int devnum = 0; /* TODO support multi fpga platforms */ + + /* Check to see if the images struct has a FIT configuration */ + if (!genimg_has_config(images)) { + debug("## FIT configuration was not specified\n"); + return 0; + } + + /* + * Obtain the os FIT header from the images struct + */ + tmp_img_addr = map_to_sysmem(images->fit_hdr_os); + buf = map_sysmem(tmp_img_addr, 0); + /* + * Check image type. For FIT images get FIT node + * and attempt to locate a generic binary. + */ + switch (genimg_get_format(buf)) { + case IMAGE_FORMAT_FIT: + conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg); + + uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0, + NULL); + if (!uname) { + debug("## FPGA image is not specified\n"); + return 0; + } + fit_img_result = fit_image_load(images, + tmp_img_addr, + (const char **)&uname, + &(images->fit_uname_cfg), + arch, + IH_TYPE_FPGA, + BOOTSTAGE_ID_FPGA_INIT, + FIT_LOAD_OPTIONAL_NON_ZERO, + &img_data, &img_len); + + debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n", + uname, img_data, img_len); + + if (fit_img_result < 0) { + /* Something went wrong! */ + return fit_img_result; + } + + if (!fpga_is_partial_data(devnum, img_len)) { + name = "full"; + err = fpga_loadbitstream(devnum, (char *)img_data, + img_len, BIT_FULL); + if (err) + err = fpga_load(devnum, (const void *)img_data, + img_len, BIT_FULL); + } else { + name = "partial"; + err = fpga_loadbitstream(devnum, (char *)img_data, + img_len, BIT_PARTIAL); + if (err) + err = fpga_load(devnum, (const void *)img_data, + img_len, BIT_PARTIAL); + } + + if (err) + return err; + + printf(" Programming %s bitstream... OK\n", name); + break; + default: + printf("The given image format is not supported (corrupt?)\n"); + return 1; + } + + return 0; +} +#endif + +static void fit_loadable_process(uint8_t img_type, + ulong img_data, + ulong img_len) +{ + int i; + const unsigned int count = + ll_entry_count(struct fit_loadable_tbl, fit_loadable); + struct fit_loadable_tbl *fit_loadable_handler = + ll_entry_start(struct fit_loadable_tbl, fit_loadable); + /* For each loadable handler */ + for (i = 0; i < count; i++, fit_loadable_handler++) + /* matching this type */ + if (fit_loadable_handler->type == img_type) + /* call that handler with this image data */ + fit_loadable_handler->handler(img_data, img_len); +} + +int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, + uint8_t arch, const ulong *ld_start, ulong * const ld_len) +{ + /* + * These variables are used to hold the current image location + * in system memory. + */ + ulong tmp_img_addr; + /* + * These two variables are requirements for fit_image_load, but + * their values are not used + */ + ulong img_data, img_len; + void *buf; + int loadables_index; + int conf_noffset; + int fit_img_result; + const char *uname; + uint8_t img_type; + + /* Check to see if the images struct has a FIT configuration */ + if (!genimg_has_config(images)) { + debug("## FIT configuration was not specified\n"); + return 0; + } + + /* + * Obtain the os FIT header from the images struct + */ + tmp_img_addr = map_to_sysmem(images->fit_hdr_os); + buf = map_sysmem(tmp_img_addr, 0); + /* + * Check image type. For FIT images get FIT node + * and attempt to locate a generic binary. + */ + switch (genimg_get_format(buf)) { + case IMAGE_FORMAT_FIT: + conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg); + + for (loadables_index = 0; + uname = fdt_stringlist_get(buf, conf_noffset, + FIT_LOADABLE_PROP, loadables_index, + NULL), uname; + loadables_index++) + { + fit_img_result = fit_image_load(images, + tmp_img_addr, + &uname, + &(images->fit_uname_cfg), arch, + IH_TYPE_LOADABLE, + BOOTSTAGE_ID_FIT_LOADABLE_START, + FIT_LOAD_OPTIONAL_NON_ZERO, + &img_data, &img_len); + if (fit_img_result < 0) { + /* Something went wrong! */ + return fit_img_result; + } + + fit_img_result = fit_image_get_node(buf, uname); + if (fit_img_result < 0) { + /* Something went wrong! */ + return fit_img_result; + } + fit_img_result = fit_image_get_type(buf, + fit_img_result, + &img_type); + if (fit_img_result < 0) { + /* Something went wrong! */ + return fit_img_result; + } + + fit_loadable_process(img_type, img_data, img_len); + } + break; + default: + printf("The given image format is not supported (corrupt?)\n"); + return 1; + } + + return 0; +} +#endif + +#ifdef CONFIG_SYS_BOOT_GET_CMDLINE +/** + * boot_get_cmdline - allocate and initialize kernel cmdline + * @lmb: pointer to lmb handle, will be used for memory mgmt + * @cmd_start: pointer to a ulong variable, will hold cmdline start + * @cmd_end: pointer to a ulong variable, will hold cmdline end + * + * boot_get_cmdline() allocates space for kernel command line below + * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment + * variable is present its contents is copied to allocated kernel + * command line. + * + * returns: + * 0 - success + * -1 - failure + */ +int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) +{ + char *cmdline; + char *s; + + cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf, + env_get_bootm_mapsize() + env_get_bootm_low()); + + if (cmdline == NULL) + return -1; + + s = env_get("bootargs"); + if (!s) + s = ""; + + strcpy(cmdline, s); + + *cmd_start = (ulong) & cmdline[0]; + *cmd_end = *cmd_start + strlen(cmdline); + + debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end); + + return 0; +} +#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */ + +#ifdef CONFIG_SYS_BOOT_GET_KBD +/** + * boot_get_kbd - allocate and initialize kernel copy of board info + * @lmb: pointer to lmb handle, will be used for memory mgmt + * @kbd: double pointer to board info data + * + * boot_get_kbd() allocates space for kernel copy of board info data below + * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized + * with the current u-boot board info data. + * + * returns: + * 0 - success + * -1 - failure + */ +int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd) +{ + *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb, + sizeof(struct bd_info), + 0xf, + env_get_bootm_mapsize() + env_get_bootm_low()); + if (*kbd == NULL) + return -1; + + **kbd = *(gd->bd); + + debug("## kernel board info at 0x%08lx\n", (ulong)*kbd); + +#if defined(DEBUG) && defined(CONFIG_CMD_BDI) + do_bdinfo(NULL, 0, 0, NULL); +#endif + + return 0; +} +#endif /* CONFIG_SYS_BOOT_GET_KBD */ + +#ifdef CONFIG_LMB +int image_setup_linux(bootm_headers_t *images) +{ + ulong of_size = images->ft_len; + char **of_flat_tree = &images->ft_addr; + struct lmb *lmb = &images->lmb; + int ret; + + if (IMAGE_ENABLE_OF_LIBFDT) + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + + if (IMAGE_BOOT_GET_CMDLINE) { + ret = boot_get_cmdline(lmb, &images->cmdline_start, + &images->cmdline_end); + if (ret) { + puts("ERROR with allocation of cmdline\n"); + return ret; + } + } + + if (IMAGE_ENABLE_OF_LIBFDT) { + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); + if (ret) + return ret; + } + + if (IMAGE_ENABLE_OF_LIBFDT && of_size) { + ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb); + if (ret) + return ret; + } + + return 0; +} +#endif /* CONFIG_LMB */ diff --git a/common/image.c b/common/image.c index e16d433b91..ed7f188b59 100644 --- a/common/image.c +++ b/common/image.c @@ -8,15 +8,11 @@ #ifndef USE_HOSTCC #include -#include -#include #include #include #include #include -#include #include -#include #ifdef CONFIG_SHOW_BOOT_PROGRESS #include @@ -24,14 +20,9 @@ #include -#include -#include - #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT #include #include -#include -#include #endif #include @@ -47,11 +38,6 @@ extern int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) -static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, - int verify); -#endif - /* Set this if we have less than 4 MB of malloc() space */ #if CONFIG_SYS_MALLOC_LEN < (4096 * 1024) #define CONSERVE_MEMORY true @@ -63,7 +49,6 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #include "mkimage.h" #include #include -#include #ifndef __maybe_unused # define __maybe_unused /* unimplemented */ @@ -76,6 +61,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #include #include #include +#include #include #include #include @@ -86,10 +72,6 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, #include #include -#ifndef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE 512 -#endif - static const table_entry_t uimage_arch[] = { { IH_ARCH_INVALID, "invalid", "Invalid ARCH", }, { IH_ARCH_ALPHA, "alpha", "Alpha", }, @@ -546,180 +528,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, return 0; } -#ifndef USE_HOSTCC -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) -/** - * image_get_ramdisk - get and verify ramdisk image - * @rd_addr: ramdisk image start address - * @arch: expected ramdisk architecture - * @verify: checksum verification flag - * - * image_get_ramdisk() returns a pointer to the verified ramdisk image - * header. Routine receives image start address and expected architecture - * flag. Verification done covers data and header integrity and os/type/arch - * fields checking. - * - * returns: - * pointer to a ramdisk image header, if image was found and valid - * otherwise, return NULL - */ -static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, - int verify) -{ - const image_header_t *rd_hdr = (const image_header_t *)rd_addr; - - if (!image_check_magic(rd_hdr)) { - puts("Bad Magic Number\n"); - bootstage_error(BOOTSTAGE_ID_RD_MAGIC); - return NULL; - } - - if (!image_check_hcrc(rd_hdr)) { - puts("Bad Header Checksum\n"); - bootstage_error(BOOTSTAGE_ID_RD_HDR_CHECKSUM); - return NULL; - } - - bootstage_mark(BOOTSTAGE_ID_RD_MAGIC); - image_print_contents(rd_hdr); - - if (verify) { - puts(" Verifying Checksum ... "); - if (!image_check_dcrc(rd_hdr)) { - puts("Bad Data CRC\n"); - bootstage_error(BOOTSTAGE_ID_RD_CHECKSUM); - return NULL; - } - puts("OK\n"); - } - - bootstage_mark(BOOTSTAGE_ID_RD_HDR_CHECKSUM); - - if (!image_check_os(rd_hdr, IH_OS_LINUX) || - !image_check_arch(rd_hdr, arch) || - !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) { - printf("No Linux %s Ramdisk Image\n", - genimg_get_arch_name(arch)); - bootstage_error(BOOTSTAGE_ID_RAMDISK); - return NULL; - } - - return rd_hdr; -} -#endif -#endif /* !USE_HOSTCC */ - -/*****************************************************************************/ -/* Shared dual-format routines */ -/*****************************************************************************/ -#ifndef USE_HOSTCC -ulong image_load_addr = CONFIG_SYS_LOAD_ADDR; /* Default Load Address */ -ulong image_save_addr; /* Default Save Address */ -ulong image_save_size; /* Default Save Size (in bytes) */ - -static int on_loadaddr(const char *name, const char *value, enum env_op op, - int flags) -{ - switch (op) { - case env_op_create: - case env_op_overwrite: - image_load_addr = hextoul(value, NULL); - break; - default: - break; - } - - return 0; -} -U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr); - -ulong env_get_bootm_low(void) -{ - char *s = env_get("bootm_low"); - if (s) { - ulong tmp = hextoul(s, NULL); - return tmp; - } - -#if defined(CONFIG_SYS_SDRAM_BASE) - return CONFIG_SYS_SDRAM_BASE; -#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) - return gd->bd->bi_dram[0].start; -#else - return 0; -#endif -} - -phys_size_t env_get_bootm_size(void) -{ - phys_size_t tmp, size; - phys_addr_t start; - char *s = env_get("bootm_size"); - if (s) { - tmp = (phys_size_t)simple_strtoull(s, NULL, 16); - return tmp; - } - - start = gd->ram_base; - size = gd->ram_size; - - if (start + size > gd->ram_top) - size = gd->ram_top - start; - - s = env_get("bootm_low"); - if (s) - tmp = (phys_size_t)simple_strtoull(s, NULL, 16); - else - tmp = start; - - return size - (tmp - start); -} - -phys_size_t env_get_bootm_mapsize(void) -{ - phys_size_t tmp; - char *s = env_get("bootm_mapsize"); - if (s) { - tmp = (phys_size_t)simple_strtoull(s, NULL, 16); - return tmp; - } - -#if defined(CONFIG_SYS_BOOTMAPSZ) - return CONFIG_SYS_BOOTMAPSZ; -#else - return env_get_bootm_size(); -#endif -} - -void memmove_wd(void *to, void *from, size_t len, ulong chunksz) -{ - if (to == from) - return; - -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - if (to > from) { - from += len; - to += len; - } - while (len > 0) { - size_t tail = (len > chunksz) ? chunksz : len; - WATCHDOG_RESET(); - if (to > from) { - to -= tail; - from -= tail; - } - memmove(to, from, tail); - if (to < from) { - to += tail; - from += tail; - } - len -= tail; - } -#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ - memmove(to, from, len); -#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ -} -#else /* USE_HOSTCC */ +#ifdef USE_HOSTCC void memmove_wd(void *to, void *from, size_t len, ulong chunksz) { memmove(to, from, len); @@ -982,733 +791,3 @@ int genimg_get_comp_id(const char *name) { return (get_table_entry_id(uimage_comp, "Compression", name)); } - -#ifndef USE_HOSTCC -/** - * genimg_get_kernel_addr_fit - get the real kernel address and return 2 - * FIT strings - * @img_addr: a string might contain real image address - * @fit_uname_config: double pointer to a char, will hold pointer to a - * configuration unit name - * @fit_uname_kernel: double pointer to a char, will hold pointer to a subimage - * name - * - * genimg_get_kernel_addr_fit get the real kernel start address from a string - * which is normally the first argv of bootm/bootz - * - * returns: - * kernel start address - */ -ulong genimg_get_kernel_addr_fit(char * const img_addr, - const char **fit_uname_config, - const char **fit_uname_kernel) -{ - ulong kernel_addr; - - /* find out kernel image address */ - if (!img_addr) { - kernel_addr = image_load_addr; - debug("* kernel: default image load address = 0x%08lx\n", - image_load_addr); -#if CONFIG_IS_ENABLED(FIT) - } else if (fit_parse_conf(img_addr, image_load_addr, &kernel_addr, - fit_uname_config)) { - debug("* kernel: config '%s' from image at 0x%08lx\n", - *fit_uname_config, kernel_addr); - } else if (fit_parse_subimage(img_addr, image_load_addr, &kernel_addr, - fit_uname_kernel)) { - debug("* kernel: subimage '%s' from image at 0x%08lx\n", - *fit_uname_kernel, kernel_addr); -#endif - } else { - kernel_addr = hextoul(img_addr, NULL); - debug("* kernel: cmdline image address = 0x%08lx\n", - kernel_addr); - } - - return kernel_addr; -} - -/** - * genimg_get_kernel_addr() is the simple version of - * genimg_get_kernel_addr_fit(). It ignores those return FIT strings - */ -ulong genimg_get_kernel_addr(char * const img_addr) -{ - const char *fit_uname_config = NULL; - const char *fit_uname_kernel = NULL; - - return genimg_get_kernel_addr_fit(img_addr, &fit_uname_config, - &fit_uname_kernel); -} - -/** - * genimg_get_format - get image format type - * @img_addr: image start address - * - * genimg_get_format() checks whether provided address points to a valid - * legacy or FIT image. - * - * New uImage format and FDT blob are based on a libfdt. FDT blob - * may be passed directly or embedded in a FIT image. In both situations - * genimg_get_format() must be able to dectect libfdt header. - * - * returns: - * image format type or IMAGE_FORMAT_INVALID if no image is present - */ -int genimg_get_format(const void *img_addr) -{ -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - const image_header_t *hdr; - - hdr = (const image_header_t *)img_addr; - if (image_check_magic(hdr)) - return IMAGE_FORMAT_LEGACY; -#endif -#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT - if (fdt_check_header(img_addr) == 0) - return IMAGE_FORMAT_FIT; -#endif -#ifdef CONFIG_ANDROID_BOOT_IMAGE - if (android_image_check_header(img_addr) == 0) - return IMAGE_FORMAT_ANDROID; -#endif - - return IMAGE_FORMAT_INVALID; -} - -/** - * fit_has_config - check if there is a valid FIT configuration - * @images: pointer to the bootm command headers structure - * - * fit_has_config() checks if there is a FIT configuration in use - * (if FTI support is present). - * - * returns: - * 0, no FIT support or no configuration found - * 1, configuration found - */ -int genimg_has_config(bootm_headers_t *images) -{ -#if IMAGE_ENABLE_FIT - if (images->fit_uname_cfg) - return 1; -#endif - return 0; -} - -/** - * boot_get_ramdisk - main ramdisk handling routine - * @argc: command argument count - * @argv: command argument list - * @images: pointer to the bootm images structure - * @arch: expected ramdisk architecture - * @rd_start: pointer to a ulong variable, will hold ramdisk start address - * @rd_end: pointer to a ulong variable, will hold ramdisk end - * - * boot_get_ramdisk() is responsible for finding a valid ramdisk image. - * Curently supported are the following ramdisk sources: - * - multicomponent kernel/ramdisk image, - * - commandline provided address of decicated ramdisk image. - * - * returns: - * 0, if ramdisk image was found and valid, or skiped - * rd_start and rd_end are set to ramdisk start/end addresses if - * ramdisk image is found and valid - * - * 1, if ramdisk image is found but corrupted, or invalid - * rd_start and rd_end are set to 0 if no ramdisk exists - */ -int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, - uint8_t arch, ulong *rd_start, ulong *rd_end) -{ - ulong rd_addr, rd_load; - ulong rd_data, rd_len; -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - const image_header_t *rd_hdr; -#endif - void *buf; -#ifdef CONFIG_SUPPORT_RAW_INITRD - char *end; -#endif -#if IMAGE_ENABLE_FIT - const char *fit_uname_config = images->fit_uname_cfg; - const char *fit_uname_ramdisk = NULL; - ulong default_addr; - int rd_noffset; -#endif - const char *select = NULL; - - *rd_start = 0; - *rd_end = 0; - -#ifdef CONFIG_ANDROID_BOOT_IMAGE - /* - * Look for an Android boot image. - */ - buf = map_sysmem(images->os.start, 0); - if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) - select = (argc == 0) ? env_get("loadaddr") : argv[0]; -#endif - - if (argc >= 2) - select = argv[1]; - - /* - * Look for a '-' which indicates to ignore the - * ramdisk argument - */ - if (select && strcmp(select, "-") == 0) { - debug("## Skipping init Ramdisk\n"); - rd_len = rd_data = 0; - } else if (select || genimg_has_config(images)) { -#if IMAGE_ENABLE_FIT - if (select) { - /* - * If the init ramdisk comes from the FIT image and - * the FIT image address is omitted in the command - * line argument, try to use os FIT image address or - * default load address. - */ - if (images->fit_uname_os) - default_addr = (ulong)images->fit_hdr_os; - else - default_addr = image_load_addr; - - if (fit_parse_conf(select, default_addr, - &rd_addr, &fit_uname_config)) { - debug("* ramdisk: config '%s' from image at " - "0x%08lx\n", - fit_uname_config, rd_addr); - } else if (fit_parse_subimage(select, default_addr, - &rd_addr, &fit_uname_ramdisk)) { - debug("* ramdisk: subimage '%s' from image at " - "0x%08lx\n", - fit_uname_ramdisk, rd_addr); - } else -#endif - { - rd_addr = hextoul(select, NULL); - debug("* ramdisk: cmdline image address = " - "0x%08lx\n", - rd_addr); - } -#if IMAGE_ENABLE_FIT - } else { - /* use FIT configuration provided in first bootm - * command argument. If the property is not defined, - * quit silently. - */ - rd_addr = map_to_sysmem(images->fit_hdr_os); - rd_noffset = fit_get_node_from_config(images, - FIT_RAMDISK_PROP, rd_addr); - if (rd_noffset == -ENOENT) - return 0; - else if (rd_noffset < 0) - return 1; - } -#endif - - /* - * Check if there is an initrd image at the - * address provided in the second bootm argument - * check image type, for FIT images get FIT node. - */ - buf = map_sysmem(rd_addr, 0); - switch (genimg_get_format(buf)) { -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - case IMAGE_FORMAT_LEGACY: - printf("## Loading init Ramdisk from Legacy " - "Image at %08lx ...\n", rd_addr); - - bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK); - rd_hdr = image_get_ramdisk(rd_addr, arch, - images->verify); - - if (rd_hdr == NULL) - return 1; - - rd_data = image_get_data(rd_hdr); - rd_len = image_get_data_size(rd_hdr); - rd_load = image_get_load(rd_hdr); - break; -#endif -#if IMAGE_ENABLE_FIT - case IMAGE_FORMAT_FIT: - rd_noffset = fit_image_load(images, - rd_addr, &fit_uname_ramdisk, - &fit_uname_config, arch, - IH_TYPE_RAMDISK, - BOOTSTAGE_ID_FIT_RD_START, - FIT_LOAD_OPTIONAL_NON_ZERO, - &rd_data, &rd_len); - if (rd_noffset < 0) - return 1; - - images->fit_hdr_rd = map_sysmem(rd_addr, 0); - images->fit_uname_rd = fit_uname_ramdisk; - images->fit_noffset_rd = rd_noffset; - break; -#endif -#ifdef CONFIG_ANDROID_BOOT_IMAGE - case IMAGE_FORMAT_ANDROID: - android_image_get_ramdisk((void *)images->os.start, - &rd_data, &rd_len); - break; -#endif - default: -#ifdef CONFIG_SUPPORT_RAW_INITRD - end = NULL; - if (select) - end = strchr(select, ':'); - if (end) { - rd_len = hextoul(++end, NULL); - rd_data = rd_addr; - } else -#endif - { - puts("Wrong Ramdisk Image Format\n"); - rd_data = rd_len = rd_load = 0; - return 1; - } - } - } else if (images->legacy_hdr_valid && - image_check_type(&images->legacy_hdr_os_copy, - IH_TYPE_MULTI)) { - - /* - * Now check if we have a legacy mult-component image, - * get second entry data start address and len. - */ - bootstage_mark(BOOTSTAGE_ID_RAMDISK); - printf("## Loading init Ramdisk from multi component " - "Legacy Image at %08lx ...\n", - (ulong)images->legacy_hdr_os); - - image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len); - } else { - /* - * no initrd image - */ - bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK); - rd_len = rd_data = 0; - } - - if (!rd_data) { - debug("## No init Ramdisk\n"); - } else { - *rd_start = rd_data; - *rd_end = rd_data + rd_len; - } - debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n", - *rd_start, *rd_end); - - return 0; -} - -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH -/** - * boot_ramdisk_high - relocate init ramdisk - * @lmb: pointer to lmb handle, will be used for memory mgmt - * @rd_data: ramdisk data start address - * @rd_len: ramdisk data length - * @initrd_start: pointer to a ulong variable, will hold final init ramdisk - * start address (after possible relocation) - * @initrd_end: pointer to a ulong variable, will hold final init ramdisk - * end address (after possible relocation) - * - * boot_ramdisk_high() takes a relocation hint from "initrd_high" environment - * variable and if requested ramdisk data is moved to a specified location. - * - * Initrd_start and initrd_end are set to final (after relocation) ramdisk - * start/end addresses if ramdisk image start and len were provided, - * otherwise set initrd_start and initrd_end set to zeros. - * - * returns: - * 0 - success - * -1 - failure - */ -int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, - ulong *initrd_start, ulong *initrd_end) -{ - char *s; - ulong initrd_high; - int initrd_copy_to_ram = 1; - - s = env_get("initrd_high"); - if (s) { - /* a value of "no" or a similar string will act like 0, - * turning the "load high" feature off. This is intentional. - */ - initrd_high = hextoul(s, NULL); - if (initrd_high == ~0) - initrd_copy_to_ram = 0; - } else { - initrd_high = env_get_bootm_mapsize() + env_get_bootm_low(); - } - - - debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n", - initrd_high, initrd_copy_to_ram); - - if (rd_data) { - if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ - debug(" in-place initrd\n"); - *initrd_start = rd_data; - *initrd_end = rd_data + rd_len; - lmb_reserve(lmb, rd_data, rd_len); - } else { - if (initrd_high) - *initrd_start = (ulong)lmb_alloc_base(lmb, - rd_len, 0x1000, initrd_high); - else - *initrd_start = (ulong)lmb_alloc(lmb, rd_len, - 0x1000); - - if (*initrd_start == 0) { - puts("ramdisk - allocation error\n"); - goto error; - } - bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK); - - *initrd_end = *initrd_start + rd_len; - printf(" Loading Ramdisk to %08lx, end %08lx ... ", - *initrd_start, *initrd_end); - - memmove_wd((void *)*initrd_start, - (void *)rd_data, rd_len, CHUNKSZ); - -#ifdef CONFIG_MP - /* - * Ensure the image is flushed to memory to handle - * AMP boot scenarios in which we might not be - * HW cache coherent - */ - flush_cache((unsigned long)*initrd_start, - ALIGN(rd_len, ARCH_DMA_MINALIGN)); -#endif - puts("OK\n"); - } - } else { - *initrd_start = 0; - *initrd_end = 0; - } - debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n", - *initrd_start, *initrd_end); - - return 0; - -error: - return -1; -} -#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ - -int boot_get_setup(bootm_headers_t *images, uint8_t arch, - ulong *setup_start, ulong *setup_len) -{ -#if IMAGE_ENABLE_FIT - return boot_get_setup_fit(images, arch, setup_start, setup_len); -#else - return -ENOENT; -#endif -} - -#if IMAGE_ENABLE_FIT -#if defined(CONFIG_FPGA) -int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, - uint8_t arch, const ulong *ld_start, ulong * const ld_len) -{ - ulong tmp_img_addr, img_data, img_len; - void *buf; - int conf_noffset; - int fit_img_result; - const char *uname, *name; - int err; - int devnum = 0; /* TODO support multi fpga platforms */ - - /* Check to see if the images struct has a FIT configuration */ - if (!genimg_has_config(images)) { - debug("## FIT configuration was not specified\n"); - return 0; - } - - /* - * Obtain the os FIT header from the images struct - */ - tmp_img_addr = map_to_sysmem(images->fit_hdr_os); - buf = map_sysmem(tmp_img_addr, 0); - /* - * Check image type. For FIT images get FIT node - * and attempt to locate a generic binary. - */ - switch (genimg_get_format(buf)) { - case IMAGE_FORMAT_FIT: - conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg); - - uname = fdt_stringlist_get(buf, conf_noffset, FIT_FPGA_PROP, 0, - NULL); - if (!uname) { - debug("## FPGA image is not specified\n"); - return 0; - } - fit_img_result = fit_image_load(images, - tmp_img_addr, - (const char **)&uname, - &(images->fit_uname_cfg), - arch, - IH_TYPE_FPGA, - BOOTSTAGE_ID_FPGA_INIT, - FIT_LOAD_OPTIONAL_NON_ZERO, - &img_data, &img_len); - - debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n", - uname, img_data, img_len); - - if (fit_img_result < 0) { - /* Something went wrong! */ - return fit_img_result; - } - - if (!fpga_is_partial_data(devnum, img_len)) { - name = "full"; - err = fpga_loadbitstream(devnum, (char *)img_data, - img_len, BIT_FULL); - if (err) - err = fpga_load(devnum, (const void *)img_data, - img_len, BIT_FULL); - } else { - name = "partial"; - err = fpga_loadbitstream(devnum, (char *)img_data, - img_len, BIT_PARTIAL); - if (err) - err = fpga_load(devnum, (const void *)img_data, - img_len, BIT_PARTIAL); - } - - if (err) - return err; - - printf(" Programming %s bitstream... OK\n", name); - break; - default: - printf("The given image format is not supported (corrupt?)\n"); - return 1; - } - - return 0; -} -#endif - -static void fit_loadable_process(uint8_t img_type, - ulong img_data, - ulong img_len) -{ - int i; - const unsigned int count = - ll_entry_count(struct fit_loadable_tbl, fit_loadable); - struct fit_loadable_tbl *fit_loadable_handler = - ll_entry_start(struct fit_loadable_tbl, fit_loadable); - /* For each loadable handler */ - for (i = 0; i < count; i++, fit_loadable_handler++) - /* matching this type */ - if (fit_loadable_handler->type == img_type) - /* call that handler with this image data */ - fit_loadable_handler->handler(img_data, img_len); -} - -int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, - uint8_t arch, const ulong *ld_start, ulong * const ld_len) -{ - /* - * These variables are used to hold the current image location - * in system memory. - */ - ulong tmp_img_addr; - /* - * These two variables are requirements for fit_image_load, but - * their values are not used - */ - ulong img_data, img_len; - void *buf; - int loadables_index; - int conf_noffset; - int fit_img_result; - const char *uname; - uint8_t img_type; - - /* Check to see if the images struct has a FIT configuration */ - if (!genimg_has_config(images)) { - debug("## FIT configuration was not specified\n"); - return 0; - } - - /* - * Obtain the os FIT header from the images struct - */ - tmp_img_addr = map_to_sysmem(images->fit_hdr_os); - buf = map_sysmem(tmp_img_addr, 0); - /* - * Check image type. For FIT images get FIT node - * and attempt to locate a generic binary. - */ - switch (genimg_get_format(buf)) { - case IMAGE_FORMAT_FIT: - conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg); - - for (loadables_index = 0; - uname = fdt_stringlist_get(buf, conf_noffset, - FIT_LOADABLE_PROP, loadables_index, - NULL), uname; - loadables_index++) - { - fit_img_result = fit_image_load(images, - tmp_img_addr, - &uname, - &(images->fit_uname_cfg), arch, - IH_TYPE_LOADABLE, - BOOTSTAGE_ID_FIT_LOADABLE_START, - FIT_LOAD_OPTIONAL_NON_ZERO, - &img_data, &img_len); - if (fit_img_result < 0) { - /* Something went wrong! */ - return fit_img_result; - } - - fit_img_result = fit_image_get_node(buf, uname); - if (fit_img_result < 0) { - /* Something went wrong! */ - return fit_img_result; - } - fit_img_result = fit_image_get_type(buf, - fit_img_result, - &img_type); - if (fit_img_result < 0) { - /* Something went wrong! */ - return fit_img_result; - } - - fit_loadable_process(img_type, img_data, img_len); - } - break; - default: - printf("The given image format is not supported (corrupt?)\n"); - return 1; - } - - return 0; -} -#endif - -#ifdef CONFIG_SYS_BOOT_GET_CMDLINE -/** - * boot_get_cmdline - allocate and initialize kernel cmdline - * @lmb: pointer to lmb handle, will be used for memory mgmt - * @cmd_start: pointer to a ulong variable, will hold cmdline start - * @cmd_end: pointer to a ulong variable, will hold cmdline end - * - * boot_get_cmdline() allocates space for kernel command line below - * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment - * variable is present its contents is copied to allocated kernel - * command line. - * - * returns: - * 0 - success - * -1 - failure - */ -int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) -{ - char *cmdline; - char *s; - - cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf, - env_get_bootm_mapsize() + env_get_bootm_low()); - - if (cmdline == NULL) - return -1; - - s = env_get("bootargs"); - if (!s) - s = ""; - - strcpy(cmdline, s); - - *cmd_start = (ulong) & cmdline[0]; - *cmd_end = *cmd_start + strlen(cmdline); - - debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end); - - return 0; -} -#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */ - -#ifdef CONFIG_SYS_BOOT_GET_KBD -/** - * boot_get_kbd - allocate and initialize kernel copy of board info - * @lmb: pointer to lmb handle, will be used for memory mgmt - * @kbd: double pointer to board info data - * - * boot_get_kbd() allocates space for kernel copy of board info data below - * BOOTMAPSZ + env_get_bootm_low() address and kernel board info is initialized - * with the current u-boot board info data. - * - * returns: - * 0 - success - * -1 - failure - */ -int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd) -{ - *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb, - sizeof(struct bd_info), - 0xf, - env_get_bootm_mapsize() + env_get_bootm_low()); - if (*kbd == NULL) - return -1; - - **kbd = *(gd->bd); - - debug("## kernel board info at 0x%08lx\n", (ulong)*kbd); - -#if defined(DEBUG) && defined(CONFIG_CMD_BDI) - do_bdinfo(NULL, 0, 0, NULL); -#endif - - return 0; -} -#endif /* CONFIG_SYS_BOOT_GET_KBD */ - -#ifdef CONFIG_LMB -int image_setup_linux(bootm_headers_t *images) -{ - ulong of_size = images->ft_len; - char **of_flat_tree = &images->ft_addr; - struct lmb *lmb = &images->lmb; - int ret; - - if (IMAGE_ENABLE_OF_LIBFDT) - boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); - - if (IMAGE_BOOT_GET_CMDLINE) { - ret = boot_get_cmdline(lmb, &images->cmdline_start, - &images->cmdline_end); - if (ret) { - puts("ERROR with allocation of cmdline\n"); - return ret; - } - } - - if (IMAGE_ENABLE_OF_LIBFDT) { - ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); - if (ret) - return ret; - } - - if (IMAGE_ENABLE_OF_LIBFDT && of_size) { - ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb); - if (ret) - return ret; - } - - return 0; -} -#endif /* CONFIG_LMB */ -#endif /* !USE_HOSTCC */ From 3d2a47f11c1e77e79aa4f04dc787b25054822267 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:16 -0600 Subject: [PATCH 085/228] image: Fix up checkpatch warnings in image-board.c Tidy up the warnings. Signed-off-by: Simon Glass --- common/image-board.c | 142 ++++++++++++++++++++++--------------------- 1 file changed, 72 insertions(+), 70 deletions(-) diff --git a/common/image-board.c b/common/image-board.c index 63cbf5f901..835751e07c 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; * pointer to a ramdisk image header, if image was found and valid * otherwise, return NULL */ -static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, - int verify) +static const image_header_t *image_get_ramdisk(ulong rd_addr, u8 arch, + int verify) { const image_header_t *rd_hdr = (const image_header_t *)rd_addr; @@ -77,7 +77,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch, !image_check_arch(rd_hdr, arch) || !image_check_type(rd_hdr, IH_TYPE_RAMDISK)) { printf("No Linux %s Ramdisk Image\n", - genimg_get_arch_name(arch)); + genimg_get_arch_name(arch)); bootstage_error(BOOTSTAGE_ID_RAMDISK); return NULL; } @@ -94,7 +94,7 @@ ulong image_save_addr; /* Default Save Address */ ulong image_save_size; /* Default Save Size (in bytes) */ static int on_loadaddr(const char *name, const char *value, enum env_op op, - int flags) + int flags) { switch (op) { case env_op_create: @@ -112,6 +112,7 @@ U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr); ulong env_get_bootm_low(void) { char *s = env_get("bootm_low"); + if (s) { ulong tmp = hextoul(s, NULL); return tmp; @@ -131,6 +132,7 @@ phys_size_t env_get_bootm_size(void) phys_size_t tmp, size; phys_addr_t start; char *s = env_get("bootm_size"); + if (s) { tmp = (phys_size_t)simple_strtoull(s, NULL, 16); return tmp; @@ -155,6 +157,7 @@ phys_size_t env_get_bootm_mapsize(void) { phys_size_t tmp; char *s = env_get("bootm_mapsize"); + if (s) { tmp = (phys_size_t)simple_strtoull(s, NULL, 16); return tmp; @@ -179,6 +182,7 @@ void memmove_wd(void *to, void *from, size_t len, ulong chunksz) } while (len > 0) { size_t tail = (len > chunksz) ? chunksz : len; + WATCHDOG_RESET(); if (to > from) { to -= tail; @@ -212,8 +216,8 @@ void memmove_wd(void *to, void *from, size_t len, ulong chunksz) * kernel start address */ ulong genimg_get_kernel_addr_fit(char * const img_addr, - const char **fit_uname_config, - const char **fit_uname_kernel) + const char **fit_uname_config, + const char **fit_uname_kernel) { ulong kernel_addr; @@ -319,7 +323,7 @@ int genimg_has_config(bootm_headers_t *images) * @rd_end: pointer to a ulong variable, will hold ramdisk end * * boot_get_ramdisk() is responsible for finding a valid ramdisk image. - * Curently supported are the following ramdisk sources: + * Currently supported are the following ramdisk sources: * - multicomponent kernel/ramdisk image, * - commandline provided address of decicated ramdisk image. * @@ -332,7 +336,7 @@ int genimg_has_config(bootm_headers_t *images) * rd_start and rd_end are set to 0 if no ramdisk exists */ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, - uint8_t arch, ulong *rd_start, ulong *rd_end) + u8 arch, ulong *rd_start, ulong *rd_end) { ulong rd_addr, rd_load; ulong rd_data, rd_len; @@ -372,7 +376,8 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, */ if (select && strcmp(select, "-") == 0) { debug("## Skipping init Ramdisk\n"); - rd_len = rd_data = 0; + rd_len = 0; + rd_data = 0; } else if (select || genimg_has_config(images)) { #if IMAGE_ENABLE_FIT if (select) { @@ -389,21 +394,19 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, if (fit_parse_conf(select, default_addr, &rd_addr, &fit_uname_config)) { - debug("* ramdisk: config '%s' from image at " - "0x%08lx\n", - fit_uname_config, rd_addr); + debug("* ramdisk: config '%s' from image at 0x%08lx\n", + fit_uname_config, rd_addr); } else if (fit_parse_subimage(select, default_addr, - &rd_addr, &fit_uname_ramdisk)) { - debug("* ramdisk: subimage '%s' from image at " - "0x%08lx\n", - fit_uname_ramdisk, rd_addr); + &rd_addr, + &fit_uname_ramdisk)) { + debug("* ramdisk: subimage '%s' from image at 0x%08lx\n", + fit_uname_ramdisk, rd_addr); } else #endif { rd_addr = hextoul(select, NULL); - debug("* ramdisk: cmdline image address = " - "0x%08lx\n", - rd_addr); + debug("* ramdisk: cmdline image address = 0x%08lx\n", + rd_addr); } #if IMAGE_ENABLE_FIT } else { @@ -413,7 +416,8 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, */ rd_addr = map_to_sysmem(images->fit_hdr_os); rd_noffset = fit_get_node_from_config(images, - FIT_RAMDISK_PROP, rd_addr); + FIT_RAMDISK_PROP, + rd_addr); if (rd_noffset == -ENOENT) return 0; else if (rd_noffset < 0) @@ -430,14 +434,14 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, switch (genimg_get_format(buf)) { #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) case IMAGE_FORMAT_LEGACY: - printf("## Loading init Ramdisk from Legacy " - "Image at %08lx ...\n", rd_addr); + printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n", + rd_addr); bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK); rd_hdr = image_get_ramdisk(rd_addr, arch, - images->verify); + images->verify); - if (rd_hdr == NULL) + if (!rd_hdr) return 1; rd_data = image_get_data(rd_hdr); @@ -448,12 +452,12 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, #if IMAGE_ENABLE_FIT case IMAGE_FORMAT_FIT: rd_noffset = fit_image_load(images, - rd_addr, &fit_uname_ramdisk, - &fit_uname_config, arch, - IH_TYPE_RAMDISK, - BOOTSTAGE_ID_FIT_RD_START, - FIT_LOAD_OPTIONAL_NON_ZERO, - &rd_data, &rd_len); + rd_addr, &fit_uname_ramdisk, + &fit_uname_config, arch, + IH_TYPE_RAMDISK, + BOOTSTAGE_ID_FIT_RD_START, + FIT_LOAD_OPTIONAL_NON_ZERO, + &rd_data, &rd_len); if (rd_noffset < 0) return 1; @@ -465,7 +469,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, #ifdef CONFIG_ANDROID_BOOT_IMAGE case IMAGE_FORMAT_ANDROID: android_image_get_ramdisk((void *)images->os.start, - &rd_data, &rd_len); + &rd_data, &rd_len); break; #endif default: @@ -480,22 +484,22 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, #endif { puts("Wrong Ramdisk Image Format\n"); - rd_data = rd_len = rd_load = 0; + rd_data = 0; + rd_len = 0; + rd_load = 0; return 1; } } } else if (images->legacy_hdr_valid && image_check_type(&images->legacy_hdr_os_copy, - IH_TYPE_MULTI)) { - + IH_TYPE_MULTI)) { /* * Now check if we have a legacy mult-component image, * get second entry data start address and len. */ bootstage_mark(BOOTSTAGE_ID_RAMDISK); - printf("## Loading init Ramdisk from multi component " - "Legacy Image at %08lx ...\n", - (ulong)images->legacy_hdr_os); + printf("## Loading init Ramdisk from multi component Legacy Image at %08lx ...\n", + (ulong)images->legacy_hdr_os); image_multi_getimg(images->legacy_hdr_os, 1, &rd_data, &rd_len); } else { @@ -503,7 +507,8 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, * no initrd image */ bootstage_mark(BOOTSTAGE_ID_NO_RAMDISK); - rd_len = rd_data = 0; + rd_len = 0; + rd_data = 0; } if (!rd_data) { @@ -513,7 +518,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, *rd_end = rd_data + rd_len; } debug(" ramdisk start = 0x%08lx, ramdisk end = 0x%08lx\n", - *rd_start, *rd_end); + *rd_start, *rd_end); return 0; } @@ -541,7 +546,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, * -1 - failure */ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, - ulong *initrd_start, ulong *initrd_end) + ulong *initrd_start, ulong *initrd_end) { char *s; ulong initrd_high; @@ -559,9 +564,8 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, initrd_high = env_get_bootm_mapsize() + env_get_bootm_low(); } - debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n", - initrd_high, initrd_copy_to_ram); + initrd_high, initrd_copy_to_ram); if (rd_data) { if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ @@ -585,10 +589,10 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, *initrd_end = *initrd_start + rd_len; printf(" Loading Ramdisk to %08lx, end %08lx ... ", - *initrd_start, *initrd_end); + *initrd_start, *initrd_end); memmove_wd((void *)*initrd_start, - (void *)rd_data, rd_len, CHUNKSZ); + (void *)rd_data, rd_len, CHUNKSZ); #ifdef CONFIG_MP /* @@ -606,7 +610,7 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, *initrd_end = 0; } debug(" ramdisk load start = 0x%08lx, ramdisk load end = 0x%08lx\n", - *initrd_start, *initrd_end); + *initrd_start, *initrd_end); return 0; @@ -615,7 +619,7 @@ error: } #endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ -int boot_get_setup(bootm_headers_t *images, uint8_t arch, +int boot_get_setup(bootm_headers_t *images, u8 arch, ulong *setup_start, ulong *setup_len) { #if IMAGE_ENABLE_FIT @@ -628,7 +632,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch, #if IMAGE_ENABLE_FIT #if defined(CONFIG_FPGA) int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, - uint8_t arch, const ulong *ld_start, ulong * const ld_len) + u8 arch, const ulong *ld_start, ulong * const ld_len) { ulong tmp_img_addr, img_data, img_len; void *buf; @@ -666,7 +670,7 @@ int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, fit_img_result = fit_image_load(images, tmp_img_addr, (const char **)&uname, - &(images->fit_uname_cfg), + &images->fit_uname_cfg, arch, IH_TYPE_FPGA, BOOTSTAGE_ID_FPGA_INIT, @@ -711,7 +715,7 @@ int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, } #endif -static void fit_loadable_process(uint8_t img_type, +static void fit_loadable_process(u8 img_type, ulong img_data, ulong img_len) { @@ -729,7 +733,7 @@ static void fit_loadable_process(uint8_t img_type, } int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, - uint8_t arch, const ulong *ld_start, ulong * const ld_len) + u8 arch, const ulong *ld_start, ulong * const ld_len) { /* * These variables are used to hold the current image location @@ -746,7 +750,7 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, int conf_noffset; int fit_img_result; const char *uname; - uint8_t img_type; + u8 img_type; /* Check to see if the images struct has a FIT configuration */ if (!genimg_has_config(images)) { @@ -769,18 +773,16 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, for (loadables_index = 0; uname = fdt_stringlist_get(buf, conf_noffset, - FIT_LOADABLE_PROP, loadables_index, - NULL), uname; - loadables_index++) - { - fit_img_result = fit_image_load(images, - tmp_img_addr, - &uname, - &(images->fit_uname_cfg), arch, - IH_TYPE_LOADABLE, - BOOTSTAGE_ID_FIT_LOADABLE_START, - FIT_LOAD_OPTIONAL_NON_ZERO, - &img_data, &img_len); + FIT_LOADABLE_PROP, + loadables_index, NULL), uname; + loadables_index++) { + fit_img_result = fit_image_load(images, tmp_img_addr, + &uname, + &images->fit_uname_cfg, + arch, IH_TYPE_LOADABLE, + BOOTSTAGE_ID_FIT_LOADABLE_START, + FIT_LOAD_OPTIONAL_NON_ZERO, + &img_data, &img_len); if (fit_img_result < 0) { /* Something went wrong! */ return fit_img_result; @@ -834,8 +836,7 @@ int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) cmdline = (char *)(ulong)lmb_alloc_base(lmb, CONFIG_SYS_BARGSIZE, 0xf, env_get_bootm_mapsize() + env_get_bootm_low()); - - if (cmdline == NULL) + if (!cmdline) return -1; s = env_get("bootargs"); @@ -844,7 +845,7 @@ int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) strcpy(cmdline, s); - *cmd_start = (ulong) & cmdline[0]; + *cmd_start = (ulong)cmdline; *cmd_end = *cmd_start + strlen(cmdline); debug("## cmdline at 0x%08lx ... 0x%08lx\n", *cmd_start, *cmd_end); @@ -872,11 +873,12 @@ int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd) *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb, sizeof(struct bd_info), 0xf, - env_get_bootm_mapsize() + env_get_bootm_low()); - if (*kbd == NULL) + env_get_bootm_mapsize() + + env_get_bootm_low()); + if (!*kbd) return -1; - **kbd = *(gd->bd); + **kbd = *gd->bd; debug("## kernel board info at 0x%08lx\n", (ulong)*kbd); @@ -901,7 +903,7 @@ int image_setup_linux(bootm_headers_t *images) if (IMAGE_BOOT_GET_CMDLINE) { ret = boot_get_cmdline(lmb, &images->cmdline_start, - &images->cmdline_end); + &images->cmdline_end); if (ret) { puts("ERROR with allocation of cmdline\n"); return ret; From 5d3248a688c2368be54aaa9407be30adfa994abc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:17 -0600 Subject: [PATCH 086/228] image: Split host code out into its own file To avoid having #ifdefs in a few functions which are completely different in the board and host code, create a new image-host.c file. Signed-off-by: Simon Glass --- common/image-board.c | 17 +++++++++++++++++ common/image-host.c | 27 +++++++++++++++++++++++++++ common/image.c | 38 +------------------------------------- tools/Makefile | 1 + 4 files changed, 46 insertions(+), 37 deletions(-) create mode 100644 common/image-host.c diff --git a/common/image-board.c b/common/image-board.c index 835751e07c..898f0a2b7b 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -925,3 +926,19 @@ int image_setup_linux(bootm_headers_t *images) return 0; } #endif /* CONFIG_LMB */ + +void genimg_print_size(uint32_t size) +{ + printf("%d Bytes = ", size); + print_size(size, "\n"); +} + +void genimg_print_time(time_t timestamp) +{ + struct rtc_time tm; + + rtc_to_tm(timestamp, &tm); + printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n", + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); +} diff --git a/common/image-host.c b/common/image-host.c new file mode 100644 index 0000000000..20a9521948 --- /dev/null +++ b/common/image-host.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Image code used by host tools (and not boards) + * + * (C) Copyright 2008 Semihalf + * + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include + +void memmove_wd(void *to, void *from, size_t len, ulong chunksz) +{ + memmove(to, from, len); +} + +void genimg_print_size(uint32_t size) +{ + printf("%d Bytes = %.2f KiB = %.2f MiB\n", size, (double)size / 1.024e3, + (double)size / 1.048576e6); +} + +void genimg_print_time(time_t timestamp) +{ + printf("%s", ctime(×tamp)); +} diff --git a/common/image.c b/common/image.c index ed7f188b59..3eb6a7fca1 100644 --- a/common/image.c +++ b/common/image.c @@ -18,8 +18,6 @@ #include #endif -#include - #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT #include #include @@ -60,6 +58,7 @@ DECLARE_GLOBAL_DATA_PTR; #include #include +#include #include #include #include @@ -528,41 +527,6 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, return 0; } -#ifdef USE_HOSTCC -void memmove_wd(void *to, void *from, size_t len, ulong chunksz) -{ - memmove(to, from, len); -} -#endif /* !USE_HOSTCC */ - -void genimg_print_size(uint32_t size) -{ -#ifndef USE_HOSTCC - printf("%d Bytes = ", size); - print_size(size, "\n"); -#else - printf("%d Bytes = %.2f KiB = %.2f MiB\n", - size, (double)size / 1.024e3, - (double)size / 1.048576e6); -#endif -} - -#if IMAGE_ENABLE_TIMESTAMP -void genimg_print_time(time_t timestamp) -{ -#ifndef USE_HOSTCC - struct rtc_time tm; - - rtc_to_tm(timestamp, &tm); - printf("%4d-%02d-%02d %2d:%02d:%02d UTC\n", - tm.tm_year, tm.tm_mon, tm.tm_mday, - tm.tm_hour, tm.tm_min, tm.tm_sec); -#else - printf("%s", ctime(×tamp)); -#endif -} -#endif - const table_entry_t *get_table_entry(const table_entry_t *table, int id) { for (; table->id >= 0; ++table) { diff --git a/tools/Makefile b/tools/Makefile index 4a86321f64..999fd46531 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -113,6 +113,7 @@ dumpimage-mkimage-objs := aisimage.o \ lib/fdtdec_common.o \ lib/fdtdec.o \ common/image.o \ + common/image-host.o \ imagetool.o \ imximage.o \ imx8image.o \ From 2ac00c050582389e667374bccc5cc19b4fce80f5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:18 -0600 Subject: [PATCH 087/228] image: Create a function to do manual relocation Rather than adding an #ifdef and open-coding this calculation, add a helper function to handle it. Use this in the image code. Signed-off-by: Simon Glass --- common/image.c | 33 +++++++-------------------------- include/relocate.h | 24 +++++++++++++++++++++++- 2 files changed, 30 insertions(+), 27 deletions(-) diff --git a/common/image.c b/common/image.c index 3eb6a7fca1..2f2fd052c5 100644 --- a/common/image.c +++ b/common/image.c @@ -63,6 +63,7 @@ DECLARE_GLOBAL_DATA_PTR; #include #include #include +#include #include #include #include @@ -565,11 +566,7 @@ const char *genimg_get_cat_name(enum ih_category category, uint id) entry = get_table_entry(table_info[category].table, id); if (!entry) return unknown_msg(category); -#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC) - return entry->lname; -#else - return entry->lname + gd->reloc_off; -#endif + return manual_reloc(entry->lname); } /** @@ -589,11 +586,7 @@ const char *genimg_get_cat_short_name(enum ih_category category, uint id) entry = get_table_entry(table_info[category].table, id); if (!entry) return unknown_msg(category); -#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC) - return entry->sname; -#else - return entry->sname + gd->reloc_off; -#endif + return manual_reloc(entry->sname); } int genimg_get_cat_count(enum ih_category category) @@ -643,11 +636,7 @@ char *get_table_entry_name(const table_entry_t *table, char *msg, int id) table = get_table_entry(table, id); if (!table) return msg; -#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC) - return table->lname; -#else - return table->lname + gd->reloc_off; -#endif + return manual_reloc(table->lname); } const char *genimg_get_os_name(uint8_t os) @@ -677,11 +666,7 @@ static const char *genimg_get_short_name(const table_entry_t *table, int val) table = get_table_entry(table, val); if (!table) return "unknown"; -#if defined(USE_HOSTCC) || !defined(CONFIG_NEEDS_MANUAL_RELOC) - return table->sname; -#else - return table->sname + gd->reloc_off; -#endif + return manual_reloc(table->sname); } const char *genimg_get_type_short_name(uint8_t type) @@ -724,12 +709,8 @@ int get_table_entry_id(const table_entry_t *table, const table_entry_t *t; for (t = table; t->id >= 0; ++t) { -#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) - if (t->sname && strcasecmp(t->sname + gd->reloc_off, name) == 0) -#else - if (t->sname && strcasecmp(t->sname, name) == 0) -#endif - return (t->id); + if (t->sname && !strcasecmp(manual_reloc(t->sname), name)) + return t->id; } debug("Invalid %s Type: %s\n", table_name, name); diff --git a/include/relocate.h b/include/relocate.h index 9ceeecdbe7..c4fad33612 100644 --- a/include/relocate.h +++ b/include/relocate.h @@ -7,7 +7,11 @@ #ifndef _RELOCATE_H_ #define _RELOCATE_H_ -#include +#ifndef USE_HOSTCC +#include + +DECLARE_GLOBAL_DATA_PTR; +#endif /** * copy_uboot_to_ram() - Copy U-Boot to its new relocated position @@ -35,4 +39,22 @@ int clear_bss(void); */ int do_elf_reloc_fixups(void); +/** + * manual_reloc() - Manually relocate a pointer if needed + * + * This is a nop in almost all cases, except for the systems with a broken gcc + * which need to manually relocate some things. + * + * @ptr: Pointer to relocate + * @return new pointer value + */ +static inline void *manual_reloc(void *ptr) +{ +#ifndef USE_HOSTCC + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) + return ptr + gd->reloc_off; +#endif + return ptr; +} + #endif /* _RELOCATE_H_ */ From c5a68d29e38ce25646ee42eb49a29364aab84531 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:19 -0600 Subject: [PATCH 088/228] image: Avoid #ifdefs for manual relocation Add a macro to handle manually relocating a pointer. Update the iamge code to use this to avoid needing #ifdefs. This also fixes a bug where the 'done' flag was not set. Signed-off-by: Simon Glass --- common/image-sig.c | 38 +++++++++++++++++++++----------------- include/relocate.h | 6 ++++++ 2 files changed, 27 insertions(+), 17 deletions(-) diff --git a/common/image-sig.c b/common/image-sig.c index fa9407bb30..1aa0b58645 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -9,6 +9,7 @@ #include DECLARE_GLOBAL_DATA_PTR; #include +#include #include #include #include @@ -56,17 +57,19 @@ struct checksum_algo *image_get_checksum_algo(const char *full_name) int i; const char *name; -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - static bool done; + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) { + static bool done; - if (!done) { - done = true; - for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) { - checksum_algos[i].name += gd->reloc_off; - checksum_algos[i].calculate += gd->reloc_off; + if (!done) { + done = true; + for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) { + struct checksum_algo *algo = &checksum_algos[i]; + + MANUAL_RELOC(algo->name); + MANUAL_RELOC(algo->calculate); + } } } -#endif for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) { name = checksum_algos[i].name; @@ -84,18 +87,19 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name) struct crypto_algo *crypto, *end; const char *name; -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - static bool done; + if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC)) { + static bool done; - if (!done) { - crypto = ll_entry_start(struct crypto_algo, cryptos); - end = ll_entry_end(struct crypto_algo, cryptos); - for (; crypto < end; crypto++) { - crypto->name += gd->reloc_off; - crypto->verify += gd->reloc_off; + if (!done) { + done = true; + crypto = ll_entry_start(struct crypto_algo, cryptos); + end = ll_entry_end(struct crypto_algo, cryptos); + for (; crypto < end; crypto++) { + MANUAL_RELOC(crypto->name); + MANUAL_RELOC(crypto->verify); + } } } -#endif /* Move name to after the comma */ name = strchr(full_name, ','); diff --git a/include/relocate.h b/include/relocate.h index c4fad33612..26682da955 100644 --- a/include/relocate.h +++ b/include/relocate.h @@ -57,4 +57,10 @@ static inline void *manual_reloc(void *ptr) return ptr; } +#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC) +#define MANUAL_RELOC(ptr) (ptr) = manual_reloc(ptr) +#else +#define MANUAL_RELOC(ptr) (void)(ptr) +#endif + #endif /* _RELOCATE_H_ */ From 4ed37abc49c20b5dd0dc3ecd3eac53659057e455 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 07:03:20 -0600 Subject: [PATCH 089/228] image: Remove ifdefs around image_setup_linux() el at Drop some more ifdefs in image-board.c and also the FPGA part of bootm.c which calls into it. Signed-off-by: Simon Glass --- common/bootm.c | 16 ++++++++-------- common/image-board.c | 11 +++-------- 2 files changed, 11 insertions(+), 16 deletions(-) diff --git a/common/bootm.c b/common/bootm.c index ea71522d0c..fe17d1da9e 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -296,15 +296,15 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, #endif #if IMAGE_ENABLE_FIT -#if defined(CONFIG_FPGA) - /* find bitstreams */ - ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT, - NULL, NULL); - if (ret) { - printf("FPGA image is corrupted or invalid\n"); - return 1; + if (IS_ENABLED(CONFIG_FPGA)) { + /* find bitstreams */ + ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT, + NULL, NULL); + if (ret) { + printf("FPGA image is corrupted or invalid\n"); + return 1; + } } -#endif /* find all of the loadables */ ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT, diff --git a/common/image-board.c b/common/image-board.c index 898f0a2b7b..1d6842ffed 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -814,7 +814,6 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, } #endif -#ifdef CONFIG_SYS_BOOT_GET_CMDLINE /** * boot_get_cmdline - allocate and initialize kernel cmdline * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -853,9 +852,7 @@ int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end) return 0; } -#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */ -#ifdef CONFIG_SYS_BOOT_GET_KBD /** * boot_get_kbd - allocate and initialize kernel copy of board info * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -883,15 +880,14 @@ int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd) debug("## kernel board info at 0x%08lx\n", (ulong)*kbd); -#if defined(DEBUG) && defined(CONFIG_CMD_BDI) - do_bdinfo(NULL, 0, 0, NULL); +#if defined(DEBUG) + if (IS_ENABLED(CONFIG_CMD_BDI) + do_bdinfo(NULL, 0, 0, NULL); #endif return 0; } -#endif /* CONFIG_SYS_BOOT_GET_KBD */ -#ifdef CONFIG_LMB int image_setup_linux(bootm_headers_t *images) { ulong of_size = images->ft_len; @@ -925,7 +921,6 @@ int image_setup_linux(bootm_headers_t *images) return 0; } -#endif /* CONFIG_LMB */ void genimg_print_size(uint32_t size) { From c9d6b5b5dcce6820ea794af5f046803cdd43b37b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:14 -0600 Subject: [PATCH 090/228] compiler: Rename host_build() to tools_build() With the new TOOLS_LIBCRYPTO and some other changes, it seems that we are heading towards calling this a tools build rather than a host build, although of course it does happen on the host. I cannot think of anything built by the host which cannot be described as a tool, so rename this function. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/image-fit.c | 8 ++++---- common/image.c | 12 ++++++------ include/compiler.h | 5 +++-- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index 5a0a0cc200..6f8e67e415 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -509,7 +509,7 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) ret = fit_image_get_data_and_size(fit, image_noffset, &data, &size); - if (!host_build()) { + if (!tools_build()) { printf("%s Data Start: ", p); if (ret) { printf("unavailable\n"); @@ -1845,7 +1845,7 @@ int fit_conf_get_node(const void *fit, const char *conf_uname) if (conf_uname == NULL) { /* get configuration unit name from the default property */ debug("No configuration specified, trying default...\n"); - if (!host_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (!tools_build() && IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { noffset = fit_find_config_node(fit); if (noffset < 0) return noffset; @@ -2093,7 +2093,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, } bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH); - if (!host_build() && IS_ENABLED(CONFIG_SANDBOX)) { + if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX)) { if (!fit_image_check_target_arch(fit, noffset)) { puts("Unsupported Architecture\n"); bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH); @@ -2158,7 +2158,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, } /* perform any post-processing on the image data */ - if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)) + if (!tools_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)) board_fit_image_post_process(fit, noffset, &buf, &size); len = (ulong)size; diff --git a/common/image.c b/common/image.c index 2f2fd052c5..66685b4ba9 100644 --- a/common/image.c +++ b/common/image.c @@ -460,11 +460,11 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, ret = -ENOSPC; break; case IH_COMP_GZIP: - if (!host_build() && CONFIG_IS_ENABLED(GZIP)) + if (!tools_build() && CONFIG_IS_ENABLED(GZIP)) ret = gunzip(load_buf, unc_len, image_buf, &image_len); break; case IH_COMP_BZIP2: - if (!host_build() && CONFIG_IS_ENABLED(BZIP2)) { + if (!tools_build() && CONFIG_IS_ENABLED(BZIP2)) { uint size = unc_len; /* @@ -478,7 +478,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, } break; case IH_COMP_LZMA: - if (!host_build() && CONFIG_IS_ENABLED(LZMA)) { + if (!tools_build() && CONFIG_IS_ENABLED(LZMA)) { SizeT lzma_len = unc_len; ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, @@ -487,7 +487,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, } break; case IH_COMP_LZO: - if (!host_build() && CONFIG_IS_ENABLED(LZO)) { + if (!tools_build() && CONFIG_IS_ENABLED(LZO)) { size_t size = unc_len; ret = lzop_decompress(image_buf, image_len, load_buf, &size); @@ -495,7 +495,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, } break; case IH_COMP_LZ4: - if (!host_build() && CONFIG_IS_ENABLED(LZ4)) { + if (!tools_build() && CONFIG_IS_ENABLED(LZ4)) { size_t size = unc_len; ret = ulz4fn(image_buf, image_len, load_buf, &size); @@ -503,7 +503,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, } break; case IH_COMP_ZSTD: - if (!host_build() && CONFIG_IS_ENABLED(ZSTD)) { + if (!tools_build() && CONFIG_IS_ENABLED(ZSTD)) { struct abuf in, out; abuf_init_set(&in, image_buf, image_len); diff --git a/include/compiler.h b/include/compiler.h index 6b0d3bf537..8cf11792e2 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -155,11 +155,12 @@ typedef unsigned long int uintptr_t; #endif /** - * host_build() - check if we are building for the host + * tools_build() - check if we are building host tools * * @return true if building for the host, false if for a target */ -static inline bool host_build(void) { +static inline bool tools_build(void) +{ #ifdef USE_HOSTCC return true; #else From 5500a408dd81d5e5718a0fcd98ce55586d125853 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:15 -0600 Subject: [PATCH 091/228] kconfig: Add tools support to CONFIG_IS_ENABLED() At present we must separately test for the host build for many options, since we force them to be enabled. For example, CONFIG_FIT is always enabled in the host tools, even if CONFIG_FIT is not enabled by the board itself. It would be more convenient if we could use, for example, CONFIG_IS_ENABLED(FIT) and get CONFIG_HOST_FIT, when building for the host. Add support for this. With this and the tools_build() function, we should be able to remove all the #ifdefs currently needed in code that is build by tools and targets. This will be even nicer when we move to using CONFIG(xxx) everywhere, since all the #ifdef and IS_ENABLED/CONFIG_IS_ENABLED stuff will go away. Signed-off-by: Simon Glass Suggested-by: Rasmus Villemoes # b4f73886 Reviewed-by: Alexandru Gagniuc --- include/linux/kconfig.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h index d109ed3119..a1d1a29842 100644 --- a/include/linux/kconfig.h +++ b/include/linux/kconfig.h @@ -31,11 +31,14 @@ (config_enabled(option)) /* - * U-Boot add-on: Helper macros to reference to different macros - * (CONFIG_ or CONFIG_SPL_ prefixed), depending on the build context. + * U-Boot add-on: Helper macros to reference to different macros (prefixed by + * CONFIG_, CONFIG_SPL_, CONFIG_TPL_ or CONFIG_TOOLS_), depending on the build + * context. */ -#if defined(CONFIG_TPL_BUILD) +#ifdef USE_HOSTCC +#define _CONFIG_PREFIX TOOLS_ +#elif defined(CONFIG_TPL_BUILD) #define _CONFIG_PREFIX TPL_ #elif defined(CONFIG_SPL_BUILD) #define _CONFIG_PREFIX SPL_ @@ -49,6 +52,7 @@ /* * CONFIG_VAL(FOO) evaluates to the value of + * CONFIG_TOOLS_FOO if USE_HOSTCC is defined, * CONFIG_FOO if CONFIG_SPL_BUILD is undefined, * CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined. * CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined. @@ -76,18 +80,21 @@ /* * CONFIG_IS_ENABLED(FOO) expands to + * 1 if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y', * 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', * 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', * 1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', * 0 otherwise. * * CONFIG_IS_ENABLED(FOO, (abc)) expands to + * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y', * abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', * abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', * abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', * nothing otherwise. * * CONFIG_IS_ENABLED(FOO, (abc), (def)) expands to + * abc if USE_HOSTCC is defined and CONFIG_TOOLS_FOO is set to 'y', * abc if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y', * abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y', * abc if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y', From e02b3fd4b9cf34c7d22254e8d6db69e2f4471f4f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:16 -0600 Subject: [PATCH 092/228] image: Add Kconfig options for FIT in the tools build In preparation for enabling CONFIG_IS_ENABLED() on the host build, add some options to enable the various FIT options expected in these tools. This will ensure that the code builds correctly when CONFIG_TOOLS_xxx is distinct from CONFIG_xxx. Drop some #ifdefs which are immediately unnecessary (many more are in later patches). Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc Reviewed-by: Alexandru Gagniuc --- common/image-fit-sig.c | 3 ++- common/image-fit.c | 4 ++-- tools/Kconfig | 25 +++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 3 deletions(-) diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c index b979cd2a4b..e95e64bd2f 100644 --- a/common/image-fit-sig.c +++ b/common/image-fit-sig.c @@ -72,11 +72,12 @@ static int fit_image_setup_verify(struct image_sign_info *info, char *algo_name; const char *padding_name; +#ifndef USE_HOSTCC if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) { *err_msgp = "Total size too large"; return 1; } - +#endif if (fit_image_hash_get_algo(fit, noffset, &algo_name)) { *err_msgp = "Can't get hash algo property"; return -1; diff --git a/common/image-fit.c b/common/image-fit.c index 6f8e67e415..17c6d4e781 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -170,7 +170,7 @@ int fit_get_subimage_count(const void *fit, int images_noffset) return count; } -#if CONFIG_IS_ENABLED(FIT_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT) +#if CONFIG_IS_ENABLED(FIT_PRINT) /** * fit_image_print_data() - prints out the hash node details * @fit: pointer to the FIT format image header @@ -578,7 +578,7 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) #else void fit_print_contents(const void *fit) { } void fit_image_print(const void *fit, int image_noffset, const char *p) { } -#endif /* CONFIG_IS_ENABLED(FIR_PRINT) || CONFIG_IS_ENABLED(SPL_FIT_PRINT) */ +#endif /* CONFIG_IS_ENABLED(FIT_PRINT) */ /** * fit_get_desc - get node description property diff --git a/tools/Kconfig b/tools/Kconfig index d6f82cd949..ea986ab047 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -20,4 +20,29 @@ config TOOLS_LIBCRYPTO This selection does not affect target features, such as runtime FIT signature verification. +config TOOLS_FIT + def_bool y + help + Enable FIT support in the tools builds. + +config TOOLS_FIT_FULL_CHECK + def_bool y + help + Do a full check of the FIT before using it in the tools builds + +config TOOLS_FIT_PRINT + def_bool y + help + Print the content of the FIT verbosely in the tools builds + +config TOOLS_FIT_SIGNATURE + def_bool y + help + Enable signature verification of FIT uImages in the tools builds + +config TOOLS_FIT_SIGNATURE_MAX_SIZE + hex + depends on TOOLS_FIT_SIGNATURE + default 0x10000000 + endmenu From 603d15a572d5b1e2894db87b86d85a092dacdfd1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:17 -0600 Subject: [PATCH 093/228] spl: cypto: Bring back SPL_ versions of SHA Unfortunately these were removed by mistake. This means that adding hash support to SPL brings in all software algorithms, with a substantial increase in code size. The origin of the problem was renaming them to SPL_FIT_xxx and then these were removed altogether in a later commit. Add them back. This aligns with CONFIG_MD5, for example, which has an SPL variant. Signed-off-by: Simon Glass Fixes: f5bc9c25f31 ("image: Rename SPL_SHAxxx_SUPPORT to SPL_FIT_SHAxxx") Fixes: eb5171ddec9 ("common: Remove unused CONFIG_FIT_SHAxxx selectors") Reviewed-by: Alexandru Gagniuc --- lib/Kconfig | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/lib/Kconfig b/lib/Kconfig index 034af724b5..7899e756f9 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -373,7 +373,6 @@ config SHA256 The SHA256 algorithm produces a 256-bit (32-byte) hash value (digest). - config SHA512 bool "Enable SHA512 support" help @@ -399,6 +398,48 @@ config SHA_HW_ACCEL hashing algorithms. This affects the 'hash' command and also the hash_lookup_algo() function. +if SPL + +config SPL_SHA1 + bool "Enable SHA1 support in SPL" + default y if SHA1 + help + This option enables support of hashing using SHA1 algorithm. + The hash is calculated in software. + The SHA1 algorithm produces a 160-bit (20-byte) hash value + (digest). + +config SPL_SHA256 + bool "Enable SHA256 support in SPL" + default y if SHA256 + help + This option enables support of hashing using SHA256 algorithm. + The hash is calculated in software. + The SHA256 algorithm produces a 256-bit (32-byte) hash value + (digest). + +config SPL_SHA512 + bool "Enable SHA512 support in SPL" + default y if SHA512 + help + This option enables support of hashing using SHA512 algorithm. + The hash is calculated in software. + The SHA512 algorithm produces a 512-bit (64-byte) hash value + (digest). + +config SPL_SHA384 + bool "Enable SHA384 support in SPL" + default y if SHA384 + select SPL_SHA512 + help + This option enables support of hashing using SHA384 algorithm. + The hash is calculated in software. This is also selects SHA512, + because these implementations share the bulk of the code.. + The SHA384 algorithm produces a 384-bit (48-byte) hash value + (digest). + +endif + if SHA_HW_ACCEL config SHA512_HW_ACCEL From 2c21256b27d70b5950bd059330cdab027fb6ab7e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:18 -0600 Subject: [PATCH 094/228] hash: Use Kconfig to enable hashing in host tools and SPL At present when building host tools, we force CONFIG_SHAxxx to be enabled regardless of the board Kconfig setting. This is done in the image.h header file. For SPL we currently just assume the algorithm is desired if U-Boot proper enables it. Clean this up by adding new Kconfig options to enable hashing on the host, relying on CONFIG_IS_ENABLED() to deal with the different builds. Add new SPL Kconfigs for hardware-accelerated hashing, to maintain the current settings. This allows us to drop the image.h code and the I_WANT_MD5 hack. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/hash.c | 49 ++++++++++++++++++++----------------------- include/fdt_support.h | 2 +- include/hash.h | 6 +++++- include/image.h | 5 ----- lib/Kconfig | 18 ++++++++++++++++ tools/Kconfig | 25 ++++++++++++++++++++++ 6 files changed, 72 insertions(+), 33 deletions(-) diff --git a/common/hash.c b/common/hash.c index 3884298edf..2b8e7a4d5c 100644 --- a/common/hash.c +++ b/common/hash.c @@ -25,6 +25,7 @@ #else #include "mkimage.h" #include +#include #endif /* !USE_HOSTCC*/ #include @@ -41,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; static void reloc_update(void); -#if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL) +#if CONFIG_IS_ENABLED(SHA1) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) static int hash_init_sha1(struct hash_algo *algo, void **ctxp) { sha1_context *ctx = malloc(sizeof(sha1_context)); @@ -69,7 +70,7 @@ static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf, } #endif -#if defined(CONFIG_SHA256) && !defined(CONFIG_SHA_PROG_HW_ACCEL) +#if CONFIG_IS_ENABLED(SHA256) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) static int hash_init_sha256(struct hash_algo *algo, void **ctxp) { sha256_context *ctx = malloc(sizeof(sha256_context)); @@ -97,7 +98,7 @@ static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void } #endif -#if defined(CONFIG_SHA384) && !defined(CONFIG_SHA_PROG_HW_ACCEL) +#if CONFIG_IS_ENABLED(SHA384) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) static int hash_init_sha384(struct hash_algo *algo, void **ctxp) { sha512_context *ctx = malloc(sizeof(sha512_context)); @@ -125,7 +126,7 @@ static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void } #endif -#if defined(CONFIG_SHA512) && !defined(CONFIG_SHA_PROG_HW_ACCEL) +#if CONFIG_IS_ENABLED(SHA512) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) static int hash_init_sha512(struct hash_algo *algo, void **ctxp) { sha512_context *ctx = malloc(sizeof(sha512_context)); @@ -207,18 +208,13 @@ static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf, return 0; } -#ifdef USE_HOSTCC -# define I_WANT_MD5 1 -#else -# define I_WANT_MD5 CONFIG_IS_ENABLED(MD5) -#endif /* * These are the hash algorithms we support. If we have hardware acceleration * is enable we will use that, otherwise a software version of the algorithm. * Note that algorithm names must be in lower case. */ static struct hash_algo hash_algo[] = { -#if I_WANT_MD5 +#if CONFIG_IS_ENABLED(MD5) { .name = "md5", .digest_size = MD5_SUM_LEN, @@ -226,17 +222,17 @@ static struct hash_algo hash_algo[] = { .hash_func_ws = md5_wd, }, #endif -#ifdef CONFIG_SHA1 +#if CONFIG_IS_ENABLED(SHA1) { .name = "sha1", .digest_size = SHA1_SUM_LEN, .chunk_size = CHUNKSZ_SHA1, -#ifdef CONFIG_SHA_HW_ACCEL +#if CONFIG_IS_ENABLED(SHA_HW_ACCEL) .hash_func_ws = hw_sha1, #else .hash_func_ws = sha1_csum_wd, #endif -#ifdef CONFIG_SHA_PROG_HW_ACCEL +#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) .hash_init = hw_sha_init, .hash_update = hw_sha_update, .hash_finish = hw_sha_finish, @@ -247,17 +243,17 @@ static struct hash_algo hash_algo[] = { #endif }, #endif -#ifdef CONFIG_SHA256 +#if CONFIG_IS_ENABLED(SHA256) { .name = "sha256", .digest_size = SHA256_SUM_LEN, .chunk_size = CHUNKSZ_SHA256, -#ifdef CONFIG_SHA_HW_ACCEL +#if CONFIG_IS_ENABLED(SHA_HW_ACCEL) .hash_func_ws = hw_sha256, #else .hash_func_ws = sha256_csum_wd, #endif -#ifdef CONFIG_SHA_PROG_HW_ACCEL +#if CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) .hash_init = hw_sha_init, .hash_update = hw_sha_update, .hash_finish = hw_sha_finish, @@ -268,17 +264,17 @@ static struct hash_algo hash_algo[] = { #endif }, #endif -#ifdef CONFIG_SHA384 +#if CONFIG_IS_ENABLED(SHA384) { .name = "sha384", .digest_size = SHA384_SUM_LEN, .chunk_size = CHUNKSZ_SHA384, -#ifdef CONFIG_SHA512_HW_ACCEL +#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) .hash_func_ws = hw_sha384, #else .hash_func_ws = sha384_csum_wd, #endif -#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL) +#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) .hash_init = hw_sha_init, .hash_update = hw_sha_update, .hash_finish = hw_sha_finish, @@ -289,17 +285,17 @@ static struct hash_algo hash_algo[] = { #endif }, #endif -#ifdef CONFIG_SHA512 +#if CONFIG_IS_ENABLED(SHA512) { .name = "sha512", .digest_size = SHA512_SUM_LEN, .chunk_size = CHUNKSZ_SHA512, -#ifdef CONFIG_SHA512_HW_ACCEL +#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) .hash_func_ws = hw_sha512, #else .hash_func_ws = sha512_csum_wd, #endif -#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL) +#if CONFIG_IS_ENABLED(SHA512_HW_ACCEL) && CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) .hash_init = hw_sha_init, .hash_update = hw_sha_update, .hash_finish = hw_sha_finish, @@ -331,9 +327,9 @@ static struct hash_algo hash_algo[] = { }; /* Try to minimize code size for boards that don't want much hashing */ -#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM) || \ - defined(CONFIG_CRC32_VERIFY) || defined(CONFIG_CMD_HASH) || \ - defined(CONFIG_SHA384) || defined(CONFIG_SHA512) +#if CONFIG_IS_ENABLED(SHA256) || CONFIG_IS_ENABLED(CMD_SHA1SUM) || \ + CONFIG_IS_ENABLED(CRC32_VERIFY) || CONFIG_IS_ENABLED(CMD_HASH) || \ + CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512) #define multi_hash() 1 #else #define multi_hash() 0 @@ -438,7 +434,8 @@ int hash_block(const char *algo_name, const void *data, unsigned int len, return 0; } -#if defined(CONFIG_CMD_HASH) || defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32) +#if !defined(CONFIG_SPL_BUILD) && (defined(CONFIG_CMD_HASH) || \ + defined(CONFIG_CMD_SHA1SUM) || defined(CONFIG_CMD_CRC32)) /** * store_result: Store the resulting sum to an address or variable * diff --git a/include/fdt_support.h b/include/fdt_support.h index 72a5b90c97..88d129c803 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -7,7 +7,7 @@ #ifndef __FDT_SUPPORT_H #define __FDT_SUPPORT_H -#ifdef CONFIG_OF_LIBFDT +#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC) #include #include diff --git a/include/hash.h b/include/hash.h index 97bb3ed5d9..cfafbe7006 100644 --- a/include/hash.h +++ b/include/hash.h @@ -6,13 +6,17 @@ #ifndef _HASH_H #define _HASH_H +#ifdef USE_HOSTCC +#include +#endif + struct cmd_tbl; /* * Maximum digest size for all algorithms we support. Having this value * avoids a malloc() or C99 local declaration in common/cmd_hash.c. */ -#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512) +#if CONFIG_IS_ENABLED(SHA384) || CONFIG_IS_ENABLED(SHA512) #define HASH_MAX_DIGEST_SIZE 64 #else #define HASH_MAX_DIGEST_SIZE 32 diff --git a/include/image.h b/include/image.h index 73a763a693..03857f4b50 100644 --- a/include/image.h +++ b/include/image.h @@ -31,11 +31,6 @@ struct fdt_region; #define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_RSASSA_PSS 1 -#define CONFIG_MD5 -#define CONFIG_SHA1 -#define CONFIG_SHA256 -#define CONFIG_SHA384 -#define CONFIG_SHA512 #define IMAGE_ENABLE_IGNORE 0 #define IMAGE_INDENT_STRING "" diff --git a/lib/Kconfig b/lib/Kconfig index 7899e756f9..64765acfa6 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -438,6 +438,24 @@ config SPL_SHA384 The SHA384 algorithm produces a 384-bit (48-byte) hash value (digest). +config SPL_SHA_HW_ACCEL + bool "Enable hardware acceleration for SHA hash functions" + default y if SHA_HW_ACCEL + help + This option enables hardware acceleration for the SHA1 and SHA256 + hashing algorithms. This affects the 'hash' command and also the + hash_lookup_algo() function. + +config SPL_SHA_PROG_HW_ACCEL + bool "Enable Progressive hashing support using hardware in SPL" + depends on SHA_PROG_HW_ACCEL + default y + help + This option enables hardware-acceleration for SHA progressive + hashing. + Data can be streamed in a block at a time and the hashing is + performed in hardware. + endif if SHA_HW_ACCEL diff --git a/tools/Kconfig b/tools/Kconfig index ea986ab047..6ffc2c0aa3 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -45,4 +45,29 @@ config TOOLS_FIT_SIGNATURE_MAX_SIZE depends on TOOLS_FIT_SIGNATURE default 0x10000000 +config TOOLS_MD5 + def_bool y + help + Enable MD5 support in the tools builds + +config TOOLS_SHA1 + def_bool y + help + Enable SHA1 support in the tools builds + +config TOOLS_SHA256 + def_bool y + help + Enable SHA256 support in the tools builds + +config TOOLS_SHA384 + def_bool y + help + Enable SHA384 support in the tools builds + +config TOOLS_SHA512 + def_bool y + help + Enable SHA512 support in the tools builds + endmenu From d54f7e3f2328ea361c3a58714127ed9b3ad0f70c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:19 -0600 Subject: [PATCH 095/228] hash: Drop some #ifdefs in hash.c We can use the __maybe_unused attribute to avoid some of the #ifdefs in this file. Update the functions accordingly. Note: The actual hashing interface is still a mess, with four separate combinations and lots of #ifdefs. This should really use a driver approach, e.g. as is done with partition drivers. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/hash.c | 54 ++++++++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/common/hash.c b/common/hash.c index 2b8e7a4d5c..3b591ba09e 100644 --- a/common/hash.c +++ b/common/hash.c @@ -24,6 +24,7 @@ #include #else #include "mkimage.h" +#include #include #include #endif /* !USE_HOSTCC*/ @@ -42,8 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; static void reloc_update(void); -#if CONFIG_IS_ENABLED(SHA1) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) -static int hash_init_sha1(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_sha1(struct hash_algo *algo, void **ctxp) { sha1_context *ctx = malloc(sizeof(sha1_context)); sha1_starts(ctx); @@ -51,15 +51,16 @@ static int hash_init_sha1(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_sha1(struct hash_algo *algo, void *ctx, const void *buf, - unsigned int size, int is_last) +static int __maybe_unused hash_update_sha1(struct hash_algo *algo, void *ctx, + const void *buf, unsigned int size, + int is_last) { sha1_update((sha1_context *)ctx, buf, size); return 0; } -static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf, - int size) +static int __maybe_unused hash_finish_sha1(struct hash_algo *algo, void *ctx, + void *dest_buf, int size) { if (size < algo->digest_size) return -1; @@ -68,10 +69,8 @@ static int hash_finish_sha1(struct hash_algo *algo, void *ctx, void *dest_buf, free(ctx); return 0; } -#endif -#if CONFIG_IS_ENABLED(SHA256) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) -static int hash_init_sha256(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_sha256(struct hash_algo *algo, void **ctxp) { sha256_context *ctx = malloc(sizeof(sha256_context)); sha256_starts(ctx); @@ -79,15 +78,16 @@ static int hash_init_sha256(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_sha256(struct hash_algo *algo, void *ctx, - const void *buf, unsigned int size, int is_last) +static int __maybe_unused hash_update_sha256(struct hash_algo *algo, void *ctx, + const void *buf, uint size, + int is_last) { sha256_update((sha256_context *)ctx, buf, size); return 0; } -static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void - *dest_buf, int size) +static int __maybe_unused hash_finish_sha256(struct hash_algo *algo, void *ctx, + void *dest_buf, int size) { if (size < algo->digest_size) return -1; @@ -96,10 +96,8 @@ static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void free(ctx); return 0; } -#endif -#if CONFIG_IS_ENABLED(SHA384) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) -static int hash_init_sha384(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_sha384(struct hash_algo *algo, void **ctxp) { sha512_context *ctx = malloc(sizeof(sha512_context)); sha384_starts(ctx); @@ -107,15 +105,16 @@ static int hash_init_sha384(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_sha384(struct hash_algo *algo, void *ctx, - const void *buf, unsigned int size, int is_last) +static int __maybe_unused hash_update_sha384(struct hash_algo *algo, void *ctx, + const void *buf, uint size, + int is_last) { sha384_update((sha512_context *)ctx, buf, size); return 0; } -static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void - *dest_buf, int size) +static int __maybe_unused hash_finish_sha384(struct hash_algo *algo, void *ctx, + void *dest_buf, int size) { if (size < algo->digest_size) return -1; @@ -124,10 +123,8 @@ static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void free(ctx); return 0; } -#endif -#if CONFIG_IS_ENABLED(SHA512) && !CONFIG_IS_ENABLED(SHA_PROG_HW_ACCEL) -static int hash_init_sha512(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_sha512(struct hash_algo *algo, void **ctxp) { sha512_context *ctx = malloc(sizeof(sha512_context)); sha512_starts(ctx); @@ -135,15 +132,16 @@ static int hash_init_sha512(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_sha512(struct hash_algo *algo, void *ctx, - const void *buf, unsigned int size, int is_last) +static int __maybe_unused hash_update_sha512(struct hash_algo *algo, void *ctx, + const void *buf, uint size, + int is_last) { sha512_update((sha512_context *)ctx, buf, size); return 0; } -static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void - *dest_buf, int size) +static int __maybe_unused hash_finish_sha512(struct hash_algo *algo, void *ctx, + void *dest_buf, int size) { if (size < algo->digest_size) return -1; @@ -152,8 +150,6 @@ static int hash_finish_sha512(struct hash_algo *algo, void *ctx, void free(ctx); return 0; } -#endif - static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp) { From bf371b4cf599ad1a448577daaba997a0b0ba6c9c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:20 -0600 Subject: [PATCH 096/228] image: Drop IMAGE_ENABLE_FIT Make use of the host Kconfig for FIT. With this we can use CONFIG_IS_ENABLED(FIT) directly in the host build, so drop the unnecessary indirection. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- arch/arm/mach-imx/hab.c | 2 +- common/bootm.c | 10 +++++----- common/image-board.c | 16 ++++++++-------- common/image.c | 2 +- include/image.h | 17 ++++++++--------- 5 files changed, 23 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index cc39e6bf56..55317abba2 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -591,7 +591,7 @@ static ulong get_image_ivt_offset(ulong img_addr) return (image_get_image_size((image_header_t *)img_addr) + 0x1000 - 1) & ~(0x1000 - 1); #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) case IMAGE_FORMAT_FIT: return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1); #endif diff --git a/common/bootm.c b/common/bootm.c index fe17d1da9e..8d614fe140 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -115,7 +115,7 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, images.os.arch = image_get_arch(os_hdr); break; #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) case IMAGE_FORMAT_FIT: if (fit_image_get_type(images.fit_hdr_os, images.fit_noffset_os, @@ -187,7 +187,7 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, /* Kernel entry point is the setup.bin */ } else if (images.legacy_hdr_valid) { images.ep = image_get_ep(&images.legacy_hdr_os_copy); -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) } else if (images.fit_uname_os) { int ret; @@ -295,7 +295,7 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, set_working_fdt_addr(map_to_sysmem(images.ft_addr)); #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) if (IS_ENABLED(CONFIG_FPGA)) { /* find bitstreams */ ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT, @@ -858,7 +858,7 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, const void *buf; const char *fit_uname_config = NULL; const char *fit_uname_kernel = NULL; -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) int os_noffset; #endif @@ -916,7 +916,7 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE); break; #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) case IMAGE_FORMAT_FIT: os_noffset = fit_image_load(images, img_addr, &fit_uname_kernel, &fit_uname_config, diff --git a/common/image-board.c b/common/image-board.c index 1d6842ffed..0ad75fdc75 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -282,7 +282,7 @@ int genimg_get_format(const void *img_addr) if (image_check_magic(hdr)) return IMAGE_FORMAT_LEGACY; #endif -#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT +#if CONFIG_IS_ENABLED(FIT) || IMAGE_ENABLE_OF_LIBFDT if (fdt_check_header(img_addr) == 0) return IMAGE_FORMAT_FIT; #endif @@ -307,7 +307,7 @@ int genimg_get_format(const void *img_addr) */ int genimg_has_config(bootm_headers_t *images) { -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) if (images->fit_uname_cfg) return 1; #endif @@ -348,7 +348,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, #ifdef CONFIG_SUPPORT_RAW_INITRD char *end; #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) const char *fit_uname_config = images->fit_uname_cfg; const char *fit_uname_ramdisk = NULL; ulong default_addr; @@ -380,7 +380,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, rd_len = 0; rd_data = 0; } else if (select || genimg_has_config(images)) { -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) if (select) { /* * If the init ramdisk comes from the FIT image and @@ -409,7 +409,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, debug("* ramdisk: cmdline image address = 0x%08lx\n", rd_addr); } -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) } else { /* use FIT configuration provided in first bootm * command argument. If the property is not defined, @@ -450,7 +450,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, rd_load = image_get_load(rd_hdr); break; #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) case IMAGE_FORMAT_FIT: rd_noffset = fit_image_load(images, rd_addr, &fit_uname_ramdisk, @@ -623,14 +623,14 @@ error: int boot_get_setup(bootm_headers_t *images, u8 arch, ulong *setup_start, ulong *setup_len) { -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) return boot_get_setup_fit(images, arch, setup_start, setup_len); #else return -ENOENT; #endif } -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) #if defined(CONFIG_FPGA) int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, u8 arch, const ulong *ld_start, ulong * const ld_len) diff --git a/common/image.c b/common/image.c index 66685b4ba9..59b5e70cca 100644 --- a/common/image.c +++ b/common/image.c @@ -18,7 +18,7 @@ #include #endif -#if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT +#if CONFIG_IS_ENABLED(FIT) || IMAGE_ENABLE_OF_LIBFDT #include #include #endif diff --git a/include/image.h b/include/image.h index 03857f4b50..6c229212cb 100644 --- a/include/image.h +++ b/include/image.h @@ -25,9 +25,9 @@ struct fdt_region; #ifdef USE_HOSTCC #include +#include /* new uImage format support enabled on host */ -#define IMAGE_ENABLE_FIT 1 #define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_RSASSA_PSS 1 @@ -46,16 +46,15 @@ struct fdt_region; #define IMAGE_ENABLE_IGNORE 1 #define IMAGE_INDENT_STRING " " -#define IMAGE_ENABLE_FIT CONFIG_IS_ENABLED(FIT) #define IMAGE_ENABLE_OF_LIBFDT CONFIG_IS_ENABLED(OF_LIBFDT) #endif /* USE_HOSTCC */ -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) #include #include #include -#endif /* IMAGE_ENABLE_FIT */ +#endif /* FIT */ #ifdef CONFIG_SYS_BOOT_GET_CMDLINE # define IMAGE_BOOT_GET_CMDLINE 1 @@ -328,7 +327,7 @@ typedef struct bootm_headers { image_header_t legacy_hdr_os_copy; /* header copy */ ulong legacy_hdr_valid; -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) const char *fit_uname_cfg; /* configuration node unit name */ void *fit_hdr_os; /* os FIT image header */ @@ -983,7 +982,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) /* cmdline argument format parsing */ int fit_parse_conf(const char *spec, ulong addr_curr, ulong *addr, const char **conf_name); @@ -1157,7 +1156,7 @@ int fit_conf_get_prop_node(const void *fit, int noffset, int fit_check_ramdisk(const void *fit, int os_noffset, uint8_t arch, int verify); -#endif /* IMAGE_ENABLE_FIT */ +#endif /* FIT */ int calculate_hash(const void *data, int data_len, const char *algo, uint8_t *value, int *value_len); @@ -1180,7 +1179,7 @@ int calculate_hash(const void *data, int data_len, const char *algo, # define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE) #endif -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) #ifdef USE_HOSTCC void *image_get_host_blob(void); void image_set_host_blob(void *host_blob); @@ -1335,7 +1334,7 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name); */ struct padding_algo *image_get_padding_algo(const char *name); -#if IMAGE_ENABLE_FIT +#if CONFIG_IS_ENABLED(FIT) /** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' From 0c303f9a6628de9664b4f9140464a6f9d8224c36 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:21 -0600 Subject: [PATCH 097/228] image: Drop IMAGE_ENABLE_OF_LIBFDT Add a host Kconfig for OF_LIBFDT. With this we can use CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the unnecessary indirection. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- arch/arc/lib/bootm.c | 2 +- arch/arm/lib/bootm.c | 4 ++-- arch/microblaze/lib/bootm.c | 2 +- arch/nds32/lib/bootm.c | 4 ++-- arch/riscv/lib/bootm.c | 4 ++-- board/synopsys/hsdk/hsdk.c | 2 +- common/bootm.c | 4 ++-- common/image-board.c | 8 ++++---- common/image.c | 2 +- include/image.h | 3 --- lib/lmb.c | 2 +- tools/Kconfig | 5 +++++ 12 files changed, 22 insertions(+), 20 deletions(-) diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 41408c2b46..ed6c5dfa58 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -63,7 +63,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { r0 = 2; r2 = (unsigned int)images->ft_addr; } else { diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index dd6a69315a..a59a5e6c0e 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -199,7 +199,7 @@ static void boot_prep_linux(bootm_headers_t *images) { char *commandline = env_get("bootargs"); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { @@ -356,7 +356,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) bootstage_mark(BOOTSTAGE_ID_RUN_OS); announce_and_cleanup(fake); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) r2 = (unsigned long)images->ft_addr; else r2 = gd->bd->bi_boot_params; diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 3a6da6e29f..12ea32488e 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -75,7 +75,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) static void boot_prep_linux(bootm_headers_t *images) { - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { debug("using: FDT\n"); if (image_setup_linux(images)) { printf("FDT creation failed! hanging..."); diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 1c7f785699..71ebfb4225 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -69,7 +69,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) debug("## Transferring control to Linux (at address %08lx) ...\n", (ulong)theKernel); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { @@ -110,7 +110,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) #endif } cleanup_before_linux(); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) theKernel(0, machid, (unsigned long)images->ft_addr); else theKernel(0, machid, bd->bi_boot_params); diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index ff1bdf7131..2e1e286c8e 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -64,7 +64,7 @@ static void announce_and_cleanup(int fake) static void boot_prep_linux(bootm_headers_t *images) { - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_OF_LIBFDT debug("using: FDT\n"); if (image_setup_linux(images)) { @@ -96,7 +96,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) announce_and_cleanup(fake); if (!fake) { - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_SMP ret = smp_call_function(images->ep, (ulong)images->ft_addr, 0, 0); diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 892b94bb08..226fbba629 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -871,7 +871,7 @@ int board_prep_linux(bootm_headers_t *images) if (env_common.core_mask.val == ALL_CPU_MASK) return 0; - if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) { + if (!CONFIG_IS_ENABLED(OF_LIBFDT) || !images->ft_len) { pr_err("WARN: core_mask setup will work properly only with external DTB!\n"); return 0; } diff --git a/common/bootm.c b/common/bootm.c index 8d614fe140..4482f84b40 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -271,7 +271,7 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, return 1; } -#if IMAGE_ENABLE_OF_LIBFDT +#if CONFIG_IS_ENABLED(OF_LIBFDT) /* find flattened device tree */ ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images, &images.ft_addr, &images.ft_len); @@ -706,7 +706,7 @@ int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, } } #endif -#if IMAGE_ENABLE_OF_LIBFDT && defined(CONFIG_LMB) +#if CONFIG_IS_ENABLED(OF_LIBFDT) && defined(CONFIG_LMB) if (!ret && (states & BOOTM_STATE_FDT)) { boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr); ret = boot_relocate_fdt(&images->lmb, &images->ft_addr, diff --git a/common/image-board.c b/common/image-board.c index 0ad75fdc75..cb2479f2f3 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -282,7 +282,7 @@ int genimg_get_format(const void *img_addr) if (image_check_magic(hdr)) return IMAGE_FORMAT_LEGACY; #endif -#if CONFIG_IS_ENABLED(FIT) || IMAGE_ENABLE_OF_LIBFDT +#if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT) if (fdt_check_header(img_addr) == 0) return IMAGE_FORMAT_FIT; #endif @@ -895,7 +895,7 @@ int image_setup_linux(bootm_headers_t *images) struct lmb *lmb = &images->lmb; int ret; - if (IMAGE_ENABLE_OF_LIBFDT) + if (CONFIG_IS_ENABLED(OF_LIBFDT)) boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); if (IMAGE_BOOT_GET_CMDLINE) { @@ -907,13 +907,13 @@ int image_setup_linux(bootm_headers_t *images) } } - if (IMAGE_ENABLE_OF_LIBFDT) { + if (CONFIG_IS_ENABLED(OF_LIBFDT)) { ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); if (ret) return ret; } - if (IMAGE_ENABLE_OF_LIBFDT && of_size) { + if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) { ret = image_setup_libfdt(images, *of_flat_tree, of_size, lmb); if (ret) return ret; diff --git a/common/image.c b/common/image.c index 59b5e70cca..5b77113bea 100644 --- a/common/image.c +++ b/common/image.c @@ -18,7 +18,7 @@ #include #endif -#if CONFIG_IS_ENABLED(FIT) || IMAGE_ENABLE_OF_LIBFDT +#if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT) #include #include #endif diff --git a/include/image.h b/include/image.h index 6c229212cb..f09eb9de51 100644 --- a/include/image.h +++ b/include/image.h @@ -28,7 +28,6 @@ struct fdt_region; #include /* new uImage format support enabled on host */ -#define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_RSASSA_PSS 1 @@ -46,8 +45,6 @@ struct fdt_region; #define IMAGE_ENABLE_IGNORE 1 #define IMAGE_INDENT_STRING " " -#define IMAGE_ENABLE_OF_LIBFDT CONFIG_IS_ENABLED(OF_LIBFDT) - #endif /* USE_HOSTCC */ #if CONFIG_IS_ENABLED(FIT) diff --git a/lib/lmb.c b/lib/lmb.c index 793647724c..676b3a0bda 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -153,7 +153,7 @@ static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob) arch_lmb_reserve(lmb); board_lmb_reserve(lmb); - if (IMAGE_ENABLE_OF_LIBFDT && fdt_blob) + if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob) boot_fdt_add_mem_rsv_regions(lmb, fdt_blob); } diff --git a/tools/Kconfig b/tools/Kconfig index 6ffc2c0aa3..747d221803 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -50,6 +50,11 @@ config TOOLS_MD5 help Enable MD5 support in the tools builds +config TOOLS_OF_LIBFDT + def_bool y + help + Enable libfdt support in the tools builds + config TOOLS_SHA1 def_bool y help From e059157f0d5737b63fe2f1fec145509d82508109 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:22 -0600 Subject: [PATCH 098/228] image: Use Kconfig to enable CONFIG_FIT_VERBOSE on host Add a host Kconfig for FIT_VERBOSE. With this we can use CONFIG_IS_ENABLED(FIT_VERBOSE) directly in the tools build, so drop the forcing of this in the image.h header. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- include/image.h | 5 ++--- tools/Kconfig | 5 +++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/image.h b/include/image.h index f09eb9de51..6efbef06e6 100644 --- a/include/image.h +++ b/include/image.h @@ -28,7 +28,6 @@ struct fdt_region; #include /* new uImage format support enabled on host */ -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_RSASSA_PSS 1 #define IMAGE_ENABLE_IGNORE 0 @@ -1458,7 +1457,7 @@ int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); struct cipher_algo *image_get_cipher_algo(const char *full_name); -#ifdef CONFIG_FIT_VERBOSE +#if CONFIG_IS_ENABLED(FIT_VERBOSE) #define fit_unsupported(msg) printf("! %s:%d " \ "FIT images not supported for '%s'\n", \ __FILE__, __LINE__, (msg)) @@ -1470,7 +1469,7 @@ struct cipher_algo *image_get_cipher_algo(const char *full_name); #else #define fit_unsupported(msg) #define fit_unsupported_reset(msg) -#endif /* CONFIG_FIT_VERBOSE */ +#endif /* FIT_VERBOSE */ #endif /* CONFIG_FIT */ #if !defined(USE_HOSTCC) diff --git a/tools/Kconfig b/tools/Kconfig index 747d221803..9d1c0efd40 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -45,6 +45,11 @@ config TOOLS_FIT_SIGNATURE_MAX_SIZE depends on TOOLS_FIT_SIGNATURE default 0x10000000 +config TOOLS_FIT_VERBOSE + def_bool y + help + Support verbose FIT output in the tools builds + config TOOLS_MD5 def_bool y help From 2bbed3ff8c7fa0c0fa3fd28a9497bf7a99e3388b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:23 -0600 Subject: [PATCH 099/228] image: Use Kconfig to enable FIT_RSASSA_PSS on host Add a host Kconfig for FIT_RSASSA_PSS. With this we can use CONFIG_IS_ENABLED(FIT_RSASSA_PSS) directly in the host build, so drop the forcing of this in the image.h header. Drop the #ifdef around padding_pss_verify() too since it is not needed. Use the compiler to check the config where possible, instead of the preprocessor. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- include/image.h | 3 --- include/u-boot/rsa.h | 2 -- lib/rsa/rsa-sign.c | 5 ++--- lib/rsa/rsa-verify.c | 15 ++++----------- tools/Kconfig | 5 +++++ 5 files changed, 11 insertions(+), 19 deletions(-) diff --git a/include/image.h b/include/image.h index 6efbef06e6..dc872ef5b2 100644 --- a/include/image.h +++ b/include/image.h @@ -27,9 +27,6 @@ struct fdt_region; #include #include -/* new uImage format support enabled on host */ -#define CONFIG_FIT_RSASSA_PSS 1 - #define IMAGE_ENABLE_IGNORE 0 #define IMAGE_INDENT_STRING "" diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h index 89a9c4caa0..7556aa5b4b 100644 --- a/include/u-boot/rsa.h +++ b/include/u-boot/rsa.h @@ -103,11 +103,9 @@ int padding_pkcs_15_verify(struct image_sign_info *info, uint8_t *msg, int msg_len, const uint8_t *hash, int hash_len); -#ifdef CONFIG_FIT_RSASSA_PSS int padding_pss_verify(struct image_sign_info *info, uint8_t *msg, int msg_len, const uint8_t *hash, int hash_len); -#endif /* CONFIG_FIT_RSASSA_PSS */ #define RSA_DEFAULT_PADDING_NAME "pkcs-1.5" diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index c27a784c42..0579e5294e 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -401,15 +401,14 @@ static int rsa_sign_with_key(EVP_PKEY *pkey, struct padding_algo *padding_algo, goto err_sign; } -#ifdef CONFIG_FIT_RSASSA_PSS - if (padding_algo && !strcmp(padding_algo->name, "pss")) { + if (CONFIG_IS_ENABLED(FIT_RSASSA_PSS) && padding_algo && + !strcmp(padding_algo->name, "pss")) { if (EVP_PKEY_CTX_set_rsa_padding(ckey, RSA_PKCS1_PSS_PADDING) <= 0) { ret = rsa_err("Signer padding setup failed"); goto err_sign; } } -#endif /* CONFIG_FIT_RSASSA_PSS */ for (i = 0; i < region_count; i++) { if (!EVP_DigestSignUpdate(context, region[i].data, diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index ad6d33d043..600c93ab81 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -102,7 +102,7 @@ U_BOOT_PADDING_ALGO(pkcs_15) = { }; #endif -#ifdef CONFIG_FIT_RSASSA_PSS +#if CONFIG_IS_ENABLED(FIT_RSASSA_PSS) static void u32_i2osp(uint32_t val, uint8_t *buf) { buf[0] = (uint8_t)((val >> 24) & 0xff); @@ -313,7 +313,6 @@ U_BOOT_PADDING_ALGO(pss) = { #endif -#if CONFIG_IS_ENABLED(FIT_SIGNATURE) || CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY) /** * rsa_verify_key() - Verify a signature against some data using RSA Key * @@ -385,9 +384,7 @@ static int rsa_verify_key(struct image_sign_info *info, return 0; } -#endif -#if CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY) /** * rsa_verify_with_pkey() - Verify a signature against some data using * only modulus and exponent as RSA key properties. @@ -408,6 +405,9 @@ int rsa_verify_with_pkey(struct image_sign_info *info, struct key_prop *prop; int ret; + if (!CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY)) + return -EACCES; + /* Public key is self-described to fill key_prop */ ret = rsa_gen_key_prop(info->key, info->keylen, &prop); if (ret) { @@ -422,13 +422,6 @@ int rsa_verify_with_pkey(struct image_sign_info *info, return ret; } -#else -int rsa_verify_with_pkey(struct image_sign_info *info, - const void *hash, uint8_t *sig, uint sig_len) -{ - return -EACCES; -} -#endif #if CONFIG_IS_ENABLED(FIT_SIGNATURE) /** diff --git a/tools/Kconfig b/tools/Kconfig index 9d1c0efd40..8685c800f9 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -35,6 +35,11 @@ config TOOLS_FIT_PRINT help Print the content of the FIT verbosely in the tools builds +config TOOLS_FIT_RSASSA_PSS + def_bool y + help + Support the rsassa-pss signature scheme in the tools builds + config TOOLS_FIT_SIGNATURE def_bool y help From e7d285b2f38202f9d7ffbdcae59283f08bafd8b9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:24 -0600 Subject: [PATCH 100/228] image: Use the correct checks for CRC32 Add a host Kconfig for CRC32. With this we can use CONFIG_IS_ENABLED(CRC32) directly in the host build, so drop the unnecessary indirection. Add a few more conditions to SPL_CRC32 to avoid build failures as well as TPL_CRC32. Also update hash.c to make crc32 optional and to actually take notice of SPL_CRC32. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/hash.c | 13 ++++++++----- common/spl/Kconfig | 13 ++++++++++++- lib/Kconfig | 5 +++++ lib/Makefile | 4 +--- tools/Kconfig | 5 +++++ 5 files changed, 31 insertions(+), 9 deletions(-) diff --git a/common/hash.c b/common/hash.c index 3b591ba09e..79202e18a2 100644 --- a/common/hash.c +++ b/common/hash.c @@ -178,7 +178,7 @@ static int hash_finish_crc16_ccitt(struct hash_algo *algo, void *ctx, return 0; } -static int hash_init_crc32(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_crc32(struct hash_algo *algo, void **ctxp) { uint32_t *ctx = malloc(sizeof(uint32_t)); *ctx = 0; @@ -186,15 +186,16 @@ static int hash_init_crc32(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_crc32(struct hash_algo *algo, void *ctx, - const void *buf, unsigned int size, int is_last) +static int __maybe_unused hash_update_crc32(struct hash_algo *algo, void *ctx, + const void *buf, unsigned int size, + int is_last) { *((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), buf, size); return 0; } -static int hash_finish_crc32(struct hash_algo *algo, void *ctx, void *dest_buf, - int size) +static int __maybe_unused hash_finish_crc32(struct hash_algo *algo, void *ctx, + void *dest_buf, int size) { if (size < algo->digest_size) return -1; @@ -311,6 +312,7 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc16_ccitt, .hash_finish = hash_finish_crc16_ccitt, }, +#if CONFIG_IS_ENABLED(CRC32) { .name = "crc32", .digest_size = 4, @@ -320,6 +322,7 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc32, .hash_finish = hash_finish_crc32, }, +#endif }; /* Try to minimize code size for boards that don't want much hashing */ diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 8a8a971a91..17ce2f6b61 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -419,7 +419,8 @@ config SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION config SPL_CRC32 bool "Support CRC32" - default y if SPL_LEGACY_IMAGE_SUPPORT + default y if SPL_LEGACY_IMAGE_SUPPORT || SPL_EFI_PARTITION + default y if SPL_ENV_SUPPORT || TPL_BLOBLIST help Enable this to support CRC32 in uImages or FIT images within SPL. This is a 32-bit checksum value that can be used to verify images. @@ -1419,6 +1420,16 @@ config TPL_BOOTROM_SUPPORT BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the boot device list, if not implemented for a given board) +config TPL_CRC32 + bool "Support CRC32 in TPL" + default y if TPL_ENV_SUPPORT || TPL_BLOBLIST + help + Enable this to support CRC32 in uImages or FIT images within SPL. + This is a 32-bit checksum value that can be used to verify images. + For FIT images, this is the least secure type of checksum, suitable + for detected accidental image corruption. For secure applications you + should consider SHA1 or SHA256. + config TPL_DRIVERS_MISC bool "Support misc drivers in TPL" help diff --git a/lib/Kconfig b/lib/Kconfig index 64765acfa6..70bf8e7a46 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -496,6 +496,11 @@ config SPL_MD5 security applications, but it can be useful for providing a quick checksum of a block of data. +config CRC32 + def_bool y + help + Enables CRC32 support in U-Boot. This is normally required. + config CRC32C bool diff --git a/lib/Makefile b/lib/Makefile index 454396f101..5ddbc77ed6 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -96,9 +96,7 @@ obj-y += display_options.o CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"') obj-$(CONFIG_BCH) += bch.o obj-$(CONFIG_MMC_SPI) += crc7.o -#ifndef CONFIG_TPL_BUILD -obj-y += crc32.o -#endif +obj-$(CONFIG_$(SPL_TPL_)CRC32) += crc32.o obj-$(CONFIG_CRC32C) += crc32c.o obj-y += ctype.o obj-y += div64.o diff --git a/tools/Kconfig b/tools/Kconfig index 8685c800f9..91ce8ae3e5 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -9,6 +9,11 @@ config MKIMAGE_DTC_PATH some cases the system dtc may not support all required features and the path to a different version should be given here. +config TOOLS_CRC32 + def_bool y + help + Enable CRC32 support in the tools builds + config TOOLS_LIBCRYPTO bool "Use OpenSSL's libcrypto library for host tools" default y From 806d1ff37b0afe8cbf5658dc01876f6321aed235 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:25 -0600 Subject: [PATCH 101/228] image: Drop IMAGE_BOOT_GET_CMDLINE This is not needed with Kconfig, since we can use IS_ENABLED() easily enough and the board code is now in a separate file. Update the only place where this is used and drop it. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/image-board.c | 2 +- include/image.h | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/common/image-board.c b/common/image-board.c index cb2479f2f3..6565f014f7 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -898,7 +898,7 @@ int image_setup_linux(bootm_headers_t *images) if (CONFIG_IS_ENABLED(OF_LIBFDT)) boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); - if (IMAGE_BOOT_GET_CMDLINE) { + if (IS_ENABLED(CONFIG_SYS_BOOT_GET_CMDLINE)) { ret = boot_get_cmdline(lmb, &images->cmdline_start, &images->cmdline_end); if (ret) { diff --git a/include/image.h b/include/image.h index dc872ef5b2..00a8099958 100644 --- a/include/image.h +++ b/include/image.h @@ -49,12 +49,6 @@ struct fdt_region; #include #endif /* FIT */ -#ifdef CONFIG_SYS_BOOT_GET_CMDLINE -# define IMAGE_BOOT_GET_CMDLINE 1 -#else -# define IMAGE_BOOT_GET_CMDLINE 0 -#endif - #ifdef CONFIG_OF_BOARD_SETUP # define IMAGE_OF_BOARD_SETUP 1 #else From 30ba2828652915d29892146022ed92b2bd524ad6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:26 -0600 Subject: [PATCH 102/228] image: Drop IMAGE_OF_BOARD_SETUP This is not needed with Kconfig, since we can use IS_ENABLED() easily enough. Drop it. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/image-fdt.c | 4 ++-- include/image.h | 6 ------ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index b698e961fe..2be6d193f4 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -582,7 +582,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, /* Append PStore configuration */ fdt_fixup_pstore(blob); #endif - if (IMAGE_OF_BOARD_SETUP) { + if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) { const char *skip_board_fixup; skip_board_fixup = env_get("skip_board_fixup"); @@ -629,7 +629,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, goto err; #if defined(CONFIG_ARCH_KEYSTONE) - if (IMAGE_OF_BOARD_SETUP) + if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) ft_board_setup_ex(blob, gd->bd); #endif diff --git a/include/image.h b/include/image.h index 00a8099958..e1e4148e4c 100644 --- a/include/image.h +++ b/include/image.h @@ -49,12 +49,6 @@ struct fdt_region; #include #endif /* FIT */ -#ifdef CONFIG_OF_BOARD_SETUP -# define IMAGE_OF_BOARD_SETUP 1 -#else -# define IMAGE_OF_BOARD_SETUP 0 -#endif - #ifdef CONFIG_OF_SYSTEM_SETUP # define IMAGE_OF_SYSTEM_SETUP 1 #else From 3ac0f504125e2f97364ba8cc6bc95c1e350bd35a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:27 -0600 Subject: [PATCH 103/228] image: Drop IMAGE_OF_SYSTEM_SETUP This is not needed with Kconfig, since we can use IS_ENABLED() easily enough. Drop it. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/image-fdt.c | 2 +- include/image.h | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 2be6d193f4..abea17bd56 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -597,7 +597,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, } } } - if (IMAGE_OF_SYSTEM_SETUP) { + if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) { fdt_ret = ft_system_setup(blob, gd->bd); if (fdt_ret) { printf("ERROR: system-specific fdt fixup failed: %s\n", diff --git a/include/image.h b/include/image.h index e1e4148e4c..e190f59232 100644 --- a/include/image.h +++ b/include/image.h @@ -49,12 +49,6 @@ struct fdt_region; #include #endif /* FIT */ -#ifdef CONFIG_OF_SYSTEM_SETUP -# define IMAGE_OF_SYSTEM_SETUP 1 -#else -# define IMAGE_OF_SYSTEM_SETUP 0 -#endif - extern ulong image_load_addr; /* Default Load Address */ extern ulong image_save_addr; /* Default Save Address */ extern ulong image_save_size; /* Default Save Size */ From fa13940740e5ce1822611205bb8ac329c91306fd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:28 -0600 Subject: [PATCH 104/228] image: Drop IMAGE_ENABLE_IGNORE We can use the new host_build() function for this, so drop it. Signed-off-by: Simon Glass Reviewed-by: Alexandru Gagniuc --- common/image-fit.c | 2 +- include/image.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index 17c6d4e781..f44f5527b9 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1277,7 +1277,7 @@ static int fit_image_check_hash(const void *fit, int noffset, const void *data, } printf("%s", algo); - if (IMAGE_ENABLE_IGNORE) { + if (!tools_build()) { fit_image_hash_get_ignore(fit, noffset, &ignore); if (ignore) { printf("-skipped "); diff --git a/include/image.h b/include/image.h index e190f59232..a236180ccd 100644 --- a/include/image.h +++ b/include/image.h @@ -27,7 +27,6 @@ struct fdt_region; #include #include -#define IMAGE_ENABLE_IGNORE 0 #define IMAGE_INDENT_STRING "" #else @@ -37,8 +36,6 @@ struct fdt_region; #include #include -/* Take notice of the 'ignore' property for hashes */ -#define IMAGE_ENABLE_IGNORE 1 #define IMAGE_INDENT_STRING " " #endif /* USE_HOSTCC */ From 1eccbb16a2c0427488d91e169572c3c397c4c1d5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:29 -0600 Subject: [PATCH 105/228] efi: Correct dependency on FIT_SIGNATURE At present EFI_SECURE BOOT selects RSA but does not necessarily enable FIT_SIGNATURE. Mostly this is fine, but a few boards do not enable it, so U-Boot tries to do RSA verification when loading FIT images, but it is not enabled. This worked because the condition for checking the RSA signature is wrong in the fit_image_verify_with_data() function. In order to fix it we need to fix this dependency. Make sure that FIT_SIGNATURE is enabled so that RSA can be used. It might be better to avoid using 'select' in this situation. Signed-off-by: Simon Glass --- lib/efi_loader/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 3d5a5cd189..83d584a60e 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -336,7 +336,7 @@ config EFI_LOAD_FILE2_INITRD config EFI_SECURE_BOOT bool "Enable EFI secure boot support" - depends on EFI_LOADER + depends on EFI_LOADER && FIT_SIGNATURE select HASH select SHA256 select RSA From 0ab5e027045f78973b7b7d52a71a89a707398f9f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:32 -0600 Subject: [PATCH 106/228] image: Tidy up fit_unsupported_reset() This function is only used in one place and does not need to use the preprocessor. Move it to the C file and convert it to a normal function. Drop fit_unsupported() since it is not used. Signed-off-by: Simon Glass --- common/bootm_os.c | 8 ++++++++ include/image.h | 13 ------------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/common/bootm_os.c b/common/bootm_os.c index d635037064..39623f9126 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -58,6 +58,14 @@ static void copy_args(char *dest, int argc, char *const argv[], char delim) } #endif +static void __maybe_unused fit_unsupported_reset(const char *msg) +{ + if (CONFIG_IS_ENABLED(FIT_VERBOSE)) { + printf("! FIT images not supported for '%s' - must reset board to recover!\n", + msg); + } +} + #ifdef CONFIG_BOOTM_NETBSD static int do_bootm_netbsd(int flag, int argc, char *const argv[], bootm_headers_t *images) diff --git a/include/image.h b/include/image.h index a236180ccd..e397da80a5 100644 --- a/include/image.h +++ b/include/image.h @@ -1433,19 +1433,6 @@ int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); struct cipher_algo *image_get_cipher_algo(const char *full_name); -#if CONFIG_IS_ENABLED(FIT_VERBOSE) -#define fit_unsupported(msg) printf("! %s:%d " \ - "FIT images not supported for '%s'\n", \ - __FILE__, __LINE__, (msg)) - -#define fit_unsupported_reset(msg) printf("! %s:%d " \ - "FIT images not supported for '%s' " \ - "- must reset board to recover!\n", \ - __FILE__, __LINE__, (msg)) -#else -#define fit_unsupported(msg) -#define fit_unsupported_reset(msg) -#endif /* FIT_VERBOSE */ #endif /* CONFIG_FIT */ #if !defined(USE_HOSTCC) From 13c133b995decefdc64160f1df2c58e5bf342e28 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:33 -0600 Subject: [PATCH 107/228] image: Drop unnecessary #ifdefs from image.h This file has a lot of conditional code and much of it is unnecessary. Clean this up to reduce the number of build combinations. Signed-off-by: Simon Glass --- include/image.h | 39 ++++------------------------------ include/u-boot/hash-checksum.h | 5 +++-- lib/hash-checksum.c | 2 +- 3 files changed, 8 insertions(+), 38 deletions(-) diff --git a/include/image.h b/include/image.h index e397da80a5..04eccb12a9 100644 --- a/include/image.h +++ b/include/image.h @@ -40,11 +40,10 @@ struct fdt_region; #endif /* USE_HOSTCC */ -#if CONFIG_IS_ENABLED(FIT) #include #include #include -#endif /* FIT */ +#include extern ulong image_load_addr; /* Default Load Address */ extern ulong image_save_addr; /* Default Save Address */ @@ -504,8 +503,7 @@ int genimg_get_type_id(const char *name); int genimg_get_comp_id(const char *name); void genimg_print_size(uint32_t size); -#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \ - defined(USE_HOSTCC) +#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC) #define IMAGE_ENABLE_TIMESTAMP 1 #else #define IMAGE_ENABLE_TIMESTAMP 0 @@ -523,12 +521,9 @@ enum fit_load_op { int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start, ulong *setup_len); -#ifndef USE_HOSTCC /* Image format types, returned by _get_format() routine */ #define IMAGE_FORMAT_INVALID 0x00 -#if defined(CONFIG_LEGACY_IMAGE_FORMAT) #define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */ -#endif #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ #define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ @@ -567,7 +562,6 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, */ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, uint8_t arch, const ulong *ld_start, ulong *const ld_len); -#endif /* !USE_HOSTCC */ int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch, ulong *setup_start, ulong *setup_len); @@ -644,7 +638,6 @@ int fit_image_load(bootm_headers_t *images, ulong addr, */ int image_source_script(ulong addr, const char *fit_uname); -#ifndef USE_HOSTCC /** * fit_get_node_from_config() - Look up an image a FIT by type * @@ -684,10 +677,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size); int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end); int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end); -#ifdef CONFIG_SYS_BOOT_GET_KBD int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd); -#endif /* CONFIG_SYS_BOOT_GET_KBD */ -#endif /* !USE_HOSTCC */ /*******************************************************************/ /* Legacy format specific code (prefixed with image_) */ @@ -802,11 +792,9 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type) } static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) { -#ifndef USE_HOSTCC /* Let's assume that sandbox can load any architecture */ - if (IS_ENABLED(CONFIG_SANDBOX)) + if (!tools_build() && IS_ENABLED(CONFIG_SANDBOX)) return true; -#endif return (image_get_arch(hdr) == arch) || (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64); } @@ -954,7 +942,6 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE -#if CONFIG_IS_ENABLED(FIT) /* cmdline argument format parsing */ int fit_parse_conf(const char *spec, ulong addr_curr, ulong *addr, const char **conf_name); @@ -1128,7 +1115,6 @@ int fit_conf_get_prop_node(const void *fit, int noffset, int fit_check_ramdisk(const void *fit, int os_noffset, uint8_t arch, int verify); -#endif /* FIT */ int calculate_hash(const void *data, int data_len, const char *algo, uint8_t *value, int *value_len); @@ -1151,7 +1137,6 @@ int calculate_hash(const void *data, int data_len, const char *algo, # define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE) #endif -#if CONFIG_IS_ENABLED(FIT) #ifdef USE_HOSTCC void *image_get_host_blob(void); void image_set_host_blob(void *host_blob); @@ -1160,8 +1145,6 @@ void image_set_host_blob(void *host_blob); # define gd_fdt_blob() (gd->fdt_blob) #endif -#endif /* IMAGE_ENABLE_FIT */ - /* * Information passed to the signing routines * @@ -1198,9 +1181,6 @@ struct image_region { int size; }; -#if FIT_IMAGE_ENABLE_VERIFY -# include -#endif struct checksum_algo { const char *name; const int checksum_len; @@ -1210,7 +1190,7 @@ struct checksum_algo { const EVP_MD *(*calculate_sign)(void); #endif int (*calculate)(const char *name, - const struct image_region region[], + const struct image_region *region, int region_count, uint8_t *checksum); }; @@ -1306,8 +1286,6 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name); */ struct padding_algo *image_get_padding_algo(const char *name); -#if CONFIG_IS_ENABLED(FIT) - /** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' * @@ -1433,10 +1411,6 @@ int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); struct cipher_algo *image_get_cipher_algo(const char *full_name); -#endif /* CONFIG_FIT */ - -#if !defined(USE_HOSTCC) -#if defined(CONFIG_ANDROID_BOOT_IMAGE) struct andr_img_hdr; int android_image_check_header(const struct andr_img_hdr *hdr); int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, @@ -1452,12 +1426,7 @@ ulong android_image_get_end(const struct andr_img_hdr *hdr); ulong android_image_get_kload(const struct andr_img_hdr *hdr); ulong android_image_get_kcomp(const struct andr_img_hdr *hdr); void android_print_contents(const struct andr_img_hdr *hdr); -#if !defined(CONFIG_SPL_BUILD) bool android_image_print_dtb_contents(ulong hdr_addr); -#endif - -#endif /* CONFIG_ANDROID_BOOT_IMAGE */ -#endif /* !USE_HOSTCC */ /** * board_fit_config_name_match() - Check for a matching board name diff --git a/include/u-boot/hash-checksum.h b/include/u-boot/hash-checksum.h index 54e6a73744..7f16b37a9a 100644 --- a/include/u-boot/hash-checksum.h +++ b/include/u-boot/hash-checksum.h @@ -7,11 +7,12 @@ #define _RSA_CHECKSUM_H #include -#include #include #include #include +struct image_region; + /** * hash_calculate() - Calculate hash over the data * @@ -23,7 +24,7 @@ * @return 0 if OK, < 0 if error */ int hash_calculate(const char *name, - const struct image_region region[], int region_count, + const struct image_region *region, int region_count, uint8_t *checksum); #endif diff --git a/lib/hash-checksum.c b/lib/hash-checksum.c index d732ecc38f..8f2a42f9a0 100644 --- a/lib/hash-checksum.c +++ b/lib/hash-checksum.c @@ -17,7 +17,7 @@ #include int hash_calculate(const char *name, - const struct image_region region[], + const struct image_region *region, int region_count, uint8_t *checksum) { struct hash_algo *algo; From 78740bcce87518d2c71c96e41429c4e65f516635 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:34 -0600 Subject: [PATCH 108/228] image: Drop #ifdefs for fit_print_contents() Use a simple return to drop the unwanted code. Signed-off-by: Simon Glass --- common/image-fit.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/common/image-fit.c b/common/image-fit.c index f44f5527b9..1e4099d127 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -170,7 +170,6 @@ int fit_get_subimage_count(const void *fit, int images_noffset) return count; } -#if CONFIG_IS_ENABLED(FIT_PRINT) /** * fit_image_print_data() - prints out the hash node details * @fit: pointer to the FIT format image header @@ -380,6 +379,9 @@ void fit_print_contents(const void *fit) const char *p; time_t timestamp; + if (!CONFIG_IS_ENABLED(FIT_PRINT)) + return; + /* Indent string is defined in header image.h */ p = IMAGE_INDENT_STRING; @@ -482,6 +484,9 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) int ndepth; int ret; + if (!CONFIG_IS_ENABLED(FIT_PRINT)) + return; + /* Mandatory properties */ ret = fit_get_desc(fit, image_noffset, &desc); printf("%s Description: ", p); @@ -575,10 +580,6 @@ void fit_image_print(const void *fit, int image_noffset, const char *p) } } } -#else -void fit_print_contents(const void *fit) { } -void fit_image_print(const void *fit, int image_noffset, const char *p) { } -#endif /* CONFIG_IS_ENABLED(FIT_PRINT) */ /** * fit_get_desc - get node description property From 1df654a6af5b14731383039f868f12db7069a476 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:35 -0600 Subject: [PATCH 109/228] image: Drop most #ifdefs in image-board.c Remove ifdefs in this file, so far as possible without too much refactoring. Signed-off-by: Simon Glass --- common/image-board.c | 111 +++++++++++++++++++------------------------ include/image.h | 7 ++- 2 files changed, 55 insertions(+), 63 deletions(-) diff --git a/common/image-board.c b/common/image-board.c index 6565f014f7..4f3c98dc9b 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -227,16 +227,16 @@ ulong genimg_get_kernel_addr_fit(char * const img_addr, kernel_addr = image_load_addr; debug("* kernel: default image load address = 0x%08lx\n", image_load_addr); -#if CONFIG_IS_ENABLED(FIT) - } else if (fit_parse_conf(img_addr, image_load_addr, &kernel_addr, + } else if (CONFIG_IS_ENABLED(FIT) && + fit_parse_conf(img_addr, image_load_addr, &kernel_addr, fit_uname_config)) { debug("* kernel: config '%s' from image at 0x%08lx\n", *fit_uname_config, kernel_addr); - } else if (fit_parse_subimage(img_addr, image_load_addr, &kernel_addr, - fit_uname_kernel)) { + } else if (CONFIG_IS_ENABLED(FIT) && + fit_parse_subimage(img_addr, image_load_addr, &kernel_addr, + fit_uname_kernel)) { debug("* kernel: subimage '%s' from image at 0x%08lx\n", *fit_uname_kernel, kernel_addr); -#endif } else { kernel_addr = hextoul(img_addr, NULL); debug("* kernel: cmdline image address = 0x%08lx\n", @@ -275,21 +275,20 @@ ulong genimg_get_kernel_addr(char * const img_addr) */ int genimg_get_format(const void *img_addr) { -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - const image_header_t *hdr; + if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) { + const image_header_t *hdr; - hdr = (const image_header_t *)img_addr; - if (image_check_magic(hdr)) - return IMAGE_FORMAT_LEGACY; -#endif -#if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT) - if (fdt_check_header(img_addr) == 0) - return IMAGE_FORMAT_FIT; -#endif -#ifdef CONFIG_ANDROID_BOOT_IMAGE - if (android_image_check_header(img_addr) == 0) + hdr = (const image_header_t *)img_addr; + if (image_check_magic(hdr)) + return IMAGE_FORMAT_LEGACY; + } + if (CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT)) { + if (!fdt_check_header(img_addr)) + return IMAGE_FORMAT_FIT; + } + if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) && + !android_image_check_header(img_addr)) return IMAGE_FORMAT_ANDROID; -#endif return IMAGE_FORMAT_INVALID; } @@ -307,10 +306,9 @@ int genimg_get_format(const void *img_addr) */ int genimg_has_config(bootm_headers_t *images) { -#if CONFIG_IS_ENABLED(FIT) - if (images->fit_uname_cfg) + if (CONFIG_IS_ENABLED(FIT) && images->fit_uname_cfg) return 1; -#endif + return 0; } @@ -345,9 +343,6 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, const image_header_t *rd_hdr; #endif void *buf; -#ifdef CONFIG_SUPPORT_RAW_INITRD - char *end; -#endif #if CONFIG_IS_ENABLED(FIT) const char *fit_uname_config = images->fit_uname_cfg; const char *fit_uname_ramdisk = NULL; @@ -359,14 +354,12 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, *rd_start = 0; *rd_end = 0; -#ifdef CONFIG_ANDROID_BOOT_IMAGE - /* - * Look for an Android boot image. - */ - buf = map_sysmem(images->os.start, 0); - if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) - select = (argc == 0) ? env_get("loadaddr") : argv[0]; -#endif + if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { + /* Look for an Android boot image */ + buf = map_sysmem(images->os.start, 0); + if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) + select = (argc == 0) ? env_get("loadaddr") : argv[0]; + } if (argc >= 2) select = argv[1]; @@ -474,22 +467,22 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, break; #endif default: -#ifdef CONFIG_SUPPORT_RAW_INITRD - end = NULL; - if (select) - end = strchr(select, ':'); - if (end) { - rd_len = hextoul(++end, NULL); - rd_data = rd_addr; - } else -#endif - { - puts("Wrong Ramdisk Image Format\n"); - rd_data = 0; - rd_len = 0; - rd_load = 0; - return 1; + if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) { + char *end = NULL; + + if (select) + end = strchr(select, ':'); + if (end) { + rd_len = hextoul(++end, NULL); + rd_data = rd_addr; + break; + } } + puts("Wrong Ramdisk Image Format\n"); + rd_data = 0; + rd_len = 0; + rd_load = 0; + return 1; } } else if (images->legacy_hdr_valid && image_check_type(&images->legacy_hdr_os_copy, @@ -524,7 +517,6 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, return 0; } -#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH /** * boot_ramdisk_high - relocate init ramdisk * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -595,15 +587,15 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, memmove_wd((void *)*initrd_start, (void *)rd_data, rd_len, CHUNKSZ); -#ifdef CONFIG_MP /* * Ensure the image is flushed to memory to handle * AMP boot scenarios in which we might not be * HW cache coherent */ - flush_cache((unsigned long)*initrd_start, - ALIGN(rd_len, ARCH_DMA_MINALIGN)); -#endif + if (IS_ENABLED(CONFIG_MP)) { + flush_cache((unsigned long)*initrd_start, + ALIGN(rd_len, ARCH_DMA_MINALIGN)); + } puts("OK\n"); } } else { @@ -618,20 +610,16 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, error: return -1; } -#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ int boot_get_setup(bootm_headers_t *images, u8 arch, ulong *setup_start, ulong *setup_len) { -#if CONFIG_IS_ENABLED(FIT) + if (!CONFIG_IS_ENABLED(FIT)) + return -ENOENT; + return boot_get_setup_fit(images, arch, setup_start, setup_len); -#else - return -ENOENT; -#endif } -#if CONFIG_IS_ENABLED(FIT) -#if defined(CONFIG_FPGA) int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, u8 arch, const ulong *ld_start, ulong * const ld_len) { @@ -643,6 +631,9 @@ int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, int err; int devnum = 0; /* TODO support multi fpga platforms */ + if (!IS_ENABLED(CONFIG_FPGA)) + return -ENOSYS; + /* Check to see if the images struct has a FIT configuration */ if (!genimg_has_config(images)) { debug("## FIT configuration was not specified\n"); @@ -714,7 +705,6 @@ int boot_get_fpga(int argc, char *const argv[], bootm_headers_t *images, return 0; } -#endif static void fit_loadable_process(u8 img_type, ulong img_data, @@ -812,7 +802,6 @@ int boot_get_loadable(int argc, char *const argv[], bootm_headers_t *images, return 0; } -#endif /** * boot_get_cmdline - allocate and initialize kernel cmdline diff --git a/include/image.h b/include/image.h index 04eccb12a9..34d13ada84 100644 --- a/include/image.h +++ b/include/image.h @@ -298,7 +298,11 @@ typedef struct bootm_headers { image_header_t legacy_hdr_os_copy; /* header copy */ ulong legacy_hdr_valid; -#if CONFIG_IS_ENABLED(FIT) + /* + * The fit_ members are only used with FIT, but it involves a lot of + * #ifdefs to avoid compiling that code. Since FIT is the standard + * format, even for SPL, this extra data size seems worth it. + */ const char *fit_uname_cfg; /* configuration node unit name */ void *fit_hdr_os; /* os FIT image header */ @@ -316,7 +320,6 @@ typedef struct bootm_headers { void *fit_hdr_setup; /* x86 setup FIT image header */ const char *fit_uname_setup; /* x86 setup subimage node name */ int fit_noffset_setup;/* x86 setup subimage node offset */ -#endif #ifndef USE_HOSTCC image_info_t os; /* os image info */ From 78f88790e3f7693a1ee9a87cc53d79e959c5633f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:36 -0600 Subject: [PATCH 110/228] image: Reduce variable scope in boot_get_ramdisk() Move the variables declarations to where they are needed, to reduce the number of #ifdefs needed. Signed-off-by: Simon Glass --- common/image-board.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/common/image-board.c b/common/image-board.c index 4f3c98dc9b..131584a858 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -337,18 +337,8 @@ int genimg_has_config(bootm_headers_t *images) int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, u8 arch, ulong *rd_start, ulong *rd_end) { - ulong rd_addr, rd_load; ulong rd_data, rd_len; -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - const image_header_t *rd_hdr; -#endif void *buf; -#if CONFIG_IS_ENABLED(FIT) - const char *fit_uname_config = images->fit_uname_cfg; - const char *fit_uname_ramdisk = NULL; - ulong default_addr; - int rd_noffset; -#endif const char *select = NULL; *rd_start = 0; @@ -373,8 +363,15 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, rd_len = 0; rd_data = 0; } else if (select || genimg_has_config(images)) { + ulong rd_addr, rd_load; + #if CONFIG_IS_ENABLED(FIT) + const char *fit_uname_config = images->fit_uname_cfg; + const char *fit_uname_ramdisk = NULL; + int rd_noffset; + if (select) { + ulong default_addr; /* * If the init ramdisk comes from the FIT image and * the FIT image address is omitted in the command @@ -427,7 +424,9 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, buf = map_sysmem(rd_addr, 0); switch (genimg_get_format(buf)) { #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - case IMAGE_FORMAT_LEGACY: + case IMAGE_FORMAT_LEGACY: { + const image_header_t *rd_hdr; + printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n", rd_addr); @@ -442,6 +441,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, rd_len = image_get_data_size(rd_hdr); rd_load = image_get_load(rd_hdr); break; + } #endif #if CONFIG_IS_ENABLED(FIT) case IMAGE_FORMAT_FIT: From e4c928792e93ed87abb1633cc3f80c2d0a84dd4a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:37 -0600 Subject: [PATCH 111/228] image: Split up boot_get_ramdisk() This function is far too long. Before trying to remove #ifdefs, split out the code that deals with selecting the ramdisk into a separate function. Leave the code indented as it was for easier review. The next patch cleans this up along with checkpatch violations. Signed-off-by: Simon Glass --- common/image-board.c | 149 +++++++++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 63 deletions(-) diff --git a/common/image-board.c b/common/image-board.c index 131584a858..b693a5281f 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -313,57 +313,21 @@ int genimg_has_config(bootm_headers_t *images) } /** - * boot_get_ramdisk - main ramdisk handling routine - * @argc: command argument count - * @argv: command argument list + * select_ramdisk() - Select and locate the ramdisk to use + * * @images: pointer to the bootm images structure + * @select: name of ramdisk to select, or NULL for any * @arch: expected ramdisk architecture - * @rd_start: pointer to a ulong variable, will hold ramdisk start address - * @rd_end: pointer to a ulong variable, will hold ramdisk end - * - * boot_get_ramdisk() is responsible for finding a valid ramdisk image. - * Currently supported are the following ramdisk sources: - * - multicomponent kernel/ramdisk image, - * - commandline provided address of decicated ramdisk image. - * - * returns: - * 0, if ramdisk image was found and valid, or skiped - * rd_start and rd_end are set to ramdisk start/end addresses if - * ramdisk image is found and valid - * - * 1, if ramdisk image is found but corrupted, or invalid - * rd_start and rd_end are set to 0 if no ramdisk exists + * @rd_datap: pointer to a ulong variable, will hold ramdisk pointer + * @rd_lenp: pointer to a ulong variable, will hold ramdisk length + * @return 0 if OK, -ENOPKG if no ramdisk (but an error should not be reported), + * other -ve value on other error */ -int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, - u8 arch, ulong *rd_start, ulong *rd_end) +static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch, + ulong *rd_datap, ulong *rd_lenp) { - ulong rd_data, rd_len; - void *buf; - const char *select = NULL; - - *rd_start = 0; - *rd_end = 0; - - if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { - /* Look for an Android boot image */ - buf = map_sysmem(images->os.start, 0); - if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) - select = (argc == 0) ? env_get("loadaddr") : argv[0]; - } - - if (argc >= 2) - select = argv[1]; - - /* - * Look for a '-' which indicates to ignore the - * ramdisk argument - */ - if (select && strcmp(select, "-") == 0) { - debug("## Skipping init Ramdisk\n"); - rd_len = 0; - rd_data = 0; - } else if (select || genimg_has_config(images)) { - ulong rd_addr, rd_load; + ulong rd_addr; + char *buf; #if CONFIG_IS_ENABLED(FIT) const char *fit_uname_config = images->fit_uname_cfg; @@ -403,16 +367,16 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, } else { /* use FIT configuration provided in first bootm * command argument. If the property is not defined, - * quit silently. + * quit silently (with -ENOPKG) */ rd_addr = map_to_sysmem(images->fit_hdr_os); rd_noffset = fit_get_node_from_config(images, FIT_RAMDISK_PROP, rd_addr); if (rd_noffset == -ENOENT) - return 0; + return -ENOPKG; else if (rd_noffset < 0) - return 1; + return rd_noffset; } #endif @@ -435,11 +399,10 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, images->verify); if (!rd_hdr) - return 1; + return -ENOENT; - rd_data = image_get_data(rd_hdr); - rd_len = image_get_data_size(rd_hdr); - rd_load = image_get_load(rd_hdr); + *rd_datap = image_get_data(rd_hdr); + *rd_lenp = image_get_data_size(rd_hdr); break; } #endif @@ -451,9 +414,9 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, IH_TYPE_RAMDISK, BOOTSTAGE_ID_FIT_RD_START, FIT_LOAD_OPTIONAL_NON_ZERO, - &rd_data, &rd_len); + rd_datap, rd_lenp); if (rd_noffset < 0) - return 1; + return rd_noffset; images->fit_hdr_rd = map_sysmem(rd_addr, 0); images->fit_uname_rd = fit_uname_ramdisk; @@ -463,7 +426,7 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, #ifdef CONFIG_ANDROID_BOOT_IMAGE case IMAGE_FORMAT_ANDROID: android_image_get_ramdisk((void *)images->os.start, - &rd_data, &rd_len); + rd_datap, rd_lenp); break; #endif default: @@ -473,17 +436,77 @@ int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, if (select) end = strchr(select, ':'); if (end) { - rd_len = hextoul(++end, NULL); - rd_data = rd_addr; + *rd_lenp = hextoul(++end, NULL); + *rd_datap = rd_addr; break; } } puts("Wrong Ramdisk Image Format\n"); - rd_data = 0; - rd_len = 0; - rd_load = 0; - return 1; + return -EINVAL; } + + return 0; +} + +/** + * boot_get_ramdisk - main ramdisk handling routine + * @argc: command argument count + * @argv: command argument list + * @images: pointer to the bootm images structure + * @arch: expected ramdisk architecture + * @rd_start: pointer to a ulong variable, will hold ramdisk start address + * @rd_end: pointer to a ulong variable, will hold ramdisk end + * + * boot_get_ramdisk() is responsible for finding a valid ramdisk image. + * Currently supported are the following ramdisk sources: + * - multicomponent kernel/ramdisk image, + * - commandline provided address of decicated ramdisk image. + * + * returns: + * 0, if ramdisk image was found and valid, or skiped + * rd_start and rd_end are set to ramdisk start/end addresses if + * ramdisk image is found and valid + * + * 1, if ramdisk image is found but corrupted, or invalid + * rd_start and rd_end are set to 0 if no ramdisk exists + */ +int boot_get_ramdisk(int argc, char *const argv[], bootm_headers_t *images, + u8 arch, ulong *rd_start, ulong *rd_end) +{ + ulong rd_data, rd_len; + const char *select = NULL; + + *rd_start = 0; + *rd_end = 0; + + if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { + char *buf; + + /* Look for an Android boot image */ + buf = map_sysmem(images->os.start, 0); + if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) + select = (argc == 0) ? env_get("loadaddr") : argv[0]; + } + + if (argc >= 2) + select = argv[1]; + + /* + * Look for a '-' which indicates to ignore the + * ramdisk argument + */ + if (select && strcmp(select, "-") == 0) { + debug("## Skipping init Ramdisk\n"); + rd_len = 0; + rd_data = 0; + } else if (select || genimg_has_config(images)) { + int ret; + + ret = select_ramdisk(images, select, arch, &rd_data, &rd_len); + if (ret == -ENOPKG) + return 0; + else if (ret) + return ret; } else if (images->legacy_hdr_valid && image_check_type(&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) { From f33a2c1bd0fb371511a485cac1f182ba50db51be Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:38 -0600 Subject: [PATCH 112/228] image: Remove #ifdefs from select_ramdisk() Use boolean variables to deal with the strange #ifdef logic of this function, so we can remove the #ifdefs. Signed-off-by: Simon Glass --- common/image-board.c | 137 ++++++++++++++++++++++--------------------- 1 file changed, 71 insertions(+), 66 deletions(-) diff --git a/common/image-board.c b/common/image-board.c index b693a5281f..e7660352e9 100644 --- a/common/image-board.c +++ b/common/image-board.c @@ -26,7 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) /** * image_get_ramdisk - get and verify ramdisk image * @rd_addr: ramdisk image start address @@ -85,7 +84,6 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, u8 arch, return rd_hdr; } -#endif /*****************************************************************************/ /* Shared dual-format routines */ @@ -326,16 +324,18 @@ int genimg_has_config(bootm_headers_t *images) static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch, ulong *rd_datap, ulong *rd_lenp) { - ulong rd_addr; + ulong rd_addr = 0; char *buf; + const char *fit_uname_config = images->fit_uname_cfg; + const char *fit_uname_ramdisk = NULL; + bool processed; + int rd_noffset; -#if CONFIG_IS_ENABLED(FIT) - const char *fit_uname_config = images->fit_uname_cfg; - const char *fit_uname_ramdisk = NULL; - int rd_noffset; + if (select) { + ulong default_addr; + bool done = true; - if (select) { - ulong default_addr; + if (CONFIG_IS_ENABLED(FIT)) { /* * If the init ramdisk comes from the FIT image and * the FIT image address is omitted in the command @@ -347,8 +347,8 @@ static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch, else default_addr = image_load_addr; - if (fit_parse_conf(select, default_addr, - &rd_addr, &fit_uname_config)) { + if (fit_parse_conf(select, default_addr, &rd_addr, + &fit_uname_config)) { debug("* ramdisk: config '%s' from image at 0x%08lx\n", fit_uname_config, rd_addr); } else if (fit_parse_subimage(select, default_addr, @@ -356,60 +356,58 @@ static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch, &fit_uname_ramdisk)) { debug("* ramdisk: subimage '%s' from image at 0x%08lx\n", fit_uname_ramdisk, rd_addr); - } else -#endif - { - rd_addr = hextoul(select, NULL); - debug("* ramdisk: cmdline image address = 0x%08lx\n", - rd_addr); + } else { + done = false; } -#if CONFIG_IS_ENABLED(FIT) - } else { - /* use FIT configuration provided in first bootm - * command argument. If the property is not defined, - * quit silently (with -ENOPKG) - */ - rd_addr = map_to_sysmem(images->fit_hdr_os); - rd_noffset = fit_get_node_from_config(images, - FIT_RAMDISK_PROP, - rd_addr); - if (rd_noffset == -ENOENT) - return -ENOPKG; - else if (rd_noffset < 0) - return rd_noffset; } -#endif - - /* - * Check if there is an initrd image at the - * address provided in the second bootm argument - * check image type, for FIT images get FIT node. + if (!done) { + rd_addr = hextoul(select, NULL); + debug("* ramdisk: cmdline image address = 0x%08lx\n", + rd_addr); + } + } else if (CONFIG_IS_ENABLED(FIT)) { + /* use FIT configuration provided in first bootm + * command argument. If the property is not defined, + * quit silently (with -ENOPKG ) */ - buf = map_sysmem(rd_addr, 0); - switch (genimg_get_format(buf)) { -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - case IMAGE_FORMAT_LEGACY: { + rd_addr = map_to_sysmem(images->fit_hdr_os); + rd_noffset = fit_get_node_from_config(images, FIT_RAMDISK_PROP, + rd_addr); + if (rd_noffset == -ENOENT) + return -ENOPKG; + else if (rd_noffset < 0) + return rd_noffset; + } + + /* + * Check if there is an initrd image at the + * address provided in the second bootm argument + * check image type, for FIT images get FIT node. + */ + buf = map_sysmem(rd_addr, 0); + processed = false; + switch (genimg_get_format(buf)) { + case IMAGE_FORMAT_LEGACY: + if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) { const image_header_t *rd_hdr; printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n", rd_addr); bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK); - rd_hdr = image_get_ramdisk(rd_addr, arch, - images->verify); - + rd_hdr = image_get_ramdisk(rd_addr, arch, images->verify); if (!rd_hdr) return -ENOENT; *rd_datap = image_get_data(rd_hdr); *rd_lenp = image_get_data_size(rd_hdr); - break; + processed = true; } -#endif -#if CONFIG_IS_ENABLED(FIT) - case IMAGE_FORMAT_FIT: - rd_noffset = fit_image_load(images, - rd_addr, &fit_uname_ramdisk, + break; + case IMAGE_FORMAT_FIT: + if (CONFIG_IS_ENABLED(FIT)) { + rd_noffset = fit_image_load(images, rd_addr, + &fit_uname_ramdisk, &fit_uname_config, arch, IH_TYPE_RAMDISK, BOOTSTAGE_ID_FIT_RD_START, @@ -421,29 +419,36 @@ static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch, images->fit_hdr_rd = map_sysmem(rd_addr, 0); images->fit_uname_rd = fit_uname_ramdisk; images->fit_noffset_rd = rd_noffset; - break; -#endif -#ifdef CONFIG_ANDROID_BOOT_IMAGE - case IMAGE_FORMAT_ANDROID: + processed = true; + } + break; + case IMAGE_FORMAT_ANDROID: + if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { android_image_get_ramdisk((void *)images->os.start, rd_datap, rd_lenp); - break; -#endif - default: - if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) { - char *end = NULL; + processed = true; + } + break; + } - if (select) - end = strchr(select, ':'); - if (end) { - *rd_lenp = hextoul(++end, NULL); - *rd_datap = rd_addr; - break; - } + if (!processed) { + if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) { + char *end = NULL; + + if (select) + end = strchr(select, ':'); + if (end) { + *rd_lenp = hextoul(++end, NULL); + *rd_datap = rd_addr; + processed = true; } + } + + if (!processed) { puts("Wrong Ramdisk Image Format\n"); return -EINVAL; } + } return 0; } From b53541f7f61d506c6b19b30357f471472831e9cb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:39 -0600 Subject: [PATCH 113/228] image: Remove some #ifdefs from image-fit and image-fit-sig Drop the #ifdefs which are easy to remove without refactoring. Signed-off-by: Simon Glass --- common/Kconfig.boot | 10 ++++++++++ common/image-fit-sig.c | 8 ++------ common/image-fit.c | 7 ++++--- 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/common/Kconfig.boot b/common/Kconfig.boot index f23b998852..9b84a8d005 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -165,6 +165,16 @@ config SPL_FIT_SIGNATURE select SPL_IMAGE_SIGN_INFO select SPL_FIT_FULL_CHECK +config SPL_FIT_SIGNATURE_MAX_SIZE + hex "Max size of signed FIT structures in SPL" + depends on SPL_FIT_SIGNATURE + default 0x10000000 + help + This option sets a max size in bytes for verified FIT uImages. + A sane value of 256MB protects corrupted DTB structures from overlapping + device memory. Assure this size does not extend past expected storage + space. + config SPL_LOAD_FIT bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)" select SPL_FIT diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c index e95e64bd2f..4edebbf2d3 100644 --- a/common/image-fit-sig.c +++ b/common/image-fit-sig.c @@ -49,10 +49,8 @@ struct image_region *fit_region_make_list(const void *fit, * Use malloc() except in SPL (to save code size). In SPL the caller * must allocate the array. */ -#ifndef CONFIG_SPL_BUILD - if (!region) + if (!IS_ENABLED(CONFIG_SPL_BUILD) && !region) region = calloc(sizeof(*region), count); -#endif if (!region) return NULL; for (i = 0; i < count; i++) { @@ -72,12 +70,10 @@ static int fit_image_setup_verify(struct image_sign_info *info, char *algo_name; const char *padding_name; -#ifndef USE_HOSTCC - if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) { + if (fdt_totalsize(fit) > CONFIG_VAL(FIT_SIGNATURE_MAX_SIZE)) { *err_msgp = "Total size too large"; return 1; } -#endif if (fit_image_hash_get_algo(fit, noffset, &algo_name)) { *err_msgp = "Can't get hash algo property"; return -1; diff --git a/common/image-fit.c b/common/image-fit.c index 1e4099d127..33b4a46028 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -2009,9 +2009,6 @@ int fit_image_load(bootm_headers_t *images, ulong addr, int type_ok, os_ok; ulong load, load_end, data, len; uint8_t os, comp; -#ifndef USE_HOSTCC - uint8_t os_arch; -#endif const char *prop_name; int ret; @@ -2103,8 +2100,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr, } #ifndef USE_HOSTCC + { + uint8_t os_arch; + fit_image_get_arch(fit, noffset, &os_arch); images->os.arch = os_arch; + } #endif bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL); From a2198cd0185904929d90a1a814d7e0b47877e46b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:40 -0600 Subject: [PATCH 114/228] image: Reduce variable scope in boot_get_fdt() Move the variables declarations to where they are needed, to reduce the number of #ifdefs needed. Signed-off-by: Simon Glass --- common/image-fdt.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index abea17bd56..58c8936c98 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -276,21 +276,10 @@ error: int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, bootm_headers_t *images, char **of_flat_tree, ulong *of_size) { -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - const image_header_t *fdt_hdr; - ulong load, load_end; - ulong image_start, image_data, image_end; -#endif ulong img_addr; ulong fdt_addr; char *fdt_blob = NULL; void *buf; -#if CONFIG_IS_ENABLED(FIT) - const char *fit_uname_config = images->fit_uname_cfg; - const char *fit_uname_fdt = NULL; - ulong default_addr; - int fdt_noffset; -#endif const char *select = NULL; *of_flat_tree = NULL; @@ -304,6 +293,11 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, select = argv[2]; if (select || genimg_has_config(images)) { #if CONFIG_IS_ENABLED(FIT) + const char *fit_uname_config = images->fit_uname_cfg; + const char *fit_uname_fdt = NULL; + ulong default_addr; + int fdt_noffset; + if (select) { /* * If the FDT blob comes from the FIT image and the @@ -359,7 +353,11 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, buf = map_sysmem(fdt_addr, 0); switch (genimg_get_format(buf)) { #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - case IMAGE_FORMAT_LEGACY: + case IMAGE_FORMAT_LEGACY: { + const image_header_t *fdt_hdr; + ulong load, load_end; + ulong image_start, image_data, image_end; + /* verify fdt_addr points to a valid image header */ printf("## Flattened Device Tree from Legacy Image at %08lx\n", fdt_addr); @@ -398,6 +396,7 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, fdt_addr = load; break; + } #endif case IMAGE_FORMAT_FIT: /* From 4cb35b7a1fdf060a0839b71f6dbf8d08b1ae62e0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 25 Sep 2021 19:43:41 -0600 Subject: [PATCH 115/228] image: Split up boot_get_fdt() This function is far too long. Before trying to remove #ifdefs, split out the code that deals with selecting the FDT into a separate function. Signed-off-by: Simon Glass --- common/image-fdt.c | 324 ++++++++++++++++++++++++--------------------- 1 file changed, 175 insertions(+), 149 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 58c8936c98..7aad6d57b8 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -251,6 +251,173 @@ error: return 1; } +/** + * select_fdt() - Select and locate the FDT to use + * + * @images: pointer to the bootm images structure + * @select: name of FDT to select, or NULL for any + * @arch: expected FDT architecture + * @fdt_addrp: pointer to a ulong variable, will hold FDT pointer + * @return 0 if OK, -ENOPKG if no FDT (but an error should not be reported), + * other -ve value on other error + */ + +static int select_fdt(bootm_headers_t *images, const char *select, u8 arch, + ulong *fdt_addrp) +{ + const char *buf; + ulong fdt_addr; + +#if CONFIG_IS_ENABLED(FIT) + const char *fit_uname_config = images->fit_uname_cfg; + const char *fit_uname_fdt = NULL; + ulong default_addr; + int fdt_noffset; + + if (select) { + /* + * If the FDT blob comes from the FIT image and the + * FIT image address is omitted in the command line + * argument, try to use ramdisk or os FIT image + * address or default load address. + */ + if (images->fit_uname_rd) + default_addr = (ulong)images->fit_hdr_rd; + else if (images->fit_uname_os) + default_addr = (ulong)images->fit_hdr_os; + else + default_addr = image_load_addr; + + if (fit_parse_conf(select, default_addr, &fdt_addr, + &fit_uname_config)) { + debug("* fdt: config '%s' from image at 0x%08lx\n", + fit_uname_config, fdt_addr); + } else if (fit_parse_subimage(select, default_addr, &fdt_addr, + &fit_uname_fdt)) { + debug("* fdt: subimage '%s' from image at 0x%08lx\n", + fit_uname_fdt, fdt_addr); + } else +#endif + { + fdt_addr = hextoul(select, NULL); + debug("* fdt: cmdline image address = 0x%08lx\n", + fdt_addr); + } +#if CONFIG_IS_ENABLED(FIT) + } else { + /* use FIT configuration provided in first bootm + * command argument + */ + fdt_addr = map_to_sysmem(images->fit_hdr_os); + fdt_noffset = fit_get_node_from_config(images, FIT_FDT_PROP, + fdt_addr); + if (fdt_noffset == -ENOENT) + return -ENOPKG; + else if (fdt_noffset < 0) + return fdt_noffset; + } +#endif + debug("## Checking for 'FDT'/'FDT Image' at %08lx\n", + fdt_addr); + + /* + * Check if there is an FDT image at the + * address provided in the second bootm argument + * check image type, for FIT images get a FIT node. + */ + buf = map_sysmem(fdt_addr, 0); + switch (genimg_get_format(buf)) { +#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) + case IMAGE_FORMAT_LEGACY: { + const image_header_t *fdt_hdr; + ulong load, load_end; + ulong image_start, image_data, image_end; + + /* verify fdt_addr points to a valid image header */ + printf("## Flattened Device Tree from Legacy Image at %08lx\n", + fdt_addr); + fdt_hdr = image_get_fdt(fdt_addr); + if (!fdt_hdr) + return -ENOPKG; + + /* + * move image data to the load address, + * make sure we don't overwrite initial image + */ + image_start = (ulong)fdt_hdr; + image_data = (ulong)image_get_data(fdt_hdr); + image_end = image_get_image_end(fdt_hdr); + + load = image_get_load(fdt_hdr); + load_end = load + image_get_data_size(fdt_hdr); + + if (load == image_start || + load == image_data) { + fdt_addr = load; + break; + } + + if ((load < image_end) && (load_end > image_start)) { + fdt_error("fdt overwritten"); + return -EFAULT; + } + + debug(" Loading FDT from 0x%08lx to 0x%08lx\n", + image_data, load); + + memmove((void *)load, + (void *)image_data, + image_get_data_size(fdt_hdr)); + + fdt_addr = load; + break; + } +#endif + case IMAGE_FORMAT_FIT: + /* + * This case will catch both: new uImage format + * (libfdt based) and raw FDT blob (also libfdt + * based). + */ +#if CONFIG_IS_ENABLED(FIT) + /* check FDT blob vs FIT blob */ + if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) { + ulong load, len; + + fdt_noffset = boot_get_fdt_fit(images, fdt_addr, + &fit_uname_fdt, + &fit_uname_config, + arch, &load, &len); + + if (fdt_noffset < 0) + return -ENOENT; + + images->fit_hdr_fdt = map_sysmem(fdt_addr, 0); + images->fit_uname_fdt = fit_uname_fdt; + images->fit_noffset_fdt = fdt_noffset; + fdt_addr = load; + + break; + } else +#endif + { + /* + * FDT blob + */ + debug("* fdt: raw FDT blob\n"); + printf("## Flattened Device Tree blob at %08lx\n", + (long)fdt_addr); + } + break; + default: + puts("ERROR: Did not find a cmdline Flattened Device Tree\n"); + return -ENOENT; + } + *fdt_addrp = fdt_addr; + + return 0; +} + /** * boot_get_fdt - main fdt handling routine * @argc: command argument count @@ -261,7 +428,7 @@ error: * @of_size: pointer to a ulong variable, will hold fdt length * * boot_get_fdt() is responsible for finding a valid flat device tree image. - * Curently supported are the following ramdisk sources: + * Currently supported are the following ramdisk sources: * - multicomponent kernel/ramdisk image, * - commandline provided address of decicated ramdisk image. * @@ -285,160 +452,19 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, *of_flat_tree = NULL; *of_size = 0; - img_addr = (argc == 0) ? image_load_addr : - hextoul(argv[0], NULL); + img_addr = (argc == 0) ? image_load_addr : hextoul(argv[0], NULL); buf = map_sysmem(img_addr, 0); if (argc > 2) select = argv[2]; if (select || genimg_has_config(images)) { -#if CONFIG_IS_ENABLED(FIT) - const char *fit_uname_config = images->fit_uname_cfg; - const char *fit_uname_fdt = NULL; - ulong default_addr; - int fdt_noffset; - - if (select) { - /* - * If the FDT blob comes from the FIT image and the - * FIT image address is omitted in the command line - * argument, try to use ramdisk or os FIT image - * address or default load address. - */ - if (images->fit_uname_rd) - default_addr = (ulong)images->fit_hdr_rd; - else if (images->fit_uname_os) - default_addr = (ulong)images->fit_hdr_os; - else - default_addr = image_load_addr; - - if (fit_parse_conf(select, default_addr, - &fdt_addr, &fit_uname_config)) { - debug("* fdt: config '%s' from image at 0x%08lx\n", - fit_uname_config, fdt_addr); - } else if (fit_parse_subimage(select, default_addr, - &fdt_addr, &fit_uname_fdt)) { - debug("* fdt: subimage '%s' from image at 0x%08lx\n", - fit_uname_fdt, fdt_addr); - } else -#endif - { - fdt_addr = hextoul(select, NULL); - debug("* fdt: cmdline image address = 0x%08lx\n", - fdt_addr); - } -#if CONFIG_IS_ENABLED(FIT) - } else { - /* use FIT configuration provided in first bootm - * command argument - */ - fdt_addr = map_to_sysmem(images->fit_hdr_os); - fdt_noffset = fit_get_node_from_config(images, - FIT_FDT_PROP, - fdt_addr); - if (fdt_noffset == -ENOENT) - return 0; - else if (fdt_noffset < 0) - return 1; - } -#endif - debug("## Checking for 'FDT'/'FDT Image' at %08lx\n", - fdt_addr); - - /* - * Check if there is an FDT image at the - * address provided in the second bootm argument - * check image type, for FIT images get a FIT node. - */ - buf = map_sysmem(fdt_addr, 0); - switch (genimg_get_format(buf)) { -#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) - case IMAGE_FORMAT_LEGACY: { - const image_header_t *fdt_hdr; - ulong load, load_end; - ulong image_start, image_data, image_end; - - /* verify fdt_addr points to a valid image header */ - printf("## Flattened Device Tree from Legacy Image at %08lx\n", - fdt_addr); - fdt_hdr = image_get_fdt(fdt_addr); - if (!fdt_hdr) - goto no_fdt; - - /* - * move image data to the load address, - * make sure we don't overwrite initial image - */ - image_start = (ulong)fdt_hdr; - image_data = (ulong)image_get_data(fdt_hdr); - image_end = image_get_image_end(fdt_hdr); - - load = image_get_load(fdt_hdr); - load_end = load + image_get_data_size(fdt_hdr); - - if (load == image_start || - load == image_data) { - fdt_addr = load; - break; - } - - if ((load < image_end) && (load_end > image_start)) { - fdt_error("fdt overwritten"); - goto error; - } - - debug(" Loading FDT from 0x%08lx to 0x%08lx\n", - image_data, load); - - memmove((void *)load, - (void *)image_data, - image_get_data_size(fdt_hdr)); - - fdt_addr = load; - break; - } -#endif - case IMAGE_FORMAT_FIT: - /* - * This case will catch both: new uImage format - * (libfdt based) and raw FDT blob (also libfdt - * based). - */ -#if CONFIG_IS_ENABLED(FIT) - /* check FDT blob vs FIT blob */ - if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) { - ulong load, len; - - fdt_noffset = boot_get_fdt_fit(images, - fdt_addr, &fit_uname_fdt, - &fit_uname_config, - arch, &load, &len); - - if (fdt_noffset < 0) - goto error; - - images->fit_hdr_fdt = map_sysmem(fdt_addr, 0); - images->fit_uname_fdt = fit_uname_fdt; - images->fit_noffset_fdt = fdt_noffset; - fdt_addr = load; - - break; - } else -#endif - { - /* - * FDT blob - */ - debug("* fdt: raw FDT blob\n"); - printf("## Flattened Device Tree blob at %08lx\n", - (long)fdt_addr); - } - break; - default: - puts("ERROR: Did not find a cmdline Flattened Device Tree\n"); - goto error; - } + int ret; + ret = select_fdt(images, select, arch, &fdt_addr); + if (ret == -ENOPKG) + goto no_fdt; + else if (ret) + return 1; printf(" Booting using the fdt blob at %#08lx\n", fdt_addr); fdt_blob = map_sysmem(fdt_addr, 0); } else if (images->legacy_hdr_valid && From 0efe41ca158ef5b0e4457b4265f48860f382f3f8 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 25 Sep 2021 22:47:36 +0200 Subject: [PATCH 116/228] video: Add 30bpp support Add support for 30bpp mode where pixels are picked in 32-bit integers but use 10 bits instead of 8 bits for each component. Signed-off-by: Mark Kettenis --- drivers/video/vidconsole-uclass.c | 11 ++++++++--- include/video.h | 9 +++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 8132efa55a..f42db40d4c 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -155,9 +155,14 @@ u32 vid_console_color(struct video_priv *priv, unsigned int idx) break; case VIDEO_BPP32: if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { - return (colors[idx].r << 16) | - (colors[idx].g << 8) | - (colors[idx].b << 0); + if (priv->format == VIDEO_X2R10G10B10) + return (colors[idx].r << 22) | + (colors[idx].g << 12) | + (colors[idx].b << 2); + else + return (colors[idx].r << 16) | + (colors[idx].g << 8) | + (colors[idx].b << 0); } break; default: diff --git a/include/video.h b/include/video.h index 827733305e..f14fb15f84 100644 --- a/include/video.h +++ b/include/video.h @@ -64,6 +64,13 @@ enum video_log2_bpp { #define VNBITS(bpix) (1 << (bpix)) +enum video_format { + VIDEO_UNKNOWN, + VIDEO_X8B8G8R8, + VIDEO_X8R8G8B8, + VIDEO_X2R10G10B10, +}; + /** * struct video_priv - Device information used by the video uclass * @@ -71,6 +78,7 @@ enum video_log2_bpp { * @ysize: Number of pixels rows (e.g.. 768) * @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.) * @bpix: Encoded bits per pixel (enum video_log2_bpp) + * @format: Pixel format (enum video_format) * @vidconsole_drv_name: Driver to use for the text console, NULL to * select automatically * @font_size: Font size in pixels (0 to use a default value) @@ -95,6 +103,7 @@ struct video_priv { ushort ysize; ushort rot; enum video_log2_bpp bpix; + enum video_format format; const char *vidconsole_drv_name; int font_size; From 01fcf0eea634c727980a8b7d2d08c61fe7f142d9 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 25 Sep 2021 22:47:37 +0200 Subject: [PATCH 117/228] efi_loader: GOP: Add 30bpp support Provide correct framebuffer information for 30bpp modes. Signed-off-by: Mark Kettenis --- lib/efi_loader/efi_gop.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 1206b2d7a2..5033a2c9e3 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -432,7 +432,7 @@ efi_status_t EFIAPI gop_blt(struct efi_gop *this, struct efi_gop_pixel *buffer, efi_status_t efi_gop_register(void) { struct efi_gop_obj *gopobj; - u32 bpix, col, row; + u32 bpix, format, col, row; u64 fb_base, fb_size; void *fb; efi_status_t ret; @@ -449,6 +449,7 @@ efi_status_t efi_gop_register(void) priv = dev_get_uclass_priv(vdev); bpix = priv->bpix; + format = priv->format; col = video_get_xsize(vdev); row = video_get_ysize(vdev); fb_base = (uintptr_t)priv->fb; @@ -458,6 +459,7 @@ efi_status_t efi_gop_register(void) int line_len; bpix = panel_info.vl_bpix; + format = VIDEO_UNKNOWN; col = panel_info.vl_col; row = panel_info.vl_row; fb_base = gd->fb_base; @@ -517,7 +519,15 @@ efi_status_t efi_gop_register(void) if (bpix == LCD_COLOR32) #endif { - gopobj->info.pixel_format = EFI_GOT_BGRA8; + if (format == VIDEO_X2R10G10B10) { + gopobj->info.pixel_format = EFI_GOT_BITMASK; + gopobj->info.pixel_bitmask[0] = 0x3ff00000; /* red */ + gopobj->info.pixel_bitmask[1] = 0x000ffc00; /* green */ + gopobj->info.pixel_bitmask[2] = 0x000003ff; /* blue */ + gopobj->info.pixel_bitmask[3] = 0xc0000000; /* reserved */ + } else { + gopobj->info.pixel_format = EFI_GOT_BGRA8; + } } else { gopobj->info.pixel_format = EFI_GOT_BITMASK; gopobj->info.pixel_bitmask[0] = 0xf800; /* red */ From 2c2653d6f98eef645420f170869181710955a166 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 25 Sep 2021 22:47:38 +0200 Subject: [PATCH 118/228] video: simplefb: Add 30bpp support Recognize the canonical format strings for framebuffers in 30bpp mode and 32/24bpp mode. Signed-off-by: Mark Kettenis --- drivers/video/simplefb.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index fd58426cf5..2b0d8835e3 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -50,8 +50,18 @@ static int simple_video_probe(struct udevice *dev) if (strcmp(format, "r5g6b5") == 0) { uc_priv->bpix = VIDEO_BPP16; - } else if (strcmp(format, "a8b8g8r8") == 0) { + } else if (strcmp(format, "a8b8g8r8") == 0 || + strcmp(format, "x8b8g8r8") == 0) { uc_priv->bpix = VIDEO_BPP32; + uc_priv->format = VIDEO_X8B8G8R8; + } else if (strcmp(format, "a8r8g8b8") == 0 || + strcmp(format, "x8r8g8b8") == 0) { + uc_priv->bpix = VIDEO_BPP32; + uc_priv->format = VIDEO_X8R8G8B8; + } else if (strcmp(format, "a2r10g10b10") == 0 || + strcmp(format, "x2r10g10b10") == 0) { + uc_priv->bpix = VIDEO_BPP32; + uc_priv->format = VIDEO_X2R10G10B10; } else { printf("%s: invalid format: %s\n", __func__, format); return -EINVAL; From 79f9defeba7069fe3501086be54ba1aa3a821e07 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 25 Sep 2021 22:47:39 +0200 Subject: [PATCH 119/228] efi_loader: GOP: Fix 30bpp block transfer support Convert pixel values when necessary like we do for 16bpp framebuffers. Signed-off-by: Mark Kettenis Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_gop.c | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 5033a2c9e3..7683a34a96 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -64,6 +64,27 @@ out: return EFI_EXIT(ret); } +static __always_inline struct efi_gop_pixel efi_vid30_to_blt_col(u32 vid) +{ + struct efi_gop_pixel blt = { + .reserved = 0, + }; + + blt.blue = (vid & 0x3ff) >> 2; + vid >>= 10; + blt.green = (vid & 0x3ff) >> 2; + vid >>= 10; + blt.red = (vid & 0x3ff) >> 2; + return blt; +} + +static __always_inline u32 efi_blt_col_to_vid30(struct efi_gop_pixel *blt) +{ + return (u32)(blt->red << 2) << 20 | + (u32)(blt->green << 2) << 10 | + (u32)(blt->blue << 2); +} + static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid) { struct efi_gop_pixel blt = { @@ -191,6 +212,9 @@ static __always_inline efi_status_t gop_blt_int(struct efi_gop *this, if (vid_bpp == 32) pix = *(struct efi_gop_pixel *)&fb32[ slineoff + j + sx]; + else if (vid_bpp == 30) + pix = efi_vid30_to_blt_col(fb32[ + slineoff + j + sx]); else pix = efi_vid16_to_blt_col(fb16[ slineoff + j + sx]); @@ -207,6 +231,9 @@ static __always_inline efi_status_t gop_blt_int(struct efi_gop *this, case EFI_BLT_VIDEO_TO_VIDEO: if (vid_bpp == 32) fb32[dlineoff + j + dx] = *(u32 *)&pix; + else if (vid_bpp == 30) + fb32[dlineoff + j + dx] = + efi_blt_col_to_vid30(&pix); else fb16[dlineoff + j + dx] = efi_blt_col_to_vid16(&pix); @@ -231,7 +258,10 @@ static efi_uintn_t gop_get_bpp(struct efi_gop *this) #else case LCD_COLOR32: #endif - vid_bpp = 32; + if (gopobj->info.pixel_format == EFI_GOT_BGRA8) + vid_bpp = 32; + else + vid_bpp = 30; break; #ifdef CONFIG_DM_VIDEO case VIDEO_BPP16: @@ -277,6 +307,17 @@ static efi_status_t gop_blt_buf_to_vid16(struct efi_gop *this, dy, width, height, delta, 16); } +static efi_status_t gop_blt_buf_to_vid30(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 foo, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta) +{ + return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx, + dy, width, height, delta, 30); +} + static efi_status_t gop_blt_buf_to_vid32(struct efi_gop *this, struct efi_gop_pixel *buffer, u32 foo, efi_uintn_t sx, @@ -394,6 +435,10 @@ efi_status_t EFIAPI gop_blt(struct efi_gop *this, struct efi_gop_pixel *buffer, ret = gop_blt_buf_to_vid32(this, buffer, operation, sx, sy, dx, dy, width, height, delta); + else if (vid_bpp == 30) + ret = gop_blt_buf_to_vid30(this, buffer, operation, sx, + sy, dx, dy, width, height, + delta); else ret = gop_blt_buf_to_vid16(this, buffer, operation, sx, sy, dx, dy, width, height, From 2a2d8e94ddc75c2c8d456e9163aa5dac510badcf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 9 Oct 2021 09:28:21 -0600 Subject: [PATCH 120/228] lz4: Use a private header for U-Boot At present U-Boot has a header file called lz4.h for its own use. If the host has its own lz4 header file installed (e.g. from the 'liblz4-dev' package) then host builds will use that instead. Move the U-Boot file into its own directory, as is done with various other headers with the same problem. Signed-off-by: Simon Glass --- cmd/unlz4.c | 2 +- common/image.c | 2 +- include/{ => u-boot}/lz4.h | 0 lib/lz4_wrapper.c | 2 +- test/compression.c | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename include/{ => u-boot}/lz4.h (100%) diff --git a/cmd/unlz4.c b/cmd/unlz4.c index 323ab46717..5f20838e89 100644 --- a/cmd/unlz4.c +++ b/cmd/unlz4.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/common/image.c b/common/image.c index 5b77113bea..3fa60b5827 100644 --- a/common/image.c +++ b/common/image.c @@ -61,7 +61,6 @@ DECLARE_GLOBAL_DATA_PTR; #include #include #include -#include #include #include #include @@ -71,6 +70,7 @@ DECLARE_GLOBAL_DATA_PTR; #include #include #include +#include static const table_entry_t uimage_arch[] = { { IH_ARCH_INVALID, "invalid", "Invalid ARCH", }, diff --git a/include/lz4.h b/include/u-boot/lz4.h similarity index 100% rename from include/lz4.h rename to include/u-boot/lz4.h diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c index cdbcd05bd4..ebcb5c09a2 100644 --- a/lib/lz4_wrapper.c +++ b/lib/lz4_wrapper.c @@ -6,10 +6,10 @@ #include #include #include -#include #include #include #include +#include static u16 LZ4_readLE16(const void *src) { diff --git a/test/compression.c b/test/compression.c index 4cd1be564f..26d3c80fb5 100644 --- a/test/compression.c +++ b/test/compression.c @@ -9,11 +9,11 @@ #include #include #include -#include #include #include #include +#include #include #include From de99e776b88617a112e0ec6c01da9a0274362f5c Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 4 Oct 2021 16:04:32 +0200 Subject: [PATCH 121/228] common: Kconfig: use 'vidconsole' name instead of old 'video' After DM_VIDEO conversion the 'vidconsole' is the correct name for the frame buffer console. 'video' will not work, so update the description of the config option. Signed-off-by: Anatolij Gustschin --- common/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index 0543b839d1..d6f77ab7b9 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -182,8 +182,8 @@ config SYS_CONSOLE_IS_IN_ENV default y if CONSOLE_MUX help This allows multiple input/output devices to be set at boot time. - For example, if stdout is set to "serial,video" then output will - be sent to both the serial and video devices on boot. The + For example, if stdout is set to "serial,vidconsole" then output + will be sent to both the serial and video devices on boot. The environment variables can be updated after boot to change the input/output devices. From 450d937812c2419b830bb418f86594577809d02e Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 4 Oct 2021 17:07:14 +0200 Subject: [PATCH 122/228] video: remove not used mx3fb driver i.MX31 support was removed, and the non dm-video driver is obsolete and not used. Remove it. Signed-off-by: Anatolij Gustschin --- drivers/video/Makefile | 1 - drivers/video/cfb_console.c | 7 - drivers/video/mx3fb.c | 906 ------------------------------------ 3 files changed, 914 deletions(-) delete mode 100644 drivers/video/mx3fb.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f6d07b343f..8956b5f9b0 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -61,7 +61,6 @@ obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o -obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/ obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 566fc1e01a..7aa6f17d61 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -82,13 +82,6 @@ #define VIDEO_FB_16BPP_WORD_SWAP #endif -/* - * Defines for the i.MX31 driver (mx3fb.c) - */ -#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3) -#define VIDEO_FB_16BPP_WORD_SWAP -#endif - /* * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc. */ diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c deleted file mode 100644 index e6dd2b83c6..0000000000 --- a/drivers/video/mx3fb.c +++ /dev/null @@ -1,906 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, - * Copyright (C) 2011 - * HALE electronic GmbH, - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "videomodes.h" - -/* this might need panel specific set-up as-well */ -#define IF_CONF 0 - -/* -------------- controller specific stuff -------------- */ - -/* IPU DMA Controller channel definitions. */ -enum ipu_channel { - IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ - IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ - IDMAC_ADC_0 = 1, - IDMAC_IC_2 = 2, - IDMAC_ADC_1 = 2, - IDMAC_IC_3 = 3, - IDMAC_IC_4 = 4, - IDMAC_IC_5 = 5, - IDMAC_IC_6 = 6, - IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ - IDMAC_IC_8 = 8, - IDMAC_IC_9 = 9, - IDMAC_IC_10 = 10, - IDMAC_IC_11 = 11, - IDMAC_IC_12 = 12, - IDMAC_IC_13 = 13, - IDMAC_SDC_0 = 14, /* Background synchronous display data */ - IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ - IDMAC_SDC_2 = 16, - IDMAC_SDC_3 = 17, - IDMAC_ADC_2 = 18, - IDMAC_ADC_3 = 19, - IDMAC_ADC_4 = 20, - IDMAC_ADC_5 = 21, - IDMAC_ADC_6 = 22, - IDMAC_ADC_7 = 23, - IDMAC_PF_0 = 24, - IDMAC_PF_1 = 25, - IDMAC_PF_2 = 26, - IDMAC_PF_3 = 27, - IDMAC_PF_4 = 28, - IDMAC_PF_5 = 29, - IDMAC_PF_6 = 30, - IDMAC_PF_7 = 31, -}; - -/* More formats can be copied from the Linux driver if needed */ -enum pixel_fmt { - /* 2 bytes */ - IPU_PIX_FMT_RGB565, - IPU_PIX_FMT_RGB666, - IPU_PIX_FMT_BGR666, - /* 3 bytes */ - IPU_PIX_FMT_RGB24, -}; - -struct pixel_fmt_cfg { - u32 b0; - u32 b1; - u32 b2; - u32 acc; -}; - -static struct pixel_fmt_cfg fmt_cfg[] = { - [IPU_PIX_FMT_RGB24] = { - 0x1600AAAA, 0x00E05555, 0x00070000, 3, - }, - [IPU_PIX_FMT_RGB666] = { - 0x0005000F, 0x000B000F, 0x0011000F, 1, - }, - [IPU_PIX_FMT_BGR666] = { - 0x0011000F, 0x000B000F, 0x0005000F, 1, - }, - [IPU_PIX_FMT_RGB565] = { - 0x0004003F, 0x000A000F, 0x000F003F, 1, - } -}; - -enum ipu_panel { - IPU_PANEL_SHARP_TFT, - IPU_PANEL_TFT, -}; - -/* IPU Common registers */ -/* IPU_CONF and its bits already defined in imx-regs.h */ -#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) -#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) -#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) -#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) -#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) -#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) -#define IPU_TASKS_STAT (0x1C + IPU_BASE) -#define IPU_IMA_ADDR (0x20 + IPU_BASE) -#define IPU_IMA_DATA (0x24 + IPU_BASE) -#define IPU_INT_CTRL_1 (0x28 + IPU_BASE) -#define IPU_INT_CTRL_2 (0x2C + IPU_BASE) -#define IPU_INT_CTRL_3 (0x30 + IPU_BASE) -#define IPU_INT_CTRL_4 (0x34 + IPU_BASE) -#define IPU_INT_CTRL_5 (0x38 + IPU_BASE) -#define IPU_INT_STAT_1 (0x3C + IPU_BASE) -#define IPU_INT_STAT_2 (0x40 + IPU_BASE) -#define IPU_INT_STAT_3 (0x44 + IPU_BASE) -#define IPU_INT_STAT_4 (0x48 + IPU_BASE) -#define IPU_INT_STAT_5 (0x4C + IPU_BASE) -#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) -#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) -#define IPU_BRK_STAT (0x58 + IPU_BASE) -#define IPU_DIAGB_CTRL (0x5C + IPU_BASE) - -/* Image Converter Registers */ -#define IC_CONF (0x88 + IPU_BASE) -#define IC_PRP_ENC_RSC (0x8C + IPU_BASE) -#define IC_PRP_VF_RSC (0x90 + IPU_BASE) -#define IC_PP_RSC (0x94 + IPU_BASE) -#define IC_CMBP_1 (0x98 + IPU_BASE) -#define IC_CMBP_2 (0x9C + IPU_BASE) -#define PF_CONF (0xA0 + IPU_BASE) -#define IDMAC_CONF (0xA4 + IPU_BASE) -#define IDMAC_CHA_EN (0xA8 + IPU_BASE) -#define IDMAC_CHA_PRI (0xAC + IPU_BASE) -#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) - -/* Image Converter Register bits */ -#define IC_CONF_PRPENC_EN 0x00000001 -#define IC_CONF_PRPENC_CSC1 0x00000002 -#define IC_CONF_PRPENC_ROT_EN 0x00000004 -#define IC_CONF_PRPVF_EN 0x00000100 -#define IC_CONF_PRPVF_CSC1 0x00000200 -#define IC_CONF_PRPVF_CSC2 0x00000400 -#define IC_CONF_PRPVF_CMB 0x00000800 -#define IC_CONF_PRPVF_ROT_EN 0x00001000 -#define IC_CONF_PP_EN 0x00010000 -#define IC_CONF_PP_CSC1 0x00020000 -#define IC_CONF_PP_CSC2 0x00040000 -#define IC_CONF_PP_CMB 0x00080000 -#define IC_CONF_PP_ROT_EN 0x00100000 -#define IC_CONF_IC_GLB_LOC_A 0x10000000 -#define IC_CONF_KEY_COLOR_EN 0x20000000 -#define IC_CONF_RWS_EN 0x40000000 -#define IC_CONF_CSI_MEM_WR_EN 0x80000000 - -/* SDC Registers */ -#define SDC_COM_CONF (0xB4 + IPU_BASE) -#define SDC_GW_CTRL (0xB8 + IPU_BASE) -#define SDC_FG_POS (0xBC + IPU_BASE) -#define SDC_BG_POS (0xC0 + IPU_BASE) -#define SDC_CUR_POS (0xC4 + IPU_BASE) -#define SDC_PWM_CTRL (0xC8 + IPU_BASE) -#define SDC_CUR_MAP (0xCC + IPU_BASE) -#define SDC_HOR_CONF (0xD0 + IPU_BASE) -#define SDC_VER_CONF (0xD4 + IPU_BASE) -#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) -#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) - -/* Register bits */ -#define SDC_COM_TFT_COLOR 0x00000001UL -#define SDC_COM_FG_EN 0x00000010UL -#define SDC_COM_GWSEL 0x00000020UL -#define SDC_COM_GLB_A 0x00000040UL -#define SDC_COM_KEY_COLOR_G 0x00000080UL -#define SDC_COM_BG_EN 0x00000200UL -#define SDC_COM_SHARP 0x00001000UL - -#define SDC_V_SYNC_WIDTH_L 0x00000001UL - -/* Display Interface registers */ -#define DI_DISP_IF_CONF (0x0124 + IPU_BASE) -#define DI_DISP_SIG_POL (0x0128 + IPU_BASE) -#define DI_SER_DISP1_CONF (0x012C + IPU_BASE) -#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) -#define DI_HSP_CLK_PER (0x0134 + IPU_BASE) -#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) -#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) -#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) -#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) -#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) -#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) -#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) -#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) -#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) -#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) -#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) -#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) -#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) -#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) -#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) -#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) -#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) -#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) -#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) -#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) -#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) -#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) -#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) -#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) -#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) -#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) -#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) -#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) -#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) -#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) -#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) -#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) -#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) -#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) - -/* DI_DISP_SIG_POL bits */ -#define DI_D3_VSYNC_POL (1 << 28) -#define DI_D3_HSYNC_POL (1 << 27) -#define DI_D3_DRDY_SHARP_POL (1 << 26) -#define DI_D3_CLK_POL (1 << 25) -#define DI_D3_DATA_POL (1 << 24) - -/* DI_DISP_IF_CONF bits */ -#define DI_D3_CLK_IDLE (1 << 26) -#define DI_D3_CLK_SEL (1 << 25) -#define DI_D3_DATAMSK (1 << 24) - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_GPIONUM_SHIFT 9 -#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) - -#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) - -#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) - -struct chan_param_mem_planar { - /* Word 0 */ - u32 xv:10; - u32 yv:10; - u32 xb:12; - - u32 yb:12; - u32 res1:2; - u32 nsb:1; - u32 lnpb:6; - u32 ubo_l:11; - - u32 ubo_h:15; - u32 vbo_l:17; - - u32 vbo_h:9; - u32 res2:3; - u32 fw:12; - u32 fh_l:8; - - u32 fh_h:4; - u32 res3:28; - - /* Word 1 */ - u32 eba0; - - u32 eba1; - - u32 bpp:3; - u32 sl:14; - u32 pfs:3; - u32 bam:3; - u32 res4:2; - u32 npb:6; - u32 res5:1; - - u32 sat:2; - u32 res6:30; -} __attribute__ ((packed)); - -struct chan_param_mem_interleaved { - /* Word 0 */ - u32 xv:10; - u32 yv:10; - u32 xb:12; - - u32 yb:12; - u32 sce:1; - u32 res1:1; - u32 nsb:1; - u32 lnpb:6; - u32 sx:10; - u32 sy_l:1; - - u32 sy_h:9; - u32 ns:10; - u32 sm:10; - u32 sdx_l:3; - - u32 sdx_h:2; - u32 sdy:5; - u32 sdrx:1; - u32 sdry:1; - u32 sdr1:1; - u32 res2:2; - u32 fw:12; - u32 fh_l:8; - - u32 fh_h:4; - u32 res3:28; - - /* Word 1 */ - u32 eba0; - - u32 eba1; - - u32 bpp:3; - u32 sl:14; - u32 pfs:3; - u32 bam:3; - u32 res4:2; - u32 npb:6; - u32 res5:1; - - u32 sat:2; - u32 scc:1; - u32 ofs0:5; - u32 ofs1:5; - u32 ofs2:5; - u32 ofs3:5; - u32 wid0:3; - u32 wid1:3; - u32 wid2:3; - - u32 wid3:3; - u32 dec_sel:1; - u32 res6:28; -} __attribute__ ((packed)); - -union chan_param_mem { - struct chan_param_mem_planar pp; - struct chan_param_mem_interleaved ip; -}; - -/* graphics setup */ -static GraphicDevice panel; -static struct ctfb_res_modes *mode; -static struct ctfb_res_modes var_mode; - -/* - * sdc_init_panel() - initialize a synchronous LCD panel. - * @width: width of panel in pixels. - * @height: height of panel in pixels. - * @di_setup: pixel format of the frame buffer - * @di_panel: either SHARP or normal TFT - * @return: 0 on success or negative error code on failure. - */ -static int sdc_init_panel(u16 width, u16 height, - enum pixel_fmt di_setup, enum ipu_panel di_panel) -{ - u32 reg, div; - uint32_t old_conf; - int clock; - - debug("%s(width=%d, height=%d)\n", __func__, width, height); - - /* Init clocking, the IPU receives its clock from the hsp divder */ - clock = mxc_get_clock(MXC_IPU_CLK); - if (clock < 0) - return -EACCES; - - /* Init panel size and blanking periods */ - reg = width + mode->left_margin + mode->right_margin - 1; - if (reg > 1023) { - printf("mx3fb: Display width too large, coerced to 1023!"); - reg = 1023; - } - reg = ((mode->hsync_len - 1) << 26) | (reg << 16); - writel(reg, SDC_HOR_CONF); - - reg = height + mode->upper_margin + mode->lower_margin - 1; - if (reg > 1023) { - printf("mx3fb: Display height too large, coerced to 1023!"); - reg = 1023; - } - reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16); - writel(reg, SDC_VER_CONF); - - switch (di_panel) { - case IPU_PANEL_SHARP_TFT: - writel(0x00FD0102L, SDC_SHARP_CONF_1); - writel(0x00F500F4L, SDC_SHARP_CONF_2); - writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); - /* TODO: probably IF_CONF must be adapted (see below)! */ - break; - case IPU_PANEL_TFT: - writel(SDC_COM_TFT_COLOR, SDC_COM_CONF); - break; - default: - return -EINVAL; - } - - /* - * Calculate divider: The fractional part is 4 bits so simply - * multiple by 2^4 to get it. - * - * Opposed to the kernel driver mode->pixclock is the time of one - * pixel in pico seconds, so: - * pixel_clk = 1e12 / mode->pixclock - * div = ipu_clk * 16 / pixel_clk - * leads to: - * div = ipu_clk * 16 / (1e12 / mode->pixclock) - * or: - * div = ipu_clk * 16 * mode->pixclock / 1e12 - * - * To avoid integer overflows this is split into 2 shifts and - * one divide with sufficient accuracy: - * 16*1024*128*476837 = 0.9999996682e12 - */ - div = ((clock/1024) * (mode->pixclock/128)) / 476837; - debug("hsp_clk is %d, div=%d\n", clock, div); - /* coerce to not less than 4.0, not more than 255.9375 */ - if (div < 0x40) - div = 0x40; - else if (div > 0xFFF) - div = 0xFFF; - /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less - * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR - * based on timing debug DISP3_IF_CLK_UP_WR is 0 - */ - writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); - - /* DI settings for display 3: clock idle (bit 26) during vsync */ - old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF; - writel(old_conf | IF_CONF, DI_DISP_IF_CONF); - - /* only set display 3 polarity bits */ - old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF; - writel(old_conf | mode->sync, DI_DISP_SIG_POL); - - writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP); - writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP); - writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP); - writel(readl(DI_DISP_ACC_CC) | - ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC); - - debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF)); - debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL)); - debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF)); - debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF)); - debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF)); - - return 0; -} - -static void ipu_ch_param_set_size(union chan_param_mem *params, - uint pixelfmt, uint16_t width, - uint16_t height, uint16_t stride) -{ - debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n", - __func__, pixelfmt, width, height, stride); - - params->pp.fw = width - 1; - params->pp.fh_l = height - 1; - params->pp.fh_h = (height - 1) >> 8; - params->pp.sl = stride - 1; - - /* See above, for further formats see the Linux driver */ - switch (pixelfmt) { - case GDF_16BIT_565RGB: - params->ip.bpp = 2; - params->ip.pfs = 4; - params->ip.npb = 7; - params->ip.sat = 2; /* SAT = 32-bit access */ - params->ip.ofs0 = 0; /* Red bit offset */ - params->ip.ofs1 = 5; /* Green bit offset */ - params->ip.ofs2 = 11; /* Blue bit offset */ - params->ip.ofs3 = 16; /* Alpha bit offset */ - params->ip.wid0 = 4; /* Red bit width - 1 */ - params->ip.wid1 = 5; /* Green bit width - 1 */ - params->ip.wid2 = 4; /* Blue bit width - 1 */ - break; - case GDF_32BIT_X888RGB: - params->ip.bpp = 1; /* 24 BPP & RGB PFS */ - params->ip.pfs = 4; - params->ip.npb = 7; - params->ip.sat = 2; /* SAT = 32-bit access */ - params->ip.ofs0 = 16; /* Red bit offset */ - params->ip.ofs1 = 8; /* Green bit offset */ - params->ip.ofs2 = 0; /* Blue bit offset */ - params->ip.ofs3 = 24; /* Alpha bit offset */ - params->ip.wid0 = 7; /* Red bit width - 1 */ - params->ip.wid1 = 7; /* Green bit width - 1 */ - params->ip.wid2 = 7; /* Blue bit width - 1 */ - break; - default: - printf("mx3fb: Pixel format not supported!\n"); - break; - } - - params->pp.nsb = 1; -} - -static void ipu_ch_param_set_buffer(union chan_param_mem *params, - void *buf0, void *buf1) -{ - params->pp.eba0 = (u32)buf0; - params->pp.eba1 = (u32)buf1; -} - -static void ipu_write_param_mem(uint32_t addr, uint32_t *data, - uint32_t num_words) -{ - for (; num_words > 0; num_words--) { - writel(addr, IPU_IMA_ADDR); - writel(*data++, IPU_IMA_DATA); - addr++; - if ((addr & 0x7) == 5) { - addr &= ~0x7; /* set to word 0 */ - addr += 8; /* increment to next row */ - } - } -} - -static uint32_t dma_param_addr(enum ipu_channel channel) -{ - /* Channel Parameter Memory */ - return 0x10000 | (channel << 4); -} - -static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) -{ - union chan_param_mem params = {}; - uint32_t reg; - uint32_t stride_bytes; - - stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3; - - debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem); - - /* Build parameter memory data for DMA channel */ - ipu_ch_param_set_size(¶ms, panel.gdfIndex, - panel.plnSizeX, panel.plnSizeY, stride_bytes); - ipu_ch_param_set_buffer(¶ms, fbmem, NULL); - params.pp.bam = 0; - /* Some channels (rotation) have restriction on burst length */ - - switch (channel) { - case IDMAC_SDC_0: - /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ - params.pp.npb = 16 - 1; - break; - default: - break; - } - - ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); - - /* Disable double-buffering */ - reg = readl(IPU_CHA_DB_MODE_SEL); - reg &= ~(1UL << channel); - writel(reg, IPU_CHA_DB_MODE_SEL); -} - -static void ipu_channel_set_priority(enum ipu_channel channel, - int prio) -{ - u32 reg = readl(IDMAC_CHA_PRI); - - if (prio) - reg |= 1UL << channel; - else - reg &= ~(1UL << channel); - - writel(reg, IDMAC_CHA_PRI); -} - -/* - * ipu_enable_channel() - enable an IPU channel. - * @channel: channel ID. - * @return: 0 on success or negative error code on failure. - */ -static int ipu_enable_channel(enum ipu_channel channel) -{ - uint32_t reg; - - /* Reset to buffer 0 */ - writel(1UL << channel, IPU_CHA_CUR_BUF); - - switch (channel) { - case IDMAC_SDC_0: - ipu_channel_set_priority(channel, 1); - break; - default: - break; - } - - reg = readl(IDMAC_CHA_EN); - writel(reg | (1UL << channel), IDMAC_CHA_EN); - - return 0; -} - -static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) -{ - uint32_t reg; - - reg = readl(IPU_CHA_BUF0_RDY); - if (reg & (1UL << channel)) - return -EACCES; - - /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ - writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); - writel((u32)buf, IPU_IMA_DATA); - - return 0; -} - -static int idmac_tx_submit(enum ipu_channel channel, void *buf) -{ - int ret; - - ipu_init_channel_buffer(channel, buf); - - - /* ipu_idmac.c::ipu_submit_channel_buffers() */ - ret = ipu_update_channel_buffer(channel, buf); - if (ret < 0) - return ret; - - /* ipu_idmac.c::ipu_select_buffer() */ - /* Mark buffer 0 as ready. */ - writel(1UL << channel, IPU_CHA_BUF0_RDY); - - - ret = ipu_enable_channel(channel); - return ret; -} - -static void sdc_enable_channel(void *fbmem) -{ - int ret; - u32 reg; - - ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); - - /* mx3fb.c::sdc_fb_init() */ - if (ret >= 0) { - reg = readl(SDC_COM_CONF); - writel(reg | SDC_COM_BG_EN, SDC_COM_CONF); - } - - /* - * Attention! Without this msleep the channel keeps generating - * interrupts. Next sdc_set_brightness() is going to be called - * from mx3fb_blank(). - */ - udelay(2000); -} - -/* - * mx3fb_set_par() - set framebuffer parameters and change the operating mode. - * @return: 0 on success or negative error code on failure. - * TODO: currently only 666 and TFT as DI setup supported - */ -static int mx3fb_set_par(void) -{ - int ret; - - ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY, - IPU_PIX_FMT_RGB666, IPU_PANEL_TFT); - if (ret < 0) - return ret; - - writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS); - - return 0; -} - -static void ll_disp3_enable(void *base) -{ - u32 reg; - - debug("%s(base=0x%x)\n", __func__, (u32) base); - /* pcm037.c::mxc_board_init() */ - - /* Display Interface #3 */ - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); - - - /* ipu_idmac.c::ipu_probe() */ - - /* Start the clock */ - __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); - - - /* ipu_idmac.c::ipu_idmac_init() */ - - /* Service request counter to maximum - shouldn't be needed */ - writel(0x00000070, IDMAC_CONF); - - - /* ipu_idmac.c::ipu_init_channel() */ - - /* Enable IPU sub modules */ - reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; - writel(reg, IPU_CONF); - - - /* mx3fb.c::init_fb_chan() */ - - /* set Display Interface clock period */ - writel(0x00100010L, DI_HSP_CLK_PER); - /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ - - - /* mx3fb.c::sdc_set_brightness() */ - - /* This might be board-specific */ - writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL); - - - /* mx3fb.c::sdc_set_global_alpha() */ - - /* Use global - not per-pixel - Alpha-blending */ - reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; - writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); - - reg = readl(SDC_COM_CONF); - writel(reg | SDC_COM_GLB_A, SDC_COM_CONF); - - - /* mx3fb.c::sdc_set_color_key() */ - - /* Disable colour-keying for background */ - reg = readl(SDC_COM_CONF) & - ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); - writel(reg, SDC_COM_CONF); - - - mx3fb_set_par(); - - sdc_enable_channel(base); - - /* - * Linux driver calls sdc_set_brightness() here again, - * once is enough for us - */ - debug("%s() done\n", __func__); -} - -/* ------------------------ public part ------------------- */ -ulong calc_fbsize(void) -{ - return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP; -} - -/* - * The current implementation is only tested for GDF_16BIT_565RGB! - * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO, - * because the lcd code seemed loaded with color table stuff, that - * does not relate to most modern TFTs. cfb_console.c looks more - * straight forward. - * This is the environment setting for the original setup - * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17, - * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0" - * "videomode=unknown" - * - * Settings for VBEST VGG322403 display: - * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000, - * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0" - * - * Settings for COM57H5M10XRC display: - * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000, - * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0" - */ -void *video_hw_init(void) -{ - char *penv; - u32 memsize; - unsigned long t1, hsynch, vsynch; - int bits_per_pixel, i, tmp, videomode; - - tmp = 0; - - puts("Video: "); - - videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; - /* get video mode via environment */ - penv = env_get("videomode"); - if (penv) { - /* decide if it is a string */ - if (penv[0] <= '9') { - videomode = (int)hextoul(penv, NULL); - tmp = 1; - } - } else { - tmp = 1; - } - if (tmp) { - /* parameter are vesa modes */ - /* search params */ - for (i = 0; i < VESA_MODES_COUNT; i++) { - if (vesa_modes[i].vesanr == videomode) - break; - } - if (i == VESA_MODES_COUNT) { - printf("No VESA Mode found, switching to mode 0x%x ", - CONFIG_SYS_DEFAULT_VIDEO_MODE); - i = 0; - } - mode = (struct ctfb_res_modes *) - &res_mode_init[vesa_modes[i].resindex]; - bits_per_pixel = vesa_modes[i].bits_per_pixel; - } else { - mode = (struct ctfb_res_modes *) &var_mode; - bits_per_pixel = video_get_params(mode, penv); - } - - /* calculate hsynch and vsynch freq (info only) */ - t1 = (mode->left_margin + mode->xres + - mode->right_margin + mode->hsync_len) / 8; - t1 *= 8; - t1 *= mode->pixclock; - t1 /= 1000; - hsynch = 1000000000L / t1; - t1 *= (mode->upper_margin + mode->yres + - mode->lower_margin + mode->vsync_len); - t1 /= 1000; - vsynch = 1000000000L / t1; - - /* fill in Graphic device struct */ - sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz", - mode->xres, mode->yres, - bits_per_pixel, (hsynch / 1000), (vsynch / 1000)); - printf("%s\n", panel.modeIdent); - panel.winSizeX = mode->xres; - panel.winSizeY = mode->yres; - panel.plnSizeX = mode->xres; - panel.plnSizeY = mode->yres; - - switch (bits_per_pixel) { - case 24: - panel.gdfBytesPP = 4; - panel.gdfIndex = GDF_32BIT_X888RGB; - break; - case 16: - panel.gdfBytesPP = 2; - panel.gdfIndex = GDF_16BIT_565RGB; - break; - default: - panel.gdfBytesPP = 1; - panel.gdfIndex = GDF__8BIT_INDEX; - break; - } - - /* set up Hardware */ - memsize = calc_fbsize(); - - debug("%s() allocating %d bytes\n", __func__, memsize); - - /* fill in missing Graphic device struct */ - panel.frameAdrs = (u32) malloc(memsize); - if (panel.frameAdrs == 0) { - printf("%s() malloc(%d) failed\n", __func__, memsize); - return 0; - } - panel.memSize = memsize; - - ll_disp3_enable((void *) panel.frameAdrs); - memset((void *) panel.frameAdrs, 0, memsize); - - debug("%s() done, framebuffer at 0x%x, size=%d cleared\n", - __func__, panel.frameAdrs, memsize); - - return (void *) &panel; -} From 79c05335a9c101f0b54f2f378d0b08c9b765e1a3 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 4 Oct 2021 17:33:12 +0200 Subject: [PATCH 123/228] video: move MXS to Kconfig Move CONFIG_VIDEO_MXS from board headers to Kconfig and drop it from obsolete cfb_console driver. Signed-off-by: Anatolij Gustschin Reviewed-by: Fabio Estevam --- configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx7_defconfig | 1 + configs/imxrt1050-evk_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/opos6uldev_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + drivers/video/Kconfig | 6 ++++++ drivers/video/cfb_console.c | 4 ---- include/configs/colibri-imx6ull.h | 3 +-- include/configs/colibri_imx7.h | 3 +-- include/configs/imxrt1050-evk.h | 1 - include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx6sxsabresd.h | 3 +-- include/configs/mx6ul_14x14_evk.h | 1 - include/configs/mx7dsabresd.h | 3 +-- include/configs/mxs.h | 5 ----- include/configs/opos6uldev.h | 1 - include/configs/pico-imx6ul.h | 3 +-- include/configs/pico-imx7d.h | 1 - 23 files changed, 22 insertions(+), 25 deletions(-) diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 0af56f438a..0c0f1435ab 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -95,6 +95,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 88d6994153..671390453a 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -91,6 +91,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 94363cf6ea..ace8941693 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -72,6 +72,7 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index c9760df4b5..ee80006635 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -93,6 +93,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index a373e20299..7abe5be359 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -83,6 +83,7 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 32adb5d818..bd78f25295 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -103,6 +103,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index d7c3821a0c..e55c0b71cf 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -78,5 +78,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index df81717a32..cb057b66f2 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -81,6 +81,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 7d535625bf..e840bf04f3 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -85,6 +85,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y +CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index b1f8a9c1e6..9f789a6a58 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -648,6 +648,12 @@ source "drivers/video/bridge/Kconfig" source "drivers/video/imx/Kconfig" +config VIDEO_MXS + bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs" + depends on DM_VIDEO + help + Enable framebuffer driver for i.MX28/i.MX6UL/i.MX7 processors + config VIDEO_NX bool "Enable video support on Nexell SoC" depends on ARCH_S5P6818 || ARCH_S5P4418 diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 7aa6f17d61..7df7d57e6e 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -78,10 +78,6 @@ #include #include -#if defined(CONFIG_VIDEO_MXS) -#define VIDEO_FB_16BPP_WORD_SWAP -#endif - /* * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc. */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index a2f2de7ea1..741c3fedec 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -134,8 +134,7 @@ /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 -#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) -#define CONFIG_VIDEO_MXS +#if defined(CONFIG_DM_VIDEO) #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 07c26e3d0b..344b266db9 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -200,8 +200,7 @@ #define CONFIG_USBD_HS -#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) -#define CONFIG_VIDEO_MXS +#if defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #endif diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 1b6754299e..99d25c1e6e 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -22,7 +22,6 @@ DMAMEM_SZ_ALL) #ifdef CONFIG_DM_VIDEO -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 1f40d98be0..bccba5cbb1 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -26,7 +26,7 @@ #endif /* Framebuffer support */ -#ifdef CONFIG_VIDEO +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 10292c86fa..fe4ea8997d 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -40,7 +40,7 @@ #endif /* Framebuffer support */ -#ifdef CONFIG_VIDEO +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1237ddef8e..df2bd97438 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -161,8 +161,7 @@ #endif #ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index ff2ad094a7..9ddb47910f 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -167,7 +167,6 @@ #ifndef CONFIG_SPL_BUILD #if defined(CONFIG_DM_VIDEO) -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 397af53bec..92ce741768 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -126,8 +126,7 @@ #define CONFIG_USBD_HS -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #endif diff --git a/include/configs/mxs.h b/include/configs/mxs.h index b5c525dc78..45d1766482 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -105,11 +105,6 @@ #endif #endif -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS -#endif - /* NAND */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index f9db8efd2f..d9311a4935 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -43,7 +43,6 @@ #ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VIDEO_MXS #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR #endif #endif diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 7e36ceed3f..6fed7522bd 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -135,8 +135,7 @@ */ #define CONFIG_BOARD_SIZE_LIMIT 715776 -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 36c57923de..c0464278b9 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -126,7 +126,6 @@ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #ifdef CONFIG_DM_VIDEO -#define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #endif From 5427da02bebb3a375f11a5623dea07993ea0d555 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Mon, 6 Sep 2021 23:06:13 +0200 Subject: [PATCH 124/228] configs: add PineTab defconfig The PineTab device-tree is already in u-boot, this commit adds the corresponding defconfig, based on pinephone_defconfig. Signed-off-by: Arnaud Ferraris Signed-off-by: Andre Przywara --- board/sunxi/MAINTAINERS | 5 +++++ configs/pinetab_defconfig | 10 ++++++++++ 2 files changed, 15 insertions(+) create mode 100644 configs/pinetab_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 4fc26077b2..2543c94de7 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -471,6 +471,11 @@ M: Samuel Holland S: Maintained F: configs/pinephone_defconfig +PINETAB BOARD +M: Arnaud Ferraris +S: Maintained +F: configs/pinetab_defconfig + R16 EVB PARROT BOARD M: Quentin Schulz S: Maintained diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig new file mode 100644 index 0000000000..0cc24146b3 --- /dev/null +++ b/configs/pinetab_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab" +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set From 21d314a6612564ee202d8a8189ed37d5c6abf0dd Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 11:48:43 -0500 Subject: [PATCH 125/228] clk: sunxi: Move header out of arch directory The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland Reviewed-by: Bin Meng Signed-off-by: Andre Przywara --- drivers/clk/sunxi/clk_a10.c | 2 +- drivers/clk/sunxi/clk_a10s.c | 2 +- drivers/clk/sunxi/clk_a23.c | 2 +- drivers/clk/sunxi/clk_a31.c | 2 +- drivers/clk/sunxi/clk_a64.c | 2 +- drivers/clk/sunxi/clk_a80.c | 2 +- drivers/clk/sunxi/clk_a83t.c | 2 +- drivers/clk/sunxi/clk_h3.c | 2 +- drivers/clk/sunxi/clk_h6.c | 2 +- drivers/clk/sunxi/clk_h616.c | 2 +- drivers/clk/sunxi/clk_r40.c | 2 +- drivers/clk/sunxi/clk_sunxi.c | 2 +- drivers/clk/sunxi/clk_v3s.c | 2 +- drivers/reset/reset-sunxi.c | 2 +- .../include/asm/arch-sunxi/ccu.h => include/clk/sunxi.h | 8 +++----- 15 files changed, 17 insertions(+), 19 deletions(-) rename arch/arm/include/asm/arch-sunxi/ccu.h => include/clk/sunxi.h (94%) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 1b5de86e20..1342a6cda6 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 184f61ab23..d30846a9b3 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 5750514a74..52de1cb8d4 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 9226112f4a..28ff82108e 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 0553ffa439..a46cb27bd1 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 68973d528e..bda7835c04 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 880c7d7599..5c3cc5bbf7 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f81633b92d..3adc6a9837 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index df93d96b3b..86496ed1bb 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index 553d7c6e55..c39ba06fb8 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index ee1e86d22e..a261296805 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 41934cd826..9673b58a49 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 29622199fd..34ccda7e72 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index 264337ed80..8b95938dfe 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -11,11 +11,11 @@ #include #include #include +#include #include #include #include #include -#include struct sunxi_reset_priv { void *base; diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/include/clk/sunxi.h similarity index 94% rename from arch/arm/include/asm/arch-sunxi/ccu.h rename to include/clk/sunxi.h index cac5c5faf0..d4ad5fd0ba 100644 --- a/arch/arm/include/asm/arch-sunxi/ccu.h +++ b/include/clk/sunxi.h @@ -4,12 +4,10 @@ * Author: Jagan Teki */ -#ifndef _ASM_ARCH_CCU_H -#define _ASM_ARCH_CCU_H +#ifndef _CLK_SUNXI_H +#define _CLK_SUNXI_H -#ifndef __ASSEMBLY__ #include -#endif /** * enum ccu_flags - ccu clock/reset flags @@ -97,4 +95,4 @@ extern struct clk_ops sunxi_clk_ops; */ int sunxi_reset_bind(struct udevice *dev, ulong count); -#endif /* _ASM_ARCH_CCU_H */ +#endif /* _CLK_SUNXI_H */ From dda9fa734f813c0d0c29aa03bfe200950b40cfea Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 10:28:35 -0500 Subject: [PATCH 126/228] sunxi: Simplify MMC pinmux selection Only one board, Yones Toptech BD1078, actually uses a non-default MMC pinmux. All other uses of these symbols select the default value or an invalid value. To simplify things, remove support for the unused pinmux options, and convert the remaining option to a Boolean. This allows the pinmux to be chosen by the preprocessor, instead of having the code parse a string at runtime (for a build-time option!). Not only does this reduce code size, but it also allows this Kconfig option to be used in a table-driven DM pinctrl driver. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 4 - arch/arm/mach-sunxi/Kconfig | 21 +---- board/sunxi/board.c | 101 +++++++------------------ configs/A20-Olimex-SOM-EVB_defconfig | 1 - configs/Sinlinx_SinA31s_defconfig | 1 - configs/Yones_Toptech_BD1078_defconfig | 2 +- configs/parrot_r16_defconfig | 1 - 7 files changed, 34 insertions(+), 97 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 2969a530ae..43b1b97391 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -148,8 +148,6 @@ enum sunxi_gpio_number { #define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 -#define SUN6I_GPA_SDC2 5 -#define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2 #define SUN4I_GPB_PWM 2 @@ -173,12 +171,10 @@ enum sunxi_gpio_number { #define SUN6I_GPC_SDC3 4 #define SUN50I_GPC_SPI0 4 -#define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3 #define SUNXI_GPD_PWM 2 -#define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 #define SUN50I_GPE_TWI2 3 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1d4a4fdd0c..7308f977a5 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -677,24 +677,11 @@ config MMC3_CD_PIN ---help--- See MMC0_CD_PIN help text. -config MMC1_PINS - string "Pins for mmc1" - default "" +config MMC1_PINS_PH + bool "Pins for mmc1 are on Port H" + depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 ---help--- - Set the pins used for mmc1, when applicable. This takes a string in the - format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. - -config MMC2_PINS - string "Pins for mmc2" - default "" - ---help--- - See MMC1_PINS help text. - -config MMC3_PINS - string "Pins for mmc3" - default "" - ---help--- - See MMC1_PINS help text. + Select this option for boards where mmc1 uses the Port H pinmux. config MMC_SUNXI_SLOT_EXTRA int "mmc extra slot number" diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 2b7d655678..418dc0ce75 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -413,7 +413,6 @@ void board_nand_init(void) static void mmc_pinmux_setup(int sdc) { unsigned int pin; - __maybe_unused int pins; switch (sdc) { case 0: @@ -426,11 +425,9 @@ static void mmc_pinmux_setup(int sdc) break; case 1: - pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); - #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ defined(CONFIG_MACH_SUN8I_R40) - if (pins == SUNXI_GPIO_H) { + if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) { /* SDC1: PH22-PH-27 */ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); @@ -460,27 +457,16 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_drv(pin, 2); } #elif defined(CONFIG_MACH_SUN8I) - if (pins == SUNXI_GPIO_D) { - /* SDC1: PD2-PD7 */ - for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } else { - /* SDC1: PG0-PG5 */ - for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } + /* SDC1: PG0-PG5 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); } #endif break; case 2: - pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); - #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) /* SDC2: PC6-PC11 */ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { @@ -489,41 +475,23 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_drv(pin, 2); } #elif defined(CONFIG_MACH_SUN5I) - if (pins == SUNXI_GPIO_E) { - /* SDC2: PE4-PE9 */ - for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } else { - /* SDC2: PC6-PC15 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } + /* SDC2: PC6-PC15 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); } #elif defined(CONFIG_MACH_SUN6I) - if (pins == SUNXI_GPIO_A) { - /* SDC2: PA9-PA14 */ - for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } else { - /* SDC2: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); #elif defined(CONFIG_MACH_SUN8I_R40) /* SDC2: PC6-PC15, PC24 */ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { @@ -579,8 +547,6 @@ static void mmc_pinmux_setup(int sdc) break; case 3: - pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); - #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ defined(CONFIG_MACH_SUN8I_R40) /* SDC3: PI4-PI9 */ @@ -590,25 +556,16 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_drv(pin, 2); } #elif defined(CONFIG_MACH_SUN6I) - if (pins == SUNXI_GPIO_A) { - /* SDC3: PA9-PA14 */ - for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - } else { - /* SDC3: PC6-PC15, PC24 */ - for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { - sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); - sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(pin, 2); - } - - sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); - sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); - sunxi_gpio_set_drv(SUNXI_GPC(24), 2); + /* SDC3: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); #endif break; diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index ececdaca15..075d999e1c 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC3_CD_PIN="PH0" -CONFIG_MMC3_PINS="PH" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 8fa8246344..238b0073e7 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=251 CONFIG_MMC0_CD_PIN="PA4" -CONFIG_MMC3_PINS="PC" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 1b88cfabf0..f1ceb8b552 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -6,7 +6,7 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC1_CD_PIN="PH2" -CONFIG_MMC1_PINS="PH" +CONFIG_MMC1_PINS_PH=y CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index de340e230f..d56c4504b6 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=600 CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PD14" -CONFIG_MMC2_PINS="PC" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" From 14c8c631e986d350ce468ae5d627f547e5a4e1aa Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 10:28:36 -0500 Subject: [PATCH 127/228] gpio: sunxi: Remove the sunxi_name_to_gpio_bank function The only caller of this function was the MMC pinmux code, which used it to parse a string given from a Kconfig symbol. As the Kconfig symbol has been converted to a Boolean, this function is no longer needed. Signed-off-by: Samuel Holland Reviewed-by: Simon Glass Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 - drivers/gpio/sunxi_gpio.c | 14 -------------- 2 files changed, 15 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 43b1b97391..c595dcc635 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -238,7 +238,6 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); -int sunxi_name_to_gpio_bank(const char *name); int sunxi_name_to_gpio(const char *name); #define name_to_gpio(name) sunxi_name_to_gpio(name) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 24cb604e3e..c5d73d0a04 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -118,20 +118,6 @@ int sunxi_name_to_gpio(const char *name) } #endif /* DM_GPIO */ -int sunxi_name_to_gpio_bank(const char *name) -{ - int group = 0; - - if (*name == 'P' || *name == 'p') - name++; - if (*name >= 'A') { - group = *name - (*name > 'a' ? 'a' : 'A'); - return group; - } - - return -1; -} - #if CONFIG_IS_ENABLED(DM_GPIO) /* TODO(sjg@chromium.org): Remove this function and use device tree */ int sunxi_name_to_gpio(const char *name) From 8f872bb37dc216785822b77d4421dc7f782e236c Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Wed, 8 Sep 2021 21:14:19 +0200 Subject: [PATCH 128/228] board: sunxi: enable status LED early For some systems, such as the PinePhone, there is no way for the end user to make sure the system is indeed booting before the boot script is executed, which takes several seconds. Therefore, it can be useful to provide early visual feedback as soon as possible. In order achieve this goal, this patch initializes the status LED (if configured) in the SPL. Signed-off-by: Arnaud Ferraris Reviewed-by: Samuel Holland Signed-off-by: Andre Przywara --- board/sunxi/board.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 418dc0ce75..6ba7bf523a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -46,6 +46,7 @@ #include #include #include +#include #if defined(CONFIG_VIDEO_LCD_PANEL_I2C) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ @@ -629,6 +630,11 @@ void sunxi_board_init(void) { int power_failed = 0; +#ifdef CONFIG_LED_STATUS + if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC)) + status_led_init(); +#endif + #ifdef CONFIG_SY8106A_POWER power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); #endif From 0534153fd14115cf66d33c2b841c1ac6048aed60 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Wed, 8 Sep 2021 21:14:20 +0200 Subject: [PATCH 129/228] pinephone_defconfig: add support for early-boot status LED This commit enables the green status LED (PD18/GPIO 114) on boot in the SPL, in order to provide visual feedback that the PinePhone is booting. Signed-off-by: Arnaud Ferraris Reviewed-by: Andre Przywara Reviewed-by: Samuel Holland Tested-by: Samuel Holland Signed-off-by: Andre Przywara --- configs/pinephone_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 64e13d3132..9d39204a43 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2" +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y @@ -10,3 +11,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" +CONFIG_LED_STATUS=y +CONFIG_LED_STATUS_GPIO=y +CONFIG_LED_STATUS0=y +CONFIG_LED_STATUS_BIT=114 +CONFIG_LED_STATUS_STATE=2 From 425084610e08e344d43e0d142e72e65c9602379f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 11 Sep 2021 16:50:47 -0500 Subject: [PATCH 130/228] sunxi: Clean up inclusions of asm/arch/gpio.h As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/board.c | 1 - arch/arm/mach-sunxi/clock.c | 1 - arch/arm/mach-sunxi/clock_sun4i.c | 1 - board/sunxi/board.c | 1 - board/sunxi/gmac.c | 1 - drivers/gpio/axp_gpio.c | 1 - drivers/gpio/sunxi_gpio.c | 1 - drivers/mmc/sunxi_mmc.c | 3 +-- drivers/net/sun8i_emac.c | 5 +---- drivers/power/axp809.c | 1 - drivers/power/axp818.c | 1 - drivers/usb/musb-new/sunxi.c | 2 -- drivers/video/sunxi/sunxi_display.c | 1 - drivers/video/sunxi/sunxi_lcd.c | 1 - 14 files changed, 2 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index d9b04f75fc..373cb56db4 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock.c b/arch/arm/mach-sunxi/clock.c index f591affebf..de7e875298 100644 --- a/arch/arm/mach-sunxi/clock.c +++ b/arch/arm/mach-sunxi/clock.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 57ee018eaa..471609764d 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #ifdef CONFIG_SPL_BUILD diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 6ba7bf523a..65cb3a6fe3 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index d8fdf7728e..1fa54ed72d 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -4,7 +4,6 @@ #include #include #include -#include void eth_init_board(void) { diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index 73058cf40b..35585dc8ac 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index c5d73d0a04..bf7d82fbf5 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index aaab0cf866..c170c16d5a 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -15,12 +15,11 @@ #include #include #include +#include #include #include #include -#include #include -#include #include #ifndef CCM_MMC_CTRL_MODE_SEL_NEW diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a6eb82bd16..2e24d12214 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -14,9 +14,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -31,9 +31,6 @@ #include #include #include -#if CONFIG_IS_ENABLED(DM_GPIO) -#include -#endif #define MDIO_CMD_MII_BUSY BIT(0) #define MDIO_CMD_MII_WRITE BIT(1) diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c index 6323492b66..0396502cdb 100644 --- a/drivers/power/axp809.c +++ b/drivers/power/axp809.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c index 0531707c8a..2dc736467b 100644 --- a/drivers/power/axp818.c +++ b/drivers/power/axp818.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index fea4105f3d..7e62e3fe6e 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -25,8 +25,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4361a58cd7..128888f7af 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 7a9eba1ed4..8b9c3b2bfa 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include From 4d9958b6424b370555fa9fda7a0dd97b353b9797 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 11 Sep 2021 16:50:48 -0500 Subject: [PATCH 131/228] sunxi: gpio: Remove name_to_gpio macro This clarifies which callers must be updated to complete the DM_GPIO conversion. The only remaining caller of name_to_gpio in generic code is inside the !DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so that code cannot be reached. And after this commit, there are only two remaining implementations of name_to_gpio. Signed-off-by: Samuel Holland Acked-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 - drivers/spi/spi-sunxi.c | 2 +- drivers/video/Kconfig | 10 +++++----- drivers/video/hitachi_tx18d42vm_lcd.c | 6 +++--- drivers/video/sunxi/sunxi_display.c | 10 +++++----- 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index c595dcc635..59e3915c37 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -239,7 +239,6 @@ int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); int sunxi_name_to_gpio(const char *name); -#define name_to_gpio(name) sunxi_name_to_gpio(name) #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO int axp_gpio_init(void); diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 4ca5d3a93a..bc2f544e86 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -245,7 +245,7 @@ static int sun4i_spi_parse_pins(struct udevice *dev) break; } - pin = name_to_gpio(pin_name); + pin = sunxi_name_to_gpio(pin_name); if (pin < 0) break; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 9f789a6a58..2f4650f830 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -452,7 +452,7 @@ config VIDEO_LCD_SSD2828_RESET default "" ---help--- The reset pin of SSD2828 chip. This takes a string in the format - understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" @@ -477,7 +477,7 @@ config VIDEO_LCD_SPI_CS This is one of the SPI communication pins, involved in setting up a working LCD configuration. The exact role of SPI may differ for different hardware setups. The option takes a string in the format - understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_SCLK string "SPI SCLK pin for LCD related config job" @@ -487,7 +487,7 @@ config VIDEO_LCD_SPI_SCLK This is one of the SPI communication pins, involved in setting up a working LCD configuration. The exact role of SPI may differ for different hardware setups. The option takes a string in the format - understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MOSI string "SPI MOSI pin for LCD related config job" @@ -497,7 +497,7 @@ config VIDEO_LCD_SPI_MOSI This is one of the SPI communication pins, involved in setting up a working LCD configuration. The exact role of SPI may differ for different hardware setups. The option takes a string in the format - understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MISO string "SPI MISO pin for LCD related config job (optional)" @@ -509,7 +509,7 @@ config VIDEO_LCD_SPI_MISO different hardware setups. If wired up, this pin may provide additional useful functionality. Such as bi-directional communication with the hardware and LCD panel id retrieval (if the panel can report it). The - option takes a string in the format understood by 'name_to_gpio' + option takes a string in the format understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. source "drivers/video/meson/Kconfig" diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c index c6c8df6a96..87c4d27438 100644 --- a/drivers/video/hitachi_tx18d42vm_lcd.c +++ b/drivers/video/hitachi_tx18d42vm_lcd.c @@ -49,9 +49,9 @@ int hitachi_tx18d42vm_init(void) }; int i, cs, clk, mosi, ret = 0; - cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); - clk = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK); - mosi = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI); + cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); + clk = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK); + mosi = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI); if (cs == -1 || clk == -1 || mosi == 1) { printf("Error tx18d42vm spi gpio config is invalid\n"); diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 128888f7af..da3e898829 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -871,11 +871,11 @@ static void sunxi_vga_external_dac_enable(void) static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode) { struct ssd2828_config cfg = { - .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS), - .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK), - .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), - .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), - .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), + .csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS), + .sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK), + .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), + .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), + .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000, .ssd2828_color_depth = 24, #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 From 8fe8ff34110792f8a4ed4ab7a4f4e14c82feb452 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 11 Sep 2021 16:50:49 -0500 Subject: [PATCH 132/228] sunxi: gpio: Remove bank-specific size macros Since the beginning, all banks have had space for 32 pins, even when not all pins were implemented. Let's use a single constant for the GPIO bank size here, like the GPIO driver is already doing. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 14 ++------------ drivers/gpio/sunxi_gpio.c | 2 -- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 59e3915c37..f3ab1aea0e 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -93,20 +93,10 @@ struct sunxi_gpio_reg { #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) /* GPIO bank sizes */ -#define SUNXI_GPIO_A_NR 32 -#define SUNXI_GPIO_B_NR 32 -#define SUNXI_GPIO_C_NR 32 -#define SUNXI_GPIO_D_NR 32 -#define SUNXI_GPIO_E_NR 32 -#define SUNXI_GPIO_F_NR 32 -#define SUNXI_GPIO_G_NR 32 -#define SUNXI_GPIO_H_NR 32 -#define SUNXI_GPIO_I_NR 32 -#define SUNXI_GPIO_L_NR 32 -#define SUNXI_GPIO_M_NR 32 +#define SUNXI_GPIOS_PER_BANK 32 #define SUNXI_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + 0) + ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) enum sunxi_gpio_number { SUNXI_GPIO_A_START = 0, diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index bf7d82fbf5..cdbc40d48f 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -19,8 +19,6 @@ #include #include -#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR - struct sunxi_gpio_plat { struct sunxi_gpio *regs; const char *bank_name; /* Name of bank, e.g. "B" */ From c61897bf029e86a46cdba53ced48889eae1cd468 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 09:47:24 -0500 Subject: [PATCH 133/228] clk: sunxi: Add support for I2C gates/resets Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/clk/sunxi/clk_a10.c | 5 +++++ drivers/clk/sunxi/clk_a10s.c | 3 +++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 8 ++++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a80.c | 10 ++++++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ drivers/clk/sunxi/clk_h6.c | 10 ++++++++++ drivers/clk/sunxi/clk_h616.c | 12 ++++++++++++ drivers/clk/sunxi/clk_r40.c | 10 ++++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 12 files changed, 86 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 1342a6cda6..90b929d3d3 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_GMAC] = GATE(0x064, BIT(17)), + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), + [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)), + [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index d30846a9b3..addf4f4d5c 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 52de1cb8d4..c45d2c3529 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = { [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = { [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 28ff82108e..251fc3b705 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), + [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), + [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), + [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), + [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)), [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), @@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = { [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)), [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)), + [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)), + [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)), + [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)), + [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)), [RST_APB2_UART0] = RESET(0x2d8, BIT(16)), [RST_APB2_UART1] = RESET(0x2d8, BIT(17)), [RST_APB2_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index a46cb27bd1..1004a79503 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index bda7835c04..8a0834d83a 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = { [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), [CLK_BUS_SPI3] = GATE(0x580, BIT(23)), + [CLK_BUS_I2C0] = GATE(0x594, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x594, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x594, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x594, BIT(3)), + [CLK_BUS_I2C4] = GATE(0x594, BIT(4)), [CLK_BUS_UART0] = GATE(0x594, BIT(16)), [CLK_BUS_UART1] = GATE(0x594, BIT(17)), [CLK_BUS_UART2] = GATE(0x594, BIT(18)), @@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = { [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)), [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)), + [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)), + [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)), + [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)), + [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)), + [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)), [RST_BUS_UART0] = RESET(0x5b4, BIT(16)), [RST_BUS_UART1] = RESET(0x5b4, BIT(17)), [RST_BUS_UART2] = RESET(0x5b4, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 5c3cc5bbf7..8c6043f51e 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = { [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = { [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 3adc6a9837..59afba53ee 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 86496ed1bb..4a53788352 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), + [CLK_SPI0] = GATE(0x940, BIT(31)), [CLK_SPI1] = GATE(0x944, BIT(31)), @@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = { [RST_BUS_UART2] = RESET(0x90c, BIT(18)), [RST_BUS_UART3] = RESET(0x90c, BIT(19)), + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index c39ba06fb8..af97d3bb9f 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = { [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), + [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)), + [CLK_SPI0] = GATE(0x940, BIT(31)), [CLK_SPI1] = GATE(0x944, BIT(31)), @@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = { [RST_BUS_UART4] = RESET(0x90c, BIT(20)), [RST_BUS_UART5] = RESET(0x90c, BIT(21)), + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), + [RST_BUS_I2C4] = RESET(0x91c, BIT(20)), + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index a261296805..4d5b69a976 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)), + [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)), + [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 34ccda7e72..cce5c658ca 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = { [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), From 23c83366f326fb88dd4ec40315ebae14df55ebc0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 12 Sep 2021 09:47:25 -0500 Subject: [PATCH 134/228] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/clk/sunxi/Kconfig | 14 ++++++++ drivers/clk/sunxi/Makefile | 2 ++ drivers/clk/sunxi/clk_a31_r.c | 59 +++++++++++++++++++++++++++++++++ drivers/clk/sunxi/clk_h6_r.c | 61 +++++++++++++++++++++++++++++++++++ 4 files changed, 136 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a31_r.c create mode 100644 drivers/clk/sunxi/clk_h6_r.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index bf084fa7a8..f89c7ffd42 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -30,6 +30,13 @@ config CLK_SUN6I_A31 This enables common clock driver support for platforms based on Allwinner A31/A31s SoC. +config CLK_SUN6I_A31_R + bool "Clock driver for Allwinner A31 generation PRCM" + default SUNXI_GEN_SUN6I + help + This enables common clock driver support for the PRCM + in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs. + config CLK_SUN8I_A23 bool "Clock driver for Allwinner A23/A33" default MACH_SUN8I_A23 || MACH_SUN8I_A33 @@ -79,6 +86,13 @@ config CLK_SUN50I_H6 This enables common clock driver support for platforms based on Allwinner H6 SoC. +config CLK_SUN50I_H6_R + bool "Clock driver for Allwinner H6 generation PRCM" + default SUN50I_GEN_H6 + help + This enables common clock driver support for the PRCM + in Allwinner H6/H616 SoCs. + config CLK_SUN50I_H616 bool "Clock driver for Allwinner H616" default MACH_SUN50I_H616 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 4f9282a8b9..48a48a2f00 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o +obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o @@ -18,5 +19,6 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o +obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c new file mode 100644 index 0000000000..1f08ea956f --- /dev/null +++ b/drivers/clk/sunxi/clk_a31_r.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Samuel Holland + */ + +#include +#include +#include +#include +#include +#include + +static struct ccu_clk_gate a31_r_gates[] = { + [CLK_APB0_PIO] = GATE(0x028, BIT(0)), + [CLK_APB0_IR] = GATE(0x028, BIT(1)), + [CLK_APB0_TIMER] = GATE(0x028, BIT(2)), + [CLK_APB0_RSB] = GATE(0x028, BIT(3)), + [CLK_APB0_UART] = GATE(0x028, BIT(4)), + [CLK_APB0_I2C] = GATE(0x028, BIT(6)), + [CLK_APB0_TWD] = GATE(0x028, BIT(7)), +}; + +static struct ccu_reset a31_r_resets[] = { + [RST_APB0_IR] = RESET(0x0b0, BIT(1)), + [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)), + [RST_APB0_RSB] = RESET(0x0b0, BIT(3)), + [RST_APB0_UART] = RESET(0x0b0, BIT(4)), + [RST_APB0_I2C] = RESET(0x0b0, BIT(6)), +}; + +static const struct ccu_desc a31_r_ccu_desc = { + .gates = a31_r_gates, + .resets = a31_r_resets, +}; + +static int a31_r_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets)); +} + +static const struct udevice_id a31_r_clk_ids[] = { + { .compatible = "allwinner,sun8i-a83t-r-ccu", + .data = (ulong)&a31_r_ccu_desc }, + { .compatible = "allwinner,sun8i-h3-r-ccu", + .data = (ulong)&a31_r_ccu_desc }, + { .compatible = "allwinner,sun50i-a64-r-ccu", + .data = (ulong)&a31_r_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun6i_a31_r) = { + .name = "sun6i_a31_r_ccu", + .id = UCLASS_CLK, + .of_match = a31_r_clk_ids, + .priv_auto = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = a31_r_clk_bind, +}; diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c new file mode 100644 index 0000000000..b9e527e16a --- /dev/null +++ b/drivers/clk/sunxi/clk_h6_r.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) Samuel Holland + */ + +#include +#include +#include +#include +#include +#include + +static struct ccu_clk_gate h6_r_gates[] = { + [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)), + [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)), + [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)), + [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)), + [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)), + [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)), + [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)), + [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)), +}; + +static struct ccu_reset h6_r_resets[] = { + [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)), + [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)), + [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)), + [RST_R_APB2_UART] = RESET(0x18c, BIT(16)), + [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)), + [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)), + [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)), + [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)), +}; + +static const struct ccu_desc h6_r_ccu_desc = { + .gates = h6_r_gates, + .resets = h6_r_resets, +}; + +static int h6_r_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets)); +} + +static const struct udevice_id h6_r_clk_ids[] = { + { .compatible = "allwinner,sun50i-h6-r-ccu", + .data = (ulong)&h6_r_ccu_desc }, + { .compatible = "allwinner,sun50i-h616-r-ccu", + .data = (ulong)&h6_r_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun6i_h6_r) = { + .name = "sun6i_h6_r_ccu", + .id = UCLASS_CLK, + .of_match = h6_r_clk_ids, + .priv_auto = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = h6_r_clk_bind, +}; From e7510d24cab4741f72489b9d67c2d42b18fe5374 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 10 Oct 2021 21:36:57 +0800 Subject: [PATCH 135/228] sunxi: Add support for FriendlyARM NanoPi R1S H5 This adds support for the NanoPi R1S H5 board. Allwinner H5 SoC 512MB DDR3 RAM 10/100/1000M Ethernet x 2 RTL8189ETV WiFi 802.11b/g/n USB 2.0 host port (A) MicroSD Slot Reset button Serial Debug Port WAN - LAN - SYS LED The dts file is taken from Linux 5.14 tag. Signed-off-by: Chukun Pan Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/nanopi_r1s_h5_defconfig | 14 ++ 4 files changed, 215 insertions(+) create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts create mode 100644 configs/nanopi_r1s_h5_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8a382d153..ed3d360bb1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -638,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-libretech-all-h5-cc.dtb \ sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-nanopi-r1s-h5.dtb \ sun50i-h5-orangepi-zero-plus.dtb \ sun50i-h5-orangepi-pc2.dtb \ sun50i-h5-orangepi-prime.dtb \ diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts new file mode 100644 index 0000000000..55bcdf8d1a --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Chukun Pan + * + * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: + * Copyright (C) 2017 Antony Antony + * Copyright (C) 2016 ARM Ltd. + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" + +#include +#include +#include + +/ { + model = "FriendlyARM NanoPi R1S H5"; + compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; + + aliases { + ethernet0 = &emac; + ethernet1 = &rtl8189etv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + r-gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "microchip,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 2543c94de7..56a0ee3689 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -358,6 +358,11 @@ M: Jelle van der Waa S: Maintained F: configs/nanopi_neo_air_defconfig +NANOPI-R1S-H5 BOARD +M: Chukun Pan +S: Maintained +F: configs/nanopi_r1s_h5_defconfig + NANOPI-A64 BOARD M: Jagan Teki S: Maintained diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig new file mode 100644 index 0000000000..27cf172d72 --- /dev/null +++ b/configs/nanopi_r1s_h5_defconfig @@ -0,0 +1,14 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5" +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881977 +# CONFIG_DRAM_ODT_EN is not set +CONFIG_MACPWR="PD6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y From 56c7f882ee33e9a19dee0a771c9bf04b78f46dc2 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 25 Sep 2021 09:58:25 -0500 Subject: [PATCH 136/228] configs: omap3x_logic: Enable LTO on more LogicPD OMAP3 boards There are five omap3 based boards from LogicPD. Two of them have added LTO support. Add the remaining three to use LTO. Signed-off-by: Adam Ford --- configs/omap35_logic_defconfig | 1 + configs/omap35_logic_somlv_defconfig | 1 + configs/omap3_logic_somlv_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 9d8ac94d2a..db38d78a57 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set CONFIG_SPL=y +CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index ee0c58ad2b..9abfe95434 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set CONFIG_SPL=y +CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index ece92fef61..fb1ee3ada0 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set CONFIG_SPL=y +CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set From bf4a54fa788237f54f28e333da4780870a44478f Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 26 Sep 2021 11:58:56 +0200 Subject: [PATCH 137/228] ARM: dts: am33xx-clocks: add spread spectrum support Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruh73x RM, SSC is supported only for LCD and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP). Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.it Signed-off-by: Dario Binacchi --- arch/arm/dts/am33xx-clocks.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi index 9221824390..44b6268ae3 100644 --- a/arch/arm/dts/am33xx-clocks.dtsi +++ b/arch/arm/dts/am33xx-clocks.dtsi @@ -167,7 +167,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -207,7 +207,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -223,7 +223,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { @@ -247,7 +247,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { @@ -264,7 +264,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; dpll_per_m2_ck: dpll_per_m2_ck@4ac { From 15a0411787e3ea70b93029500a644c1252bc4d0a Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 26 Sep 2021 11:58:57 +0200 Subject: [PATCH 138/228] ARM: dts: am43xx-clocks: add spread spectrum support Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruhl7x RM, SSC is supported only for LCD and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP, EXTDEV). Link: https://lore.kernel.org/r/20210606202253.31649-5-dariobin@libero.it Signed-off-by: Dario Binacchi --- arch/arm/dts/am43xx-clocks.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi index d0c0dfa4ec..b1127b5b91 100644 --- a/arch/arm/dts/am43xx-clocks.dtsi +++ b/arch/arm/dts/am43xx-clocks.dtsi @@ -199,7 +199,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -245,7 +245,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck { @@ -263,7 +263,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck { @@ -281,7 +281,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck { @@ -300,7 +300,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; dpll_per_m2_ck: dpll_per_m2_ck { @@ -583,7 +583,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck { From 165e8fe5db64542d64fff6f81edb77c350e993cf Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 26 Sep 2021 11:58:58 +0200 Subject: [PATCH 139/228] clk: ti: add am33xx/am43xx spread spectrum clock support The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it Signed-off-by: Dario Binacchi --- arch/arm/include/asm/arch-am33xx/clock.h | 12 +++ drivers/clk/ti/clk-am3-dpll.c | 131 ++++++++++++++++++++++- 2 files changed, 140 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 5d775902bb..79e3b8c7d9 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -78,6 +78,18 @@ #define CM_CLKSEL_DPLL_N_SHIFT 0 #define CM_CLKSEL_DPLL_N_MASK 0x7F +/* CM_SSC_DELTAM_DPLL */ +#define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0 +#define CM_SSC_DELTAM_DPLL_FRAC_MASK GENMASK(17, 0) +#define CM_SSC_DELTAM_DPLL_INT_SHIFT 18 +#define CM_SSC_DELTAM_DPLL_INT_MASK GENMASK(19, 18) + +/* CM_SSC_MODFREQ_DPLL */ +#define CM_SSC_MODFREQ_DPLL_MANT_SHIFT 0 +#define CM_SSC_MODFREQ_DPLL_MANT_MASK GENMASK(6, 0) +#define CM_SSC_MODFREQ_DPLL_EXP_SHIFT 7 +#define CM_SSC_MODFREQ_DPLL_EXP_MASK GENMASK(10, 8) + struct dpll_params { u32 m; u32 n; diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c index 916d308034..398a011a5c 100644 --- a/drivers/clk/ti/clk-am3-dpll.c +++ b/drivers/clk/ti/clk-am3-dpll.c @@ -27,11 +27,17 @@ struct clk_ti_am3_dpll_priv { struct clk_ti_reg clkmode_reg; struct clk_ti_reg idlest_reg; struct clk_ti_reg clksel_reg; + struct clk_ti_reg ssc_deltam_reg; + struct clk_ti_reg ssc_modfreq_reg; struct clk clk_bypass; struct clk clk_ref; u16 last_rounded_mult; u8 last_rounded_div; + u8 min_div; ulong max_rate; + u32 ssc_modfreq; + u32 ssc_deltam; + bool ssc_downspread; }; static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate) @@ -51,7 +57,7 @@ static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate) err = rate; err_min = rate; ref_rate = clk_get_rate(&priv->clk_ref); - for (d = 1; err_min && d <= 128; d++) { + for (d = priv->min_div; err_min && d <= 128; d++) { for (m = 2; m <= 2047; m++) { r = (ref_rate * m) / d; err = abs(r - rate); @@ -71,8 +77,8 @@ static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate) priv->last_rounded_mult = mult; priv->last_rounded_div = div; - dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate, - ret, mult, div); + dev_dbg(clk->dev, "rate=%ld, min-div: %d, best_rate=%ld, mult=%d, div=%d\n", + rate, priv->min_div, ret, mult, div); return ret; } @@ -107,6 +113,96 @@ static int clk_ti_am3_dpll_state(struct clk *clk, u8 state) return 0; } +/** + * clk_ti_am3_dpll_ssc_program - set spread-spectrum clocking registers + * @clk: struct clk * of DPLL to set + * + * Enable the DPLL spread spectrum clocking if frequency modulation and + * frequency spreading have been set, otherwise disable it. + */ +static void clk_ti_am3_dpll_ssc_program(struct clk *clk) +{ + struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev); + unsigned long ref_rate; + u32 v, ctrl, mod_freq_divider, exponent, mantissa; + u32 deltam_step, deltam_ceil; + + ctrl = clk_ti_readl(&priv->clkmode_reg); + + if (priv->ssc_modfreq && priv->ssc_deltam) { + ctrl |= CM_CLKMODE_DPLL_SSC_EN_MASK; + + if (priv->ssc_downspread) + ctrl |= CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK; + else + ctrl &= ~CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK; + + ref_rate = clk_get_rate(&priv->clk_ref); + mod_freq_divider = + (ref_rate / priv->last_rounded_div) / (4 * priv->ssc_modfreq); + if (priv->ssc_modfreq > (ref_rate / 70)) + dev_warn(clk->dev, + "clock: SSC modulation frequency of DPLL %s greater than %ld\n", + clk->dev->name, ref_rate / 70); + + exponent = 0; + mantissa = mod_freq_divider; + while ((mantissa > 127) && (exponent < 7)) { + exponent++; + mantissa /= 2; + } + if (mantissa > 127) + mantissa = 127; + + v = clk_ti_readl(&priv->ssc_modfreq_reg); + v &= ~(CM_SSC_MODFREQ_DPLL_MANT_MASK | CM_SSC_MODFREQ_DPLL_EXP_MASK); + v |= mantissa << __ffs(CM_SSC_MODFREQ_DPLL_MANT_MASK); + v |= exponent << __ffs(CM_SSC_MODFREQ_DPLL_EXP_MASK); + clk_ti_writel(v, &priv->ssc_modfreq_reg); + dev_dbg(clk->dev, + "mod_freq_divider: %u, exponent: %u, mantissa: %u, modfreq_reg: 0x%x\n", + mod_freq_divider, exponent, mantissa, v); + + deltam_step = priv->last_rounded_mult * priv->ssc_deltam; + deltam_step /= 10; + if (priv->ssc_downspread) + deltam_step /= 2; + + deltam_step <<= __ffs(CM_SSC_DELTAM_DPLL_INT_MASK); + deltam_step /= 100; + deltam_step /= mod_freq_divider; + if (deltam_step > 0xFFFFF) + deltam_step = 0xFFFFF; + + deltam_ceil = (deltam_step & CM_SSC_DELTAM_DPLL_INT_MASK) >> + __ffs(CM_SSC_DELTAM_DPLL_INT_MASK); + if (deltam_step & CM_SSC_DELTAM_DPLL_FRAC_MASK) + deltam_ceil++; + + if ((priv->ssc_downspread && + ((priv->last_rounded_mult - (2 * deltam_ceil)) < 20 || + priv->last_rounded_mult > 2045)) || + ((priv->last_rounded_mult - deltam_ceil) < 20 || + (priv->last_rounded_mult + deltam_ceil) > 2045)) + dev_warn(clk->dev, + "clock: SSC multiplier of DPLL %s is out of range\n", + clk->dev->name); + + v = clk_ti_readl(&priv->ssc_deltam_reg); + v &= ~(CM_SSC_DELTAM_DPLL_INT_MASK | CM_SSC_DELTAM_DPLL_FRAC_MASK); + v |= deltam_step << __ffs(CM_SSC_DELTAM_DPLL_INT_MASK | + CM_SSC_DELTAM_DPLL_FRAC_MASK); + clk_ti_writel(v, &priv->ssc_deltam_reg); + dev_dbg(clk->dev, + "deltam_step: %u, deltam_ceil: %u, deltam_reg: 0x%x\n", + deltam_step, deltam_ceil, v); + } else { + ctrl &= ~CM_CLKMODE_DPLL_SSC_EN_MASK; + } + + clk_ti_writel(ctrl, &priv->clkmode_reg); +} + static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate) { struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev); @@ -136,6 +232,8 @@ static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate) clk_ti_writel(v, &priv->clksel_reg); + clk_ti_am3_dpll_ssc_program(clk); + /* lock dpll */ clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK); @@ -229,6 +327,7 @@ static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev) struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev); struct clk_ti_am3_dpll_drv_data *data = (struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev); + u32 min_div; int err; priv->max_rate = data->max_rate; @@ -251,6 +350,32 @@ static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev) return err; } + err = clk_ti_get_reg_addr(dev, 3, &priv->ssc_deltam_reg); + if (err) { + dev_err(dev, "failed to get SSC deltam register\n"); + return err; + } + + err = clk_ti_get_reg_addr(dev, 4, &priv->ssc_modfreq_reg); + if (err) { + dev_err(dev, "failed to get SSC modfreq register\n"); + return err; + } + + if (dev_read_u32(dev, "ti,ssc-modfreq-hz", &priv->ssc_modfreq)) + priv->ssc_modfreq = 0; + + if (dev_read_u32(dev, "ti,ssc-deltam", &priv->ssc_deltam)) + priv->ssc_deltam = 0; + + priv->ssc_downspread = dev_read_bool(dev, "ti,ssc-downspread"); + + if (dev_read_u32(dev, "ti,min-div", &min_div) || min_div == 0 || + min_div > 128) + priv->min_div = 1; + else + priv->min_div = min_div; + return 0; } From 5134f79ee6b6bccbc5b4ef9272d05b52d75a40e3 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 3 Oct 2021 07:31:14 -0500 Subject: [PATCH 140/228] ARM: omap3_logic: Cleanup usage of MUX_VAL The macro called MUX_VAL generates a writel instruction with semicolon at the end. This table was written to use semicolons, however one was missed: MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ Since the extra semicolon is unnecessary with the use of the macro, remove all of them, and cleanup whitespace. Reviewed-by: Wolfgang Denk Suggested-by: Wolfgang Denk Signed-off-by: Adam Ford --- board/logicpd/omap3som/omap3logic.h | 386 ++++++++++++++-------------- 1 file changed, 193 insertions(+), 193 deletions(-) diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h index 0de1f2a54e..3a6f6c1f4e 100644 --- a/board/logicpd/omap3som/omap3logic.h +++ b/board/logicpd/omap3som/omap3logic.h @@ -45,209 +45,209 @@ const omap3_sysinfo sysinfo = { */ void set_muxconf_regs(void) { - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*SDRC_CKE0*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*SDRC_CKE1*/ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)) /*GPMC_nCS6*/ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) /*ETK_D0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) /*ETK_D1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) /*ETK_D2*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) /*ETK_D3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) /*ETK_D4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) /*ETK_D5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) /*ETK_D6*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) /*ETK_D7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) /*ETK_D8*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) /*ETK_D9*/ #ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/ #endif - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/ #ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/ #endif } From ce543d0d4ea39dae5828e59d21897a1a00b89ac4 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 5 Oct 2021 12:04:49 +0200 Subject: [PATCH 141/228] board: siemens: iot2050: Adjust to changes in DT and configuration Account for the changes done between merge proposal and the final merge. Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini --- arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi | 2 +- configs/iot2050_defconfig | 6 ++++-- include/configs/iot2050.h | 2 -- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index 88c36fcf43..286e25f379 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -35,7 +35,7 @@ &cbass_main { u-boot,dm-spl; - main-navss { + main_navss: bus@30800000 { u-boot,dm-spl; }; }; diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 72ee5c83f1..84e387a099 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -10,15 +11,16 @@ CONFIG_TARGET_IOT2050_A53=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic" CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ENV_OFFSET_REDUND=0x6a0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index ddb4cfcc8e..91ed76bb40 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -17,8 +17,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #define CONFIG_SYS_BOOTM_LEN SZ_64M From 08ad739f382dae83d5bb30fa43e56d19b14daa20 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 5 Oct 2021 12:04:50 +0200 Subject: [PATCH 142/228] arm: dts: Update IOT2050 device tree files This fixes the usage of the USB 3.0-capable port under U-Boot as USB 2.0-only port. Original patch by Chao Zeng. Signed-off-by: Jan Kiszka --- .../k3-am65-iot2050-common-pg2-u-boot.dtsi | 27 +++++++++++++++++++ arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi | 4 ++- 2 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi new file mode 100644 index 0000000000..64dddce648 --- /dev/null +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2018-2021 + * + * Authors: + * Chao Zeng + * + * U-Boot bits of the IOT2050 Advanced PG2 variants + * (downgrade of usb0 to USB 2.0 mode) + */ + +&serdes0 { + status = "disabled"; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ + /delete-property/ phys; + /delete-property/ phy-names; +}; + +&usb0 { + maximum-speed = "high-speed"; + /delete-property/ snps,dis-u1-entry-quirk; + /delete-property/ snps,dis-u2-entry-quirk; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi index c25bce7339..e7e0ca4159 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-pg2.dtsi @@ -44,8 +44,10 @@ phy-names = "usb3-phy"; }; -&usb0_phy { +&usb0 { maximum-speed = "super-speed"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; }; + +#include "k3-am65-iot2050-common-pg2-u-boot.dtsi" From 7f51b554be381c99a24d37945038099a82d7993e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:14 -0500 Subject: [PATCH 143/228] power: pmic: Consistently depend on DM_PMIC Kconfig symbols for two PMIC drivers (PMIC_AS3722 and DM_PMIC_MC34708) were missing a dependency on DM_PMIC. To fix this inconsistency, and to keep it from happening again, wrap the driver section with "if DM_PMIC" instead of using a "depends on DM_PMIC" clause for each driver. Reviewed-by: Igor Opaniuk Reviewed-by: Jaehoon Chung Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- drivers/power/pmic/Kconfig | 46 ++++++++------------------------------ 1 file changed, 9 insertions(+), 37 deletions(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index cf2a9b2c17..2472555a3f 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -10,10 +10,12 @@ config DM_PMIC - 'drivers/power/pmic/pmic-uclass.c' - 'include/power/pmic.h' +if DM_PMIC + config SPL_DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" depends on SPL_DM - default y if DM_PMIC + default y ---help--- This config enables the driver-model PMIC support in SPL. UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. @@ -25,7 +27,6 @@ config SPL_DM_PMIC config PMIC_CHILDREN bool "Allow child devices for PMICs" - depends on DM_PMIC default y ---help--- This allows PMICs to support child devices (such as regulators) in @@ -35,7 +36,6 @@ config PMIC_CHILDREN config SPL_PMIC_CHILDREN bool "Allow child devices for PMICs in SPL" - depends on DM_PMIC default y ---help--- This allows PMICs to support child devices (such as regulators) in @@ -46,7 +46,6 @@ config SPL_PMIC_CHILDREN config PMIC_AB8500 bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU" - depends on DM_PMIC select REGMAP select SYSCON help @@ -56,7 +55,7 @@ config PMIC_AB8500 config PMIC_ACT8846 bool "Enable support for the active-semi 8846 PMIC" - depends on DM_PMIC && DM_I2C + depends on DM_I2C ---help--- This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout regulators (LDOs). It also provides some GPIO, reset and battery @@ -65,14 +64,13 @@ config PMIC_ACT8846 config DM_PMIC_DA9063 bool "Enable Driver Model for the Dialog DA9063 PMIC" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC DA9063. The driver implements read/write operations. config SPL_DM_PMIC_DA9063 bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL" - depends on DM_PMIC && SPL + depends on SPL help This config enables implementation of driver-model pmic uclass features for PMIC DA9063. The driver implements read/write operations. @@ -87,14 +85,12 @@ config PMIC_AS3722 config DM_PMIC_BD71837 bool "Enable Driver Model for PMIC BD71837" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC BD71837. The driver implements read/write operations. config SPL_DM_PMIC_BD71837 bool "Enable Driver Model for PMIC BD71837 in SPL stage" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC BD71837. The driver implements read/write @@ -102,7 +98,7 @@ config SPL_DM_PMIC_BD71837 config DM_PMIC_FAN53555 bool "Enable support for OnSemi FAN53555" - depends on DM_PMIC && DM_REGULATOR && DM_I2C + depends on DM_REGULATOR && DM_I2C select DM_REGULATOR_FAN53555 help This config enables implementation of driver-model PMIC @@ -116,14 +112,12 @@ config DM_PMIC_FAN53555 config DM_PMIC_MP5416 bool "Enable Driver Model for PMIC MP5416" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC MP5416. The driver implements read/write operations. config SPL_DM_PMIC_MP5416 bool "Enable Driver Model for PMIC MP5416 in SPL stage" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC MP5416. The driver implements read/write @@ -131,56 +125,48 @@ config SPL_DM_PMIC_MP5416 config DM_PMIC_PCA9450 bool "Enable Driver Model for PMIC PCA9450" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC PCA9450. The driver implements read/write operations. config SPL_DM_PMIC_PCA9450 bool "Enable Driver Model for PMIC PCA9450" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC PCA9450 in SPL. The driver implements read/write operations. config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" - depends on DM_PMIC ---help--- This config enables implementation of driver-model pmic uclass features for PMIC PFUZE100. The driver implements read/write operations. config SPL_DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100 in SPL" - depends on DM_PMIC ---help--- This config enables implementation of driver-model pmic uclass features for PMIC PFUZE100 in SPL. The driver implements read/write operations. config DM_PMIC_MAX77686 bool "Enable Driver Model for PMIC MAX77686" - depends on DM_PMIC ---help--- This config enables implementation of driver-model pmic uclass features for PMIC MAX77686. The driver implements read/write operations. config DM_PMIC_MAX8998 bool "Enable Driver Model for PMIC MAX8998" - depends on DM_PMIC ---help--- This config enables implementation of driver-model pmic uclass features for PMIC MAX8998. The driver implements read/write operations. config DM_PMIC_MC34708 bool "Enable Driver Model for PMIC MC34708" - depends on DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC MC34708. The driver implements read/write operations. config PMIC_MAX8997 bool "Enable Driver Model for PMIC MAX8997" - depends on DM_PMIC ---help--- This config enables implementation of driver-model pmic uclass features for PMIC MAX8997. The driver implements read/write operations. @@ -195,7 +181,6 @@ config PMIC_MAX8997 config PMIC_PM8916 bool "Enable Driver Model for Qualcomm PM8916 PMIC" - depends on DM_PMIC ---help--- The PM8916 is a PMIC connected to one (or several) processors with SPMI bus. It has 2 slaves with several peripherals: @@ -211,7 +196,6 @@ config PMIC_PM8916 config PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" - depends on DM_PMIC ---help--- The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, an RTC and two low Rds (resistance (drain to source)) switches. It is @@ -220,7 +204,6 @@ config PMIC_RK8XX config SPL_PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" - depends on DM_PMIC ---help--- The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, an RTC and two low Rds (resistance (drain to source)) switches. It is @@ -229,7 +212,6 @@ config SPL_PMIC_RK8XX config PMIC_S2MPS11 bool "Enable Driver Model for PMIC Samsung S2MPS11" - depends on DM_PMIC ---help--- The Samsung S2MPS11 PMIC provides: - 38 adjustable LDO regulators @@ -243,7 +225,6 @@ config PMIC_S2MPS11 config DM_PMIC_SANDBOX bool "Enable Driver Model for emulated Sandbox PMIC" - depends on DM_PMIC ---help--- Enable the driver for Sandbox PMIC emulation. The emulated PMIC device depends on two drivers: @@ -268,7 +249,6 @@ config DM_PMIC_SANDBOX config PMIC_S5M8767 bool "Enable Driver Model for the Samsung S5M8767 PMIC" - depends on DM_PMIC ---help--- The S5M8767 PMIC provides a large array of LDOs and BUCKs for use as a SoC power controller. It also provides 32KHz clock outputs. This @@ -277,7 +257,6 @@ config PMIC_S5M8767 config PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC" - depends on DM_PMIC ---help--- The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO regulators Real-Time Clock and 4 GPIOs. This driver provides @@ -285,7 +264,6 @@ config PMIC_RN5T567 config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" - depends on DM_PMIC ---help--- The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, FETs and a battery charger. This driver provides register access @@ -294,21 +272,18 @@ config PMIC_TPS65090 config PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" - depends on DM_PMIC ---help--- The PALMAS is a PMIC containing several LDOs, SMPS. This driver binds the pmic children. config PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" - depends on DM_PMIC ---help--- The LP873X is a PMIC containing couple of LDOs and couple of SMPS. This driver binds the pmic children. config PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" - depends on DM_PMIC ---help--- The LP87565 is a PMIC containing a bunch of SMPS. This driver binds the pmic children. @@ -322,7 +297,6 @@ config POWER_MC34VR500 config DM_PMIC_TPS65910 bool "Enable driver for Texas Instruments TPS65910 PMIC" - depends on DM_PMIC ---help--- The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO @@ -330,7 +304,7 @@ config DM_PMIC_TPS65910 config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" - depends on DM_PMIC && DM_I2C + depends on DM_I2C select SYSRESET_CMD_POWEROFF if CMD_POWEROFF && !ARM_PSCI_FW ---help--- The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. @@ -339,28 +313,26 @@ config PMIC_STPMIC1 config SPL_PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" - depends on DM_PMIC help The PALMAS is a PMIC containing several LDOs, SMPS. This driver binds the pmic children in SPL. config SPL_PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" - depends on DM_PMIC help The LP873X is a PMIC containing couple of LDOs and couple of SMPS. This driver binds the pmic children in SPL. config SPL_PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" - depends on DM_PMIC help The LP87565 is a PMIC containing a bunch of SMPS. This driver binds the pmic children in SPL. config PMIC_TPS65941 bool "Enable driver for Texas Instruments TPS65941 PMIC" - depends on DM_PMIC help The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. This driver binds the pmic children. + +endif From 3fd90e43d9238d5b24f1d71a5eadb5ac2b51e4a8 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:15 -0500 Subject: [PATCH 144/228] power: pmic: Consistently depend on SPL_DM_PMIC Now that there is a separate symbol to enable DM_PMIC in SPL, update the the SPL-specific driver symbols to depend on this new option. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/power/pmic/Kconfig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 2472555a3f..e8a04325f8 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -36,6 +36,7 @@ config PMIC_CHILDREN config SPL_PMIC_CHILDREN bool "Allow child devices for PMICs in SPL" + depends on SPL_DM_PMIC default y ---help--- This allows PMICs to support child devices (such as regulators) in @@ -70,7 +71,7 @@ config DM_PMIC_DA9063 config SPL_DM_PMIC_DA9063 bool "Enable Driver Model for the Dialog DA9063 PMIC in SPL" - depends on SPL + depends on SPL_DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC DA9063. The driver implements read/write operations. @@ -91,6 +92,7 @@ config DM_PMIC_BD71837 config SPL_DM_PMIC_BD71837 bool "Enable Driver Model for PMIC BD71837 in SPL stage" + depends on SPL_DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC BD71837. The driver implements read/write @@ -118,6 +120,7 @@ config DM_PMIC_MP5416 config SPL_DM_PMIC_MP5416 bool "Enable Driver Model for PMIC MP5416 in SPL stage" + depends on SPL_DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC MP5416. The driver implements read/write @@ -131,6 +134,7 @@ config DM_PMIC_PCA9450 config SPL_DM_PMIC_PCA9450 bool "Enable Driver Model for PMIC PCA9450" + depends on SPL_DM_PMIC help This config enables implementation of driver-model pmic uclass features for PMIC PCA9450 in SPL. The driver implements read/write operations. @@ -143,6 +147,7 @@ config DM_PMIC_PFUZE100 config SPL_DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100 in SPL" + depends on SPL_DM_PMIC ---help--- This config enables implementation of driver-model pmic uclass features for PMIC PFUZE100 in SPL. The driver implements read/write operations. @@ -204,6 +209,7 @@ config PMIC_RK8XX config SPL_PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" + depends on SPL_DM_PMIC ---help--- The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, an RTC and two low Rds (resistance (drain to source)) switches. It is @@ -313,18 +319,21 @@ config PMIC_STPMIC1 config SPL_PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" + depends on SPL_DM_PMIC help The PALMAS is a PMIC containing several LDOs, SMPS. This driver binds the pmic children in SPL. config SPL_PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" + depends on SPL_DM_PMIC help The LP873X is a PMIC containing couple of LDOs and couple of SMPS. This driver binds the pmic children in SPL. config SPL_PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" + depends on SPL_DM_PMIC help The LP87565 is a PMIC containing a bunch of SMPS. This driver binds the pmic children in SPL. From 526c4f2e43bb61b849817ed069607dd2c475a17c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:16 -0500 Subject: [PATCH 145/228] power: pmic: Add a driver for X-Powers AXP PMICs These PMICs provide some combination of battery charger, fuel gauge, GPIOs, regulators, and VBUS routing. These functions are represented as child nodes in the device tree. Add the minimal driver needed to probe these child devices and provide the DM_PMIC ops. Enable the driver by default for SoCs that normally pair with a PMIC. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/power/pmic/Kconfig | 14 ++++++++++++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/axp.c | 38 +++++++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 drivers/power/pmic/axp.c diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index e8a04325f8..fcb517f104 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -63,6 +63,20 @@ config PMIC_ACT8846 functions. It uses an I2C interface and is designed for use with tablets and smartphones. +config PMIC_AXP + bool "Enable Driver Model for X-Powers AXP PMICs" + depends on DM_I2C + help + This config enables driver-model PMIC uclass features for + X-Powers AXP152, AXP2xx, and AXP8xx PMICs. + +config SPL_PMIC_AXP + bool "Enable Driver Model for X-Powers AXP PMICs in SPL" + depends on SPL_DM_I2C && SPL_DM_PMIC + help + This config enables driver-model PMIC uclass features in the SPL for + X-Powers AXP152, AXP2xx, and AXP8xx PMICs. + config DM_PMIC_DA9063 bool "Enable Driver Model for the Dialog DA9063 PMIC" help diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 5250eac12f..e1922df00f 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_AB8500) += ab8500.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o +obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c new file mode 100644 index 0000000000..74c94bdb47 --- /dev/null +++ b/drivers/power/pmic/axp.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include + +static int axp_pmic_reg_count(struct udevice *dev) +{ + /* TODO: Get the specific value from driver data. */ + return 0x100; +} + +static struct dm_pmic_ops axp_pmic_ops = { + .reg_count = axp_pmic_reg_count, + .read = dm_i2c_read, + .write = dm_i2c_write, +}; + +static const struct udevice_id axp_pmic_ids[] = { + { .compatible = "x-powers,axp152" }, + { .compatible = "x-powers,axp202" }, + { .compatible = "x-powers,axp209" }, + { .compatible = "x-powers,axp221" }, + { .compatible = "x-powers,axp223" }, + { .compatible = "x-powers,axp803" }, + { .compatible = "x-powers,axp806" }, + { .compatible = "x-powers,axp809" }, + { .compatible = "x-powers,axp813" }, + { } +}; + +U_BOOT_DRIVER(axp_pmic) = { + .name = "axp_pmic", + .id = UCLASS_PMIC, + .of_match = axp_pmic_ids, + .bind = dm_scan_fdt_dev, + .ops = &axp_pmic_ops, +}; From ea261fdeb23d54ee17a5e5a95cf35f97180deb76 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:17 -0500 Subject: [PATCH 146/228] sunxi: Only initialize legacy I2C when enabled CONFIG_SPL_I2C is the wrong symbol to use here. It is the top-level Kconfig symbol (not specific to either legacy or DM I2C), whereas the i2c_init() function is specific to legacy I2C. This change fixes a build failure when enabling SPL_I2C but not SPL_SYS_I2C_LEGACY. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-by: Andre Przywara --- arch/arm/mach-sunxi/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 373cb56db4..b4ba2a72c4 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -338,7 +338,7 @@ void board_init_f(ulong dummy) spl_init(); preloader_console_init(); -#ifdef CONFIG_SPL_I2C +#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) /* Needed early by sunxi_board_init if PMU is enabled */ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif From abd2e783f15ce372e275eb66f732c4edbaf0c0b6 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:18 -0500 Subject: [PATCH 147/228] sunxi: Select SUN8I_RSB more carefully SUN8I_RSB should not be selected by MACH_SUN8I, because the hardware is not present in half of those SoCs (H3/H5, R40, and V3s). Move the selection to the SoCs where the hardware actually exists. As it currently stands, selecting that option also requires using it in some way, which is not the case for one A80 board. Since we have only three A80 boards in total, we select it their via their defconfigs. Reviewed-by: Andre Przywara Signed-off-by: Samuel Holland [Andre: fixing up Sunchip_CX-A99 build] Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 5 +++-- configs/Cubieboard4_defconfig | 1 + configs/Merrii_A80_Optimus_defconfig | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 7308f977a5..03054a331a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -260,6 +260,7 @@ config MACH_SUN8I_A23 select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A23 select PHY_SUN4I_USB + select SUN8I_RSB select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT @@ -273,6 +274,7 @@ config MACH_SUN8I_A33 select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A33 select PHY_SUN4I_USB + select SUN8I_RSB select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT @@ -283,6 +285,7 @@ config MACH_SUN8I_A83T select CPU_V7A select DRAM_SUN8I_A83T select PHY_SUN4I_USB + select SUN8I_RSB select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE select MMC_SUNXI_HAS_MODE_SWITCH @@ -329,7 +332,6 @@ config MACH_SUN9I select DRAM_SUN9I select SUN6I_PRCM select SUNXI_GEN_SUN6I - select SUN8I_RSB select SUPPORT_SPL config MACH_SUN50I @@ -377,7 +379,6 @@ endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool - select SUN8I_RSB select SUN6I_PRCM default y if MACH_SUN8I_A23 default y if MACH_SUN8I_A33 diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index c66f29e5da..0377bb83da 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -11,5 +11,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" +CONFIG_SUN8I_RSB=y CONFIG_AXP_GPIO=y CONFIG_AXP809_POWER=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 0944e64957..8fb6504209 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -11,5 +11,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" +CONFIG_SUN8I_RSB=y CONFIG_AXP_GPIO=y CONFIG_AXP809_POWER=y From 4ab39e74b640799748dfdef49f099b416a5ae497 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:19 -0500 Subject: [PATCH 148/228] sunxi: pmic_bus: Fix Kconfig dependencies AXP_PMIC_BUS enables communication with a specific AXP PMIC at a PMIC-dependent I2C/P2WI/RSB bus address. It is automatically selected as a dependency of the PMIC driver. It should not be selectable by the user when no PMIC is chosen. AXP_GPIO uses the pmic_bus functions, and also depends on a specific PMIC header to pick up register definitions. Both of these changes have no impact on any existing configs, since the code does not compile if the dependencies are not met. Reviewed-by: Jaehoon Chung Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 03054a331a..da35cc87e8 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -106,7 +106,7 @@ config SUN6I_PRCM in A31 SoC. config AXP_PMIC_BUS - bool "Sunxi AXP PMIC bus access helpers" + bool help Select this PMIC bus access helpers for Sunxi platform PRCM or other AXP family PMIC devices. @@ -795,6 +795,7 @@ endif config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" + depends on AXP_PMIC_BUS ---help--- Say Y here to enable support for the gpio pins of the axp PMIC ICs. From 104950a7feae7926e40676f27cfbd279a43b4bc3 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:20 -0500 Subject: [PATCH 149/228] i2c: Add a DM_I2C driver for the sun6i P2WI controller This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the p2wi functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants. Move that to the common header, so it can be used by both interface implementations. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 14 +-- arch/arm/mach-sunxi/Makefile | 1 - arch/arm/mach-sunxi/p2wi.c | 117 ------------------ arch/arm/mach-sunxi/pmic_bus.c | 7 +- drivers/i2c/Kconfig | 8 ++ drivers/i2c/Makefile | 1 + drivers/i2c/sun6i_p2wi.c | 220 +++++++++++++++++++++++++++++++++ include/axp_pmic.h | 6 + 8 files changed, 240 insertions(+), 134 deletions(-) delete mode 100644 arch/arm/mach-sunxi/p2wi.c create mode 100644 drivers/i2c/sun6i_p2wi.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index da35cc87e8..f4a45284bd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -88,17 +88,6 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE feature. endif -config SUN6I_P2WI - bool "Allwinner sun6i internal P2WI controller" - help - If you say yes to this option, support will be included for the - P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi - SOCs. - The P2WI looks like an SMBus controller (which supports only byte - accesses), except that it only supports one slave device. - This interface is used to connect to specific PMIC devices (like the - AXP221). - config SUN6I_PRCM bool help @@ -232,10 +221,11 @@ config MACH_SUN6I select ARCH_SUPPORT_PSCI select DRAM_SUN6I select PHY_SUN4I_USB - select SUN6I_P2WI + select SPL_I2C select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SYS_I2C_SUN6I_P2WI select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN7I diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 3f081d92f3..c9312bb393 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -11,7 +11,6 @@ obj-y += clock.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-y += pinmux.o -obj-$(CONFIG_SUN6I_P2WI) += p2wi.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o obj-$(CONFIG_SUN8I_RSB) += rsb.o diff --git a/arch/arm/mach-sunxi/p2wi.c b/arch/arm/mach-sunxi/p2wi.c deleted file mode 100644 index 7c5c12254e..0000000000 --- a/arch/arm/mach-sunxi/p2wi.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Sunxi A31 Power Management Unit - * - * (C) Copyright 2013 Oliver Schinagl - * http://linux-sunxi.org - * - * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work - * - * (C) Copyright 2006-2013 - * Allwinner Technology Co., Ltd. - * Berg Xing - * Tom Cubie - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void p2wi_init(void) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - - /* Enable p2wi and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); - - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); - - /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ - writel(P2WI_CTRL_RESET, &p2wi->ctrl); - sdelay(0x100); - writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), - &p2wi->cc); -} - -int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - unsigned long tmo = timer_get_us() + 1000000; - - writel(P2WI_PM_DEV_ADDR(slave_addr) | - P2WI_PM_CTRL_ADDR(ctrl_reg) | - P2WI_PM_INIT_DATA(init_data) | - P2WI_PM_INIT_SEND, - &p2wi->pm); - - while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { - if (timer_get_us() > tmo) - return -ETIME; - } - - return 0; -} - -static int p2wi_await_trans(void) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - unsigned long tmo = timer_get_us() + 1000000; - int ret; - u8 reg; - - while (1) { - reg = readl(&p2wi->status); - if (reg & P2WI_STAT_TRANS_ERR) { - ret = -EIO; - break; - } - if (reg & P2WI_STAT_TRANS_DONE) { - ret = 0; - break; - } - if (timer_get_us() > tmo) { - ret = -ETIME; - break; - } - } - writel(reg, &p2wi->status); /* Clear status bits */ - return ret; -} - -int p2wi_read(const u8 addr, u8 *data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - int ret; - - writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); - writel(P2WI_DATA_NUM_BYTES(1) | - P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); - writel(P2WI_STAT_TRANS_DONE, &p2wi->status); - writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); - - ret = p2wi_await_trans(); - - *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; - return ret; -} - -int p2wi_write(const u8 addr, u8 data) -{ - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; - - writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); - writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); - writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); - writel(P2WI_STAT_TRANS_DONE, &p2wi->status); - writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); - - return p2wi_await_trans(); -} diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 0394ce8564..673a05fdd1 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -8,6 +8,7 @@ * axp223 uses the rsb bus, these functions abstract this. */ +#include #include #include #include @@ -21,8 +22,6 @@ #define AXP305_I2C_ADDR 0x36 #define AXP221_CHIP_ADDR 0x68 -#define AXP221_CTRL_ADDR 0x3e -#define AXP221_INIT_DATA 0x3e /* AXP818 device and runtime addresses are same as AXP223 */ #define AXP223_DEVICE_ADDR 0x3a3 @@ -40,8 +39,8 @@ int pmic_bus_init(void) #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER # ifdef CONFIG_MACH_SUN6I p2wi_init(); - ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, - AXP221_INIT_DATA); + ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP_PMIC_MODE_REG, + AXP_PMIC_MODE_P2WI); # elif defined CONFIG_MACH_SUN8I_R40 /* Nothing. R40 uses the AXP221s in I2C mode */ ret = 0; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 57cac4483f..0adf143abf 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -575,6 +575,14 @@ config SYS_I2C_STM32F7 _ Optional clock stretching _ Software reset +config SYS_I2C_SUN6I_P2WI + bool "Allwinner sun6i P2WI controller" + depends on ARCH_SUNXI + help + Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded + in the Allwinner A31 and A31s SOCs. This interface is used to connect + to specific devices like the X-Powers AXP221 PMIC. + config SYS_I2C_SYNQUACER bool "Socionext SynQuacer I2C controller" depends on ARCH_SYNQUACER && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 67841bf3e0..0a2cc64193 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o +obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c new file mode 100644 index 0000000000..c9e1b3fcd5 --- /dev/null +++ b/drivers/i2c/sun6i_p2wi.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. + * Berg Xing + * Tom Cubie + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int sun6i_p2wi_await_trans(struct sunxi_p2wi_reg *base) +{ + unsigned long tmo = timer_get_us() + 1000000; + int ret; + u8 reg; + + while (1) { + reg = readl(&base->status); + if (reg & P2WI_STAT_TRANS_ERR) { + ret = -EIO; + break; + } + if (reg & P2WI_STAT_TRANS_DONE) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(reg, &base->status); /* Clear status bits */ + + return ret; +} + +static int sun6i_p2wi_read(struct sunxi_p2wi_reg *base, const u8 addr, u8 *data) +{ + int ret; + + writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0); + writel(P2WI_DATA_NUM_BYTES(1) | + P2WI_DATA_NUM_BYTES_READ, &base->numbytes); + writel(P2WI_STAT_TRANS_DONE, &base->status); + writel(P2WI_CTRL_TRANS_START, &base->ctrl); + + ret = sun6i_p2wi_await_trans(base); + + *data = readl(&base->data0) & P2WI_DATA_BYTE_1_MASK; + + return ret; +} + +static int sun6i_p2wi_write(struct sunxi_p2wi_reg *base, const u8 addr, u8 data) +{ + writel(P2WI_DATADDR_BYTE_1(addr), &base->dataddr0); + writel(P2WI_DATA_BYTE_1(data), &base->data0); + writel(P2WI_DATA_NUM_BYTES(1), &base->numbytes); + writel(P2WI_STAT_TRANS_DONE, &base->status); + writel(P2WI_CTRL_TRANS_START, &base->ctrl); + + return sun6i_p2wi_await_trans(base); +} + +static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base, + u8 slave_addr, u8 ctrl_reg, + u8 init_data) +{ + unsigned long tmo = timer_get_us() + 1000000; + + writel(P2WI_PM_DEV_ADDR(slave_addr) | + P2WI_PM_CTRL_ADDR(ctrl_reg) | + P2WI_PM_INIT_DATA(init_data) | + P2WI_PM_INIT_SEND, + &base->pm); + + while ((readl(&base->pm) & P2WI_PM_INIT_SEND)) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return 0; +} + +static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base) +{ + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); + + /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ + writel(P2WI_CTRL_RESET, &base->ctrl); + sdelay(0x100); + writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), + &base->cc); +} + +#if IS_ENABLED(CONFIG_AXP_PMIC_BUS) +int p2wi_read(const u8 addr, u8 *data) +{ + struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + return sun6i_p2wi_read(base, addr, data); +} + +int p2wi_write(const u8 addr, u8 data) +{ + struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + return sun6i_p2wi_write(base, addr, data); +} + +int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) +{ + struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg, + init_data); +} + +void p2wi_init(void) +{ + struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + + sun6i_p2wi_init(base); +} +#endif + +#if CONFIG_IS_ENABLED(DM_I2C) +struct sun6i_p2wi_priv { + struct sunxi_p2wi_reg *base; +}; + +static int sun6i_p2wi_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct sun6i_p2wi_priv *priv = dev_get_priv(bus); + + /* The hardware only supports SMBus-style transfers. */ + if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1) + return sun6i_p2wi_read(priv->base, + msg[0].buf[0], &msg[1].buf[0]); + + if (nmsgs == 1 && msg[0].len == 2) + return sun6i_p2wi_write(priv->base, + msg[0].buf[0], msg[0].buf[1]); + + return -EINVAL; +} + +static int sun6i_p2wi_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct sun6i_p2wi_priv *priv = dev_get_priv(bus); + + return sun6i_p2wi_change_to_p2wi_mode(priv->base, chip_addr, + AXP_PMIC_MODE_REG, + AXP_PMIC_MODE_P2WI); +} + +static int sun6i_p2wi_probe(struct udevice *bus) +{ + struct sun6i_p2wi_priv *priv = dev_get_priv(bus); + + priv->base = dev_read_addr_ptr(bus); + + sun6i_p2wi_init(priv->base); + + return 0; +} + +static int sun6i_p2wi_child_pre_probe(struct udevice *child) +{ + struct dm_i2c_chip *chip = dev_get_parent_plat(child); + + /* Ensure each transfer is for a single register. */ + chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; + + return 0; +} + +static const struct dm_i2c_ops sun6i_p2wi_ops = { + .xfer = sun6i_p2wi_xfer, + .probe_chip = sun6i_p2wi_probe_chip, +}; + +static const struct udevice_id sun6i_p2wi_ids[] = { + { .compatible = "allwinner,sun6i-a31-p2wi" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sun6i_p2wi) = { + .name = "sun6i_p2wi", + .id = UCLASS_I2C, + .of_match = sun6i_p2wi_ids, + .probe = sun6i_p2wi_probe, + .child_pre_probe = sun6i_p2wi_child_pre_probe, + .priv_auto = sizeof(struct sun6i_p2wi_priv), + .ops = &sun6i_p2wi_ops, +}; +#endif /* CONFIG_IS_ENABLED(DM_I2C) */ diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 405044c3a3..0db3e143ed 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -6,6 +6,8 @@ */ #ifndef _AXP_PMIC_H_ +#include + #ifdef CONFIG_AXP152_POWER #include #endif @@ -25,6 +27,10 @@ #include #endif +#define AXP_PMIC_MODE_REG 0x3e +#define AXP_PMIC_MODE_I2C 0x00 +#define AXP_PMIC_MODE_P2WI 0x3e + int axp_set_dcdc1(unsigned int mvolt); int axp_set_dcdc2(unsigned int mvolt); int axp_set_dcdc3(unsigned int mvolt); From 3227c85fe76312290c3ec15a02dcba3f9c6bc399 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:21 -0500 Subject: [PATCH 150/228] i2c: Add a DM_I2C driver for the sun8i RSB controller This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the rsb functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants, so move that to the common header. There are only a couple of pairs of hardware/runtime addresses used across all PMIC variants. So far the code expected only the "primary" pair, but some PMICs like the AXP305 and AXP805 use the secondary pair, so add support for that to the DM driver as well. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 18 +- arch/arm/mach-sunxi/Makefile | 1 - arch/arm/mach-sunxi/pmic_bus.c | 11 +- arch/arm/mach-sunxi/rsb.c | 175 ----------------- configs/Cubieboard4_defconfig | 2 +- configs/Merrii_A80_Optimus_defconfig | 2 +- drivers/i2c/Kconfig | 8 + drivers/i2c/Makefile | 1 + drivers/i2c/sun8i_rsb.c | 281 +++++++++++++++++++++++++++ include/axp_pmic.h | 6 + 10 files changed, 309 insertions(+), 196 deletions(-) delete mode 100644 arch/arm/mach-sunxi/rsb.c create mode 100644 drivers/i2c/sun8i_rsb.c diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index f4a45284bd..10401d3249 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -100,14 +100,6 @@ config AXP_PMIC_BUS Select this PMIC bus access helpers for Sunxi platform PRCM or other AXP family PMIC devices. -config SUN8I_RSB - bool "Allwinner sunXi Reduced Serial Bus Driver" - help - Say y here to enable support for Allwinner's Reduced Serial Bus - (RSB) support. This controller is responsible for communicating - with various RSB based devices, such as AXP223, AXP8XX PMICs, - and AC100/AC200 ICs. - config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 @@ -250,9 +242,10 @@ config MACH_SUN8I_A23 select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A23 select PHY_SUN4I_USB - select SUN8I_RSB + select SPL_I2C select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SYS_I2C_SUN8I_RSB select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT imply CONS_INDEX_5 if !DM_SERIAL @@ -264,9 +257,10 @@ config MACH_SUN8I_A33 select ARCH_SUPPORT_PSCI select DRAM_SUN8I_A33 select PHY_SUN4I_USB - select SUN8I_RSB + select SPL_I2C select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SYS_I2C_SUN8I_RSB select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT imply CONS_INDEX_5 if !DM_SERIAL @@ -275,11 +269,12 @@ config MACH_SUN8I_A83T select CPU_V7A select DRAM_SUN8I_A83T select PHY_SUN4I_USB - select SUN8I_RSB + select SPL_I2C select SUNXI_GEN_SUN6I select MMC_SUNXI_HAS_NEW_MODE select MMC_SUNXI_HAS_MODE_SWITCH select SUPPORT_SPL + select SYS_I2C_SUN8I_RSB config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" @@ -320,6 +315,7 @@ config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7A select DRAM_SUN9I + select SPL_I2C select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index c9312bb393..5d3fd70f74 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -13,7 +13,6 @@ obj-y += dram_helpers.o obj-y += pinmux.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o -obj-$(CONFIG_SUN8I_RSB) += rsb.o obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 673a05fdd1..827797249e 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -23,10 +23,6 @@ #define AXP221_CHIP_ADDR 0x68 -/* AXP818 device and runtime addresses are same as AXP223 */ -#define AXP223_DEVICE_ADDR 0x3a3 -#define AXP223_RUNTIME_ADDR 0x2d - int pmic_bus_init(void) { /* This cannot be 0 because it is used in SPL before BSS is ready */ @@ -49,7 +45,8 @@ int pmic_bus_init(void) if (ret) return ret; - ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR); + ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, + AXP_PMIC_PRI_RUNTIME_ADDR); # endif if (ret) return ret; @@ -73,7 +70,7 @@ int pmic_bus_read(u8 reg, u8 *data) # elif defined CONFIG_MACH_SUN8I_R40 return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); # else - return rsb_read(AXP223_RUNTIME_ADDR, reg, data); + return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); # endif #endif } @@ -92,7 +89,7 @@ int pmic_bus_write(u8 reg, u8 data) # elif defined CONFIG_MACH_SUN8I_R40 return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); # else - return rsb_write(AXP223_RUNTIME_ADDR, reg, data); + return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); # endif #endif } diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c deleted file mode 100644 index 01bb09b747..0000000000 --- a/arch/arm/mach-sunxi/rsb.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2014 Hans de Goede - * - * Based on allwinner u-boot sources rsb code which is: - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. - * lixiang - */ - -#include -#include -#include -#include -#include -#include -#include - -static int rsb_set_device_mode(void); - -static void rsb_cfg_io(void) -{ -#ifdef CONFIG_MACH_SUN8I - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPL(0), 1); - sunxi_gpio_set_pull(SUNXI_GPL(1), 1); - sunxi_gpio_set_drv(SUNXI_GPL(0), 2); - sunxi_gpio_set_drv(SUNXI_GPL(1), 2); -#elif defined CONFIG_MACH_SUN9I - sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); - sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); - sunxi_gpio_set_pull(SUNXI_GPN(0), 1); - sunxi_gpio_set_pull(SUNXI_GPN(1), 1); - sunxi_gpio_set_drv(SUNXI_GPN(0), 2); - sunxi_gpio_set_drv(SUNXI_GPN(1), 2); -#else -#error unsupported MACH_SUNXI -#endif -} - -static void rsb_set_clk(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - u32 div = 0; - u32 cd_odly = 0; - - /* Source is Hosc24M, set RSB clk to 3Mhz */ - div = 24000000 / 3000000 / 2 - 1; - cd_odly = div >> 1; - if (!cd_odly) - cd_odly = 1; - - writel((cd_odly << 8) | div, &rsb->ccr); -} - -int rsb_init(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - /* Enable RSB and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); - - /* Setup external pins */ - rsb_cfg_io(); - - writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); - rsb_set_clk(); - - return rsb_set_device_mode(); -} - -static int rsb_await_trans(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - unsigned long tmo = timer_get_us() + 1000000; - u32 stat; - int ret; - - while (1) { - stat = readl(&rsb->stat); - if (stat & RSB_STAT_LBSY_INT) { - ret = -EBUSY; - break; - } - if (stat & RSB_STAT_TERR_INT) { - ret = -EIO; - break; - } - if (stat & RSB_STAT_TOVER_INT) { - ret = 0; - break; - } - if (timer_get_us() > tmo) { - ret = -ETIME; - break; - } - } - writel(stat, &rsb->stat); /* Clear status bits */ - - return ret; -} - -static int rsb_set_device_mode(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - unsigned long tmo = timer_get_us() + 1000000; - - writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA, - &rsb->dmcr); - - while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { - if (timer_get_us() > tmo) - return -ETIME; - } - - return rsb_await_trans(); -} - -static int rsb_do_trans(void) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); - return rsb_await_trans(); -} - -int rsb_set_device_address(u16 device_addr, u16 runtime_addr) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | - RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); - writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); - - return rsb_do_trans(); -} - -int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); - writel(reg_addr, &rsb->addr); - writel(data, &rsb->data); - writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); - - return rsb_do_trans(); -} - -int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) -{ - struct sunxi_rsb_reg * const rsb = - (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - int ret; - - writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); - writel(reg_addr, &rsb->addr); - writel(RSB_CMD_BYTE_READ, &rsb->cmd); - - ret = rsb_do_trans(); - if (ret) - return ret; - - *data = readl(&rsb->data) & 0xff; - - return 0; -} diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 0377bb83da..3848cab4b6 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -11,6 +11,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" -CONFIG_SUN8I_RSB=y +CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP_GPIO=y CONFIG_AXP809_POWER=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 8fb6504209..35e575327f 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -11,6 +11,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" -CONFIG_SUN8I_RSB=y +CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP_GPIO=y CONFIG_AXP809_POWER=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 0adf143abf..66bd6fe2f3 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -583,6 +583,14 @@ config SYS_I2C_SUN6I_P2WI in the Allwinner A31 and A31s SOCs. This interface is used to connect to specific devices like the X-Powers AXP221 PMIC. +config SYS_I2C_SUN8I_RSB + bool "Allwinner sun8i Reduced Serial Bus controller" + depends on ARCH_SUNXI + help + Support for Allwinner's Reduced Serial Bus (RSB) controller. This + controller is responsible for communicating with various RSB based + devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs. + config SYS_I2C_SYNQUACER bool "Socionext SynQuacer I2C controller" depends on ARCH_SYNQUACER && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 0a2cc64193..916427452a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o obj-$(CONFIG_SYS_I2C_SUN6I_P2WI) += sun6i_p2wi.o +obj-$(CONFIG_SYS_I2C_SUN8I_RSB) += sun8i_rsb.o obj-$(CONFIG_SYS_I2C_SYNQUACER) += synquacer_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c new file mode 100644 index 0000000000..716b245a00 --- /dev/null +++ b/drivers/i2c/sun8i_rsb.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 Hans de Goede + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * lixiang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base) +{ + unsigned long tmo = timer_get_us() + 1000000; + u32 stat; + int ret; + + while (1) { + stat = readl(&base->stat); + if (stat & RSB_STAT_LBSY_INT) { + ret = -EBUSY; + break; + } + if (stat & RSB_STAT_TERR_INT) { + ret = -EIO; + break; + } + if (stat & RSB_STAT_TOVER_INT) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(stat, &base->stat); /* Clear status bits */ + + return ret; +} + +static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base) +{ + setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS); + + return sun8i_rsb_await_trans(base); +} + +static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr, + u8 reg_addr, u8 *data) +{ + int ret; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr); + writel(reg_addr, &base->addr); + writel(RSB_CMD_BYTE_READ, &base->cmd); + + ret = sun8i_rsb_do_trans(base); + if (ret) + return ret; + + *data = readl(&base->data) & 0xff; + + return 0; +} + +static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr, + u8 reg_addr, u8 data) +{ + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr); + writel(reg_addr, &base->addr); + writel(data, &base->data); + writel(RSB_CMD_BYTE_WRITE, &base->cmd); + + return sun8i_rsb_do_trans(base); +} + +static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base, + u16 device_addr, u16 runtime_addr) +{ + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | + RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr); + writel(RSB_CMD_SET_RTSADDR, &base->cmd); + + return sun8i_rsb_do_trans(base); +} + +static void sun8i_rsb_cfg_io(void) +{ +#ifdef CONFIG_MACH_SUN8I + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); +#elif defined CONFIG_MACH_SUN9I + sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPN(0), 1); + sunxi_gpio_set_pull(SUNXI_GPN(1), 1); + sunxi_gpio_set_drv(SUNXI_GPN(0), 2); + sunxi_gpio_set_drv(SUNXI_GPN(1), 2); +#else +#error unsupported MACH_SUNXI +#endif +} + +static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base) +{ + u32 div = 0; + u32 cd_odly = 0; + + /* Source is Hosc24M, set RSB clk to 3Mhz */ + div = 24000000 / 3000000 / 2 - 1; + cd_odly = div >> 1; + if (!cd_odly) + cd_odly = 1; + + writel((cd_odly << 8) | div, &base->ccr); +} + +static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base) +{ + unsigned long tmo = timer_get_us() + 1000000; + + writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA, + &base->dmcr); + + while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return sun8i_rsb_await_trans(base); +} + +static int sun8i_rsb_init(struct sunxi_rsb_reg *base) +{ + /* Enable RSB and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + + /* Setup external pins */ + sun8i_rsb_cfg_io(); + + writel(RSB_CTRL_SOFT_RST, &base->ctrl); + sun8i_rsb_set_clk(base); + + return sun8i_rsb_set_device_mode(base); +} + +#if IS_ENABLED(CONFIG_AXP_PMIC_BUS) +int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data) +{ + struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + return sun8i_rsb_read(base, runtime_addr, reg_addr, data); +} + +int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data) +{ + struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + return sun8i_rsb_write(base, runtime_addr, reg_addr, data); +} + +int rsb_set_device_address(u16 device_addr, u16 runtime_addr) +{ + struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + return sun8i_rsb_set_device_address(base, device_addr, runtime_addr); +} + +int rsb_init(void) +{ + struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + return sun8i_rsb_init(base); +} +#endif + +#if CONFIG_IS_ENABLED(DM_I2C) +struct sun8i_rsb_priv { + struct sunxi_rsb_reg *base; +}; + +/* + * The mapping from hardware address to runtime address is fixed, and shared + * among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux. + */ +static int sun8i_rsb_get_runtime_address(u16 device_addr) +{ + if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR) + return AXP_PMIC_PRI_RUNTIME_ADDR; + if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR) + return AXP_PMIC_SEC_RUNTIME_ADDR; + + return -ENXIO; +} + +static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr); + struct sun8i_rsb_priv *priv = dev_get_priv(bus); + + if (runtime_addr < 0) + return runtime_addr; + + /* The hardware only supports SMBus-style transfers. */ + if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1) + return sun8i_rsb_read(priv->base, runtime_addr, + msg[0].buf[0], &msg[1].buf[0]); + + if (nmsgs == 1 && msg[0].len == 2) + return sun8i_rsb_write(priv->base, runtime_addr, + msg[0].buf[0], msg[0].buf[1]); + + return -EINVAL; +} + +static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr); + struct sun8i_rsb_priv *priv = dev_get_priv(bus); + + if (runtime_addr < 0) + return runtime_addr; + + return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr); +} + +static int sun8i_rsb_probe(struct udevice *bus) +{ + struct sun8i_rsb_priv *priv = dev_get_priv(bus); + + priv->base = dev_read_addr_ptr(bus); + + return sun8i_rsb_init(priv->base); +} + +static int sun8i_rsb_child_pre_probe(struct udevice *child) +{ + struct dm_i2c_chip *chip = dev_get_parent_plat(child); + + /* Ensure each transfer is for a single register. */ + chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS; + + return 0; +} + +static const struct dm_i2c_ops sun8i_rsb_ops = { + .xfer = sun8i_rsb_xfer, + .probe_chip = sun8i_rsb_probe_chip, +}; + +static const struct udevice_id sun8i_rsb_ids[] = { + { .compatible = "allwinner,sun8i-a23-rsb" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sun8i_rsb) = { + .name = "sun8i_rsb", + .id = UCLASS_I2C, + .of_match = sun8i_rsb_ids, + .probe = sun8i_rsb_probe, + .child_pre_probe = sun8i_rsb_child_pre_probe, + .priv_auto = sizeof(struct sun8i_rsb_priv), + .ops = &sun8i_rsb_ops, +}; +#endif /* CONFIG_IS_ENABLED(DM_I2C) */ diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 0db3e143ed..46a017d2ef 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -30,6 +30,12 @@ #define AXP_PMIC_MODE_REG 0x3e #define AXP_PMIC_MODE_I2C 0x00 #define AXP_PMIC_MODE_P2WI 0x3e +#define AXP_PMIC_MODE_RSB 0x7c + +#define AXP_PMIC_PRI_DEVICE_ADDR 0x3a3 +#define AXP_PMIC_PRI_RUNTIME_ADDR 0x2d +#define AXP_PMIC_SEC_DEVICE_ADDR 0x745 +#define AXP_PMIC_SEC_RUNTIME_ADDR 0x3a int axp_set_dcdc1(unsigned int mvolt); int axp_set_dcdc2(unsigned int mvolt); From d3b02987cb6126650ff5077ccaba1e4e1ba76d6c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:22 -0500 Subject: [PATCH 151/228] sunxi: pmic_bus: Clean up preprocessor conditions Instead of using the SoC symbols to decide the bus type, use whichever bus driver is actually enabled. This allows collapsing all of the AXP2xx and AXP8xx variants into one "else" case. It also has the advantage of falling back to I2C when the other bus drivers are disabled; this works because all of the PMICs support I2C in addition to other interfaces. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/pmic_bus.c | 90 +++++++++++++++------------------- 1 file changed, 39 insertions(+), 51 deletions(-) diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 827797249e..20ded436cd 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -23,75 +23,63 @@ #define AXP221_CHIP_ADDR 0x68 +static int pmic_i2c_address(void) +{ + if (IS_ENABLED(CONFIG_AXP152_POWER)) + return AXP152_I2C_ADDR; + if (IS_ENABLED(CONFIG_AXP305_POWER)) + return AXP305_I2C_ADDR; + + /* Other AXP2xx and AXP8xx variants */ + return AXP209_I2C_ADDR; +} + int pmic_bus_init(void) { /* This cannot be 0 because it is used in SPL before BSS is ready */ static int needs_init = 1; - __maybe_unused int ret; + int ret = 0; if (!needs_init) return 0; -#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - p2wi_init(); - ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP_PMIC_MODE_REG, - AXP_PMIC_MODE_P2WI); -# elif defined CONFIG_MACH_SUN8I_R40 - /* Nothing. R40 uses the AXP221s in I2C mode */ - ret = 0; -# else - ret = rsb_init(); - if (ret) - return ret; + if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) { + p2wi_init(); + ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, + AXP_PMIC_MODE_REG, + AXP_PMIC_MODE_P2WI); + } else if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) { + ret = rsb_init(); + if (ret) + return ret; - ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, - AXP_PMIC_PRI_RUNTIME_ADDR); -# endif - if (ret) - return ret; -#endif + ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, + AXP_PMIC_PRI_RUNTIME_ADDR); + } - needs_init = 0; - return 0; + needs_init = ret; + + return ret; } int pmic_bus_read(u8 reg, u8 *data) { -#ifdef CONFIG_AXP152_POWER - return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP209_POWER - return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP305_POWER - return i2c_read(AXP305_I2C_ADDR, reg, 1, data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - return p2wi_read(reg, data); -# elif defined CONFIG_MACH_SUN8I_R40 - return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); -# else - return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); -# endif -#endif + if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) + return p2wi_read(reg, data); + if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) + return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); + + return i2c_read(pmic_i2c_address(), reg, 1, data, 1); } int pmic_bus_write(u8 reg, u8 data) { -#ifdef CONFIG_AXP152_POWER - return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP209_POWER - return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP305_POWER - return i2c_write(AXP305_I2C_ADDR, reg, 1, &data, 1); -#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER -# ifdef CONFIG_MACH_SUN6I - return p2wi_write(reg, data); -# elif defined CONFIG_MACH_SUN8I_R40 - return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); -# else - return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); -# endif -#endif + if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) + return p2wi_write(reg, data); + if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) + return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); + + return i2c_write(pmic_i2c_address(), reg, 1, &data, 1); } int pmic_bus_setbits(u8 reg, u8 bits) From 8b0eacdf2b0d472d991c3af4a236ad02759fc59e Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:23 -0500 Subject: [PATCH 152/228] sunxi: pmic_bus: Use the DM PMIC interface when possible The pmic_bus functions are used in both SPL (for regulator setup) and U-Boot proper (for regulator setup, SID access, GPIO, and poweroff). Currently, pmic_bus conflicts with DM_I2C because it uses the legacy I2C interface. This commit makes pmic_bus dual-compatible with either the legacy I2C functions or the newly-added PMIC_AXP driver (which uses DM_I2C). In turn, this allows platforms to start transitioning to DM_I2C in U-Boot proper, without breaking boards that still depend on the legacy I2C interface for other reasons. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 2 ++ arch/arm/mach-sunxi/pmic_bus.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 10401d3249..83f8f9513f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -96,6 +96,8 @@ config SUN6I_PRCM config AXP_PMIC_BUS bool + select DM_PMIC if DM_I2C + select PMIC_AXP if DM_I2C help Select this PMIC bus access helpers for Sunxi platform PRCM or other AXP family PMIC devices. diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c index 20ded436cd..c090840637 100644 --- a/arch/arm/mach-sunxi/pmic_bus.c +++ b/arch/arm/mach-sunxi/pmic_bus.c @@ -10,9 +10,11 @@ #include #include +#include #include #include #include +#include #include #define AXP152_I2C_ADDR 0x30 @@ -23,6 +25,9 @@ #define AXP221_CHIP_ADDR 0x68 +#if CONFIG_IS_ENABLED(PMIC_AXP) +static struct udevice *pmic; +#else static int pmic_i2c_address(void) { if (IS_ENABLED(CONFIG_AXP152_POWER)) @@ -33,6 +38,7 @@ static int pmic_i2c_address(void) /* Other AXP2xx and AXP8xx variants */ return AXP209_I2C_ADDR; } +#endif int pmic_bus_init(void) { @@ -43,6 +49,10 @@ int pmic_bus_init(void) if (!needs_init) return 0; +#if CONFIG_IS_ENABLED(PMIC_AXP) + ret = uclass_get_device_by_driver(UCLASS_PMIC, DM_DRIVER_GET(axp_pmic), + &pmic); +#else if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) { p2wi_init(); ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, @@ -56,6 +66,7 @@ int pmic_bus_init(void) ret = rsb_set_device_address(AXP_PMIC_PRI_DEVICE_ADDR, AXP_PMIC_PRI_RUNTIME_ADDR); } +#endif needs_init = ret; @@ -64,22 +75,30 @@ int pmic_bus_init(void) int pmic_bus_read(u8 reg, u8 *data) { +#if CONFIG_IS_ENABLED(PMIC_AXP) + return pmic_read(pmic, reg, data, 1); +#else if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) return p2wi_read(reg, data); if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); return i2c_read(pmic_i2c_address(), reg, 1, data, 1); +#endif } int pmic_bus_write(u8 reg, u8 data) { +#if CONFIG_IS_ENABLED(PMIC_AXP) + return pmic_write(pmic, reg, &data, 1); +#else if (IS_ENABLED(CONFIG_SYS_I2C_SUN6I_P2WI)) return p2wi_write(reg, data); if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB)) return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data); return i2c_write(pmic_i2c_address(), reg, 1, &data, 1); +#endif } int pmic_bus_setbits(u8 reg, u8 bits) From 2421497cb78b7647ff7592acda3d444caa120f01 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:24 -0500 Subject: [PATCH 153/228] sunxi: video: Convert panel I2C to use DM_I2C Two displays supported by the sunxi display driver (each one used by a single board) require initialization over I2C. Both previously used i2c_soft; replace this with the i2c-gpio instance that already exists in those boards' device trees (sun5i-a13-utoo-p66 and sun6i-a31-colombus). Since the i2c-gpio nodes are not referenced by any other node in the device trees (the device trees have no panel node), the I2C bus is selected by its node name. This panel initialization code was the only i2c_soft user, so the i2c_soft GPIO setup code can be removed now as well. Reviewed-by: Heiko Schocher Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 21 ++---- board/sunxi/board.c | 44 +----------- configs/Colombus_defconfig | 6 -- configs/UTOO_P66_defconfig | 3 - drivers/video/anx9804.c | 103 ++++++++++++++-------------- drivers/video/anx9804.h | 5 +- drivers/video/sunxi/sunxi_display.c | 55 ++++++++++----- include/configs/sunxi-common.h | 17 ----- 8 files changed, 100 insertions(+), 154 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 83f8f9513f..c1e762a518 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -909,27 +909,18 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI - select CMD_I2C + select DM_I2C + select DM_I2C_GPIO ---help--- Say y here if the LCD panel needs to be configured via i2c. This will add a bitbang i2c controller using gpios to talk to the LCD. -config VIDEO_LCD_PANEL_I2C_SDA - string "LCD panel i2c interface SDA pin" +config VIDEO_LCD_PANEL_I2C_NAME + string "LCD panel i2c interface node name" depends on VIDEO_LCD_PANEL_I2C - default "PG12" + default "i2c@0" ---help--- - Set the SDA pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_LCD_PANEL_I2C_SCL - string "LCD panel i2c interface SCL pin" - depends on VIDEO_LCD_PANEL_I2C - default "PG10" - ---help--- - Set the SCL pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - + Set the device tree node name for the LCD i2c interface. # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 65cb3a6fe3..4f5747c34a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -47,47 +47,6 @@ #include #include -#if defined(CONFIG_VIDEO_LCD_PANEL_I2C) -/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ -int soft_i2c_gpio_sda; -int soft_i2c_gpio_scl; - -static int soft_i2c_board_init(void) -{ - int ret; - - soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); - if (soft_i2c_gpio_sda < 0) { - printf("Error invalid soft i2c sda pin: '%s', err %d\n", - CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); - return soft_i2c_gpio_sda; - } - ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); - if (ret) { - printf("Error requesting soft i2c sda pin: '%s', err %d\n", - CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); - return ret; - } - - soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); - if (soft_i2c_gpio_scl < 0) { - printf("Error invalid soft i2c scl pin: '%s', err %d\n", - CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); - return soft_i2c_gpio_scl; - } - ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); - if (ret) { - printf("Error requesting soft i2c scl pin: '%s', err %d\n", - CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); - return ret; - } - - return 0; -} -#else -static int soft_i2c_board_init(void) { return 0; } -#endif - DECLARE_GLOBAL_DATA_PTR; void i2c_init_board(void) @@ -312,8 +271,7 @@ int board_init(void) #endif #endif /* CONFIG_DM_MMC */ - /* Uses dm gpio code so do this here and not in i2c_init_board() */ - return soft_i2c_board_init(); + return 0; } /* diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 31541f898d..270bd7d351 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -13,15 +13,9 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH27" CONFIG_VIDEO_LCD_BL_EN="PM1" CONFIG_VIDEO_LCD_BL_PWM="PH13" -CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" -CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SPEED=50000 -CONFIG_SYS_I2C_SOFT_SLAVE=0x00 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index b572807308..b021b0a886 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -21,9 +21,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SPEED=50000 -CONFIG_SYS_I2C_SOFT_SLAVE=0x00 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index 3037ff39b4..52b5988ba5 100644 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c @@ -21,18 +21,23 @@ * This function will init an anx9804 parallel lcd to dp bridge chip * using the passed in parameters. * - * @i2c_bus: Number of the i2c bus to which the anx9804 is connected. + * @i2c_bus: Device of the i2c bus to which the anx9804 is connected. * @lanes: Number of displayport lanes to use * @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G * @bpp: Bits per pixel, must be 18 or 24 */ -void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) +void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp) { - unsigned int orig_i2c_bus = i2c_get_bus_num(); - u8 c, colordepth; - int i; + struct udevice *chip0, *chip1; + int c, colordepth, i, ret; - i2c_set_bus_num(i2c_bus); + ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0); + if (ret) + return; + + ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1); + if (ret) + return; if (bpp == 18) colordepth = 0x00; /* 6 bit */ @@ -40,24 +45,23 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) colordepth = 0x10; /* 8 bit */ /* Reset */ - i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1); + dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1); mdelay(100); - i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0); + dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0); /* Write 0 to the powerdown reg (powerup everything) */ - i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0); + dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0); - c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG); + c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG); if (c != 0x98) { printf("Error anx9804 chipid mismatch\n"); - i2c_set_bus_num(orig_i2c_bus); return; } for (i = 0; i < 100; i++) { - c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG); - i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c); - c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG); + c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG); + dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c); + c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG); if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0) break; @@ -66,51 +70,51 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) if (i == 100) printf("Error anx9804 clock is not stable\n"); - i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth); + dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth); /* Set a bunch of analog related register values */ - i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07); - i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19); - i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9); - i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE); - i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0); - i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99); - i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b); - i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30); - i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06); + dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07); + dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19); + dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9); + dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE); + dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0); + dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99); + dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b); + dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30); + dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06); /* Force HPD */ - i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG, - ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL); + dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG, + ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL); /* Power up and configure lanes */ - i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00); - i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00); - i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00); - i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00); - i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00); + dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00); + dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00); + dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00); + dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00); + dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00); /* Reset AUX CH */ - i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, - ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX); - i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, - ANX9804_RST_CTRL2_AC_MODE); + dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, + ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX); + dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, + ANX9804_RST_CTRL2_AC_MODE); /* Powerdown audio and some other unused bits */ - i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO); - i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00); - i2c_reg_write(0x38, 0xa7, 0x00); + dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO); + dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00); + dm_i2c_reg_write(chip0, 0xa7, 0x00); /* Set data-rate / lanes */ - i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate); - i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes); + dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate); + dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes); /* Link training */ - i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG, - ANX9804_LINK_TRAINING_CTRL_EN); + dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG, + ANX9804_LINK_TRAINING_CTRL_EN); mdelay(5); for (i = 0; i < 100; i++) { - c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG); + c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG); if ((c & 0x01) == 0) break; @@ -118,17 +122,14 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) } if(i == 100) { printf("Error anx9804 link training timeout\n"); - i2c_set_bus_num(orig_i2c_bus); return; } /* Enable */ - i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG, - ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); + dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG, + ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); /* Force stream valid */ - i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG, - ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL | - ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL); - - i2c_set_bus_num(orig_i2c_bus); + dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG, + ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL | + ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL); } diff --git a/drivers/video/anx9804.h b/drivers/video/anx9804.h index c0fe3b393b..ea6c9f2d55 100644 --- a/drivers/video/anx9804.h +++ b/drivers/video/anx9804.h @@ -16,9 +16,10 @@ #define ANX9804_DATA_RATE_2700M 0x0a #ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 -void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp); +void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp); #else -static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, +static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp) {} #endif + #endif diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index da3e898829..5a21f7af66 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -901,6 +901,42 @@ static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode) } #endif /* CONFIG_VIDEO_LCD_SSD2828 */ +#ifdef CONFIG_VIDEO_LCD_PANEL_I2C +static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) +{ + const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME; + struct udevice *i2c_bus; + int ret; + + ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus); + if (ret) + return; + + if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) { + /* + * The anx9804 needs 1.8V from eldo3, we do this here + * and not via CONFIG_AXP_ELDO3_VOLT from board_init() + * to avoid turning this on when using hdmi output. + */ + axp_set_eldo(3, 1800); + anx9804_init(i2c_bus, 4, + ANX9804_DATA_RATE_1620M, + sunxi_display->depth); + } + if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) { + struct udevice *chip; + + ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip); + if (ret) + return; + + dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */ + } +} +#else +static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {} +#endif + static void sunxi_engines_init(void) { sunxi_composer_init(); @@ -935,27 +971,12 @@ static void sunxi_mode_set(struct sunxi_display_priv *sunxi_display, break; case sunxi_monitor_lcd: sunxi_lcdc_panel_enable(); - if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) { - /* - * The anx9804 needs 1.8V from eldo3, we do this here - * and not via CONFIG_AXP_ELDO3_VOLT from board_init() - * to avoid turning this on when using hdmi output. - */ - axp_set_eldo(3, 1800); - anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4, - ANX9804_DATA_RATE_1620M, - sunxi_display->depth); - } if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) { mdelay(50); /* Wait for lcd controller power on */ hitachi_tx18d42vm_init(); } - if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) { - unsigned int orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS); - i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */ - i2c_set_bus_num(orig_i2c_bus); - } + if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C)) + sunxi_panel_i2c_init(sunxi_display); sunxi_composer_mode_set(mode, address, monitor); sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false); sunxi_composer_enable(); diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d8b6052e4..c576d65efa 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -160,23 +160,6 @@ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ #endif - -/* I2C */ -#if defined(CONFIG_VIDEO_LCD_PANEL_I2C) -/* We use pin names in Kconfig and sunxi_name_to_gpio() */ -#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda -#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl -#ifndef __ASSEMBLY__ -extern int soft_i2c_gpio_sda; -extern int soft_i2c_gpio_scl; -#endif -#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ -#else -#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ -#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ -#endif - /* Ethernet support */ #ifdef CONFIG_USB_EHCI_HCD From f9437b00c06382d3edc623c10c69901786ad6317 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Fri, 8 Oct 2021 00:17:25 -0500 Subject: [PATCH 154/228] sunxi: Enable DM_I2C for all sunxi boards Now that the last users of legacy I2C (outside of SPL) have been resolved, we can enable DM_I2C at the sunxi architecture level. Reviewed-by: Heiko Schocher Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ebb1927270..d8c041a877 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1028,6 +1028,7 @@ config ARCH_SUNXI select DM select DM_ETH select DM_GPIO + select DM_I2C if I2C select DM_KEYBOARD select DM_MMC if MMC select DM_SCSI if SCSI diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index c1e762a518..2c18cf02d1 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -165,7 +165,6 @@ endif config MACH_SUNXI_H3_H5 bool - select DM_I2C select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_DRAM_DW @@ -326,7 +325,6 @@ config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 select SPI - select DM_I2C select DM_SPI if SPI select DM_SPI_FLASH select PHY_SUN4I_USB @@ -909,7 +907,6 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI - select DM_I2C select DM_I2C_GPIO ---help--- Say y here if the LCD panel needs to be configured via i2c. This From 9b075973e9aeeab28d30398320ce722e765cdb3c Mon Sep 17 00:00:00 2001 From: Dan Sneddon Date: Mon, 20 Sep 2021 16:28:44 -0700 Subject: [PATCH 155/228] pwm: Add PWM driver for SAMA5D2 Add support for the PWM found on the SAMA5D2 family of devices. Signed-off-by: Dan Sneddon --- drivers/pwm/Kconfig | 6 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-at91.c | 207 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 drivers/pwm/pwm-at91.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6840..669d3fa4fc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,6 +9,12 @@ config DM_PWM frequency/period can be controlled along with the proportion of that time that the signal is high. +config PWM_AT91 + bool "Enable support for PWM found on AT91 SoC's" + depends on DM_PWM && ARCH_AT91 + help + Support for PWM hardware on AT91 based SoC. + config PWM_CROS_EC bool "Enable support for the Chrome OS EC PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244bfb7..55f2bc081d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_AT91) += pwm-at91.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c new file mode 100644 index 0000000000..95597aee55 --- /dev/null +++ b/drivers/pwm/pwm-at91.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PWM support for Microchip AT91 architectures. + * + * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries + * + * Author: Dan Sneddon + * + * Based on drivers/pwm/pwm-atmel.c from Linux. + */ +#include +#include +#include +#include +#include +#include +#include + +#define PERIOD_BITS 16 +#define PWM_MAX_PRES 10 +#define NSEC_PER_SEC 1000000000L + +#define PWM_ENA 0x04 +#define PWM_CHANNEL_OFFSET 0x20 +#define PWM_CMR 0x200 +#define PWM_CMR_CPRE_MSK GENMASK(3, 0) +#define PWM_CMR_CPOL BIT(9) +#define PWM_CDTY 0x204 +#define PWM_CPRD 0x20C + +struct at91_pwm_priv { + void __iomem *base; + struct clk pclk; + u32 clkrate; +}; + +static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev, + unsigned long clkrate, + uint period_ns, uint duty_ns, + unsigned long *cprd, u32 *pres) +{ + u64 cycles = period_ns; + int shift; + + /* Calculate the period cycles and prescale value */ + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + + /* + * The register for the period length is period_bits bits wide. + * So for each bit the number of clock cycles is wider divide the input + * clock frequency by two using pres and shift cprd accordingly. + */ + shift = fls(cycles) - PERIOD_BITS; + + if (shift > PWM_MAX_PRES) { + return -EINVAL; + } else if (shift > 0) { + *pres = shift; + cycles >>= *pres; + } else { + *pres = 0; + } + + *cprd = cycles; + + return 0; +} + +static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns, + unsigned long clkrate, unsigned long cprd, + u32 pres, unsigned long *cdty) +{ + u64 cycles = duty_ns; + + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + cycles >>= pres; + *cdty = cprd - cycles; +} + +/** + * Returns: channel status after set operation + */ +static bool at91_pwm_set(void __iomem *base, uint channel, bool enable) +{ + u32 val, cur_status; + + val = ioread32(base + PWM_ENA); + cur_status = !!(val & BIT(channel)); + + /* if channel is already in that state, do nothing */ + if (!(enable ^ cur_status)) + return cur_status; + + if (enable) + val |= BIT(channel); + else + val &= ~(BIT(channel)); + + iowrite32(val, base + PWM_ENA); + + return cur_status; +} + +static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + + at91_pwm_set(priv->base, channel, enable); + + return 0; +} + +static int at91_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + unsigned long cprd, cdty; + u32 pres, val; + int channel_enabled; + int ret; + + ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns, + duty_ns, &cprd, &pres); + if (ret) + return ret; + + at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty); + + /* disable the channel */ + channel_enabled = at91_pwm_set(priv->base, channel, false); + + /* It is necessary to preserve CPOL, inside CMR */ + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD); + + iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY); + + /* renable the channel if needed */ + if (channel_enabled) + at91_pwm_set(priv->base, channel, true); + + return 0; +} + +static int at91_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + u32 val; + + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + if (polarity) + val |= PWM_CMR_CPOL; + else + val &= ~PWM_CMR_CPOL; + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + return 0; +} + +static int at91_pwm_probe(struct udevice *dev) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->pclk); + if (ret) + return ret; + + /* clocks aren't ref-counted so just enabled them once here */ + ret = clk_enable(&priv->pclk); + if (ret) + return ret; + + priv->clkrate = clk_get_rate(&priv->pclk); + + return ret; +} + +static const struct pwm_ops at91_pwm_ops = { + .set_config = at91_pwm_set_config, + .set_enable = at91_pwm_set_enable, + .set_invert = at91_pwm_set_invert, +}; + +static const struct udevice_id at91_pwm_of_match[] = { + { .compatible = "atmel,sama5d2-pwm" }, + { } +}; + +U_BOOT_DRIVER(at91_pwm) = { + .name = "at91_pwm", + .id = UCLASS_PWM, + .of_match = at91_pwm_of_match, + .probe = at91_pwm_probe, + .priv_auto = sizeof(struct at91_pwm_priv), + .ops = &at91_pwm_ops, +}; From 2d2273fa1effea235669a36efbd7beddb8017f67 Mon Sep 17 00:00:00 2001 From: Dan Sneddon Date: Mon, 20 Sep 2021 16:28:45 -0700 Subject: [PATCH 156/228] dt-bindings: pwm: pwm-at91: Add PWM bindings for A5D2 Document the bindings needed for the PWM device on the SAMA5D2. Signed-off-by: Dan Sneddon --- doc/device-tree-bindings/pwm/pwm-at91.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 doc/device-tree-bindings/pwm/pwm-at91.txt diff --git a/doc/device-tree-bindings/pwm/pwm-at91.txt b/doc/device-tree-bindings/pwm/pwm-at91.txt new file mode 100644 index 0000000000..a03da404f5 --- /dev/null +++ b/doc/device-tree-bindings/pwm/pwm-at91.txt @@ -0,0 +1,16 @@ +Microchip AT91 PWM controller for SAMA5D2 + +Required properties: + - compatible: Should be "atmel,sama5d2-pwm" + - reg: Physical base address and length of the controller's registers. + - clocks: Should contain a clock identifier for the PWM's parent clock. + - #pwm-cells: Should be 3. + +Example: + +pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; +}; From 1f83bda7886c0e3fbb9aaf1d36dcaac27a7c92ea Mon Sep 17 00:00:00 2001 From: Dan Sneddon Date: Mon, 20 Sep 2021 16:28:46 -0700 Subject: [PATCH 157/228] ARM: dts: sama5d2: Add pwm0 definition Add node for the PWM0 on the SAMA5D2 SoC. Signed-off-by: Dan Sneddon --- arch/arm/dts/sama5d2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d8a125b073..038cd73c03 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -671,6 +671,14 @@ status = "disabled"; }; + pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; + status = "disabled"; + }; + rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; From 38f7d3b6530edae4c4d506d6b9dbd0ae8b8ee5e6 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 10 Sep 2021 16:16:20 +0200 Subject: [PATCH 158/228] cmd: bind: Fix driver binding on a device Fix a regression brings by commit 84f8e36f03fa ("cmd: bind: allow to bind driver with driver data") As example, the following bind command doesn't work: bind /soc/usb-otg@49000000 usb_ether As usb_ether driver has no compatible string, it can't be find by lists_bind_fdt(). In bind_by_node_path(), which called lists_bind_fdt(), the driver entry is known, pass it to lists_bind_fdt() to force the driver entry selection. For this, add a new parameter struct *driver to lists_bind_fdt(). Fix also all lists_bind_fdt() callers. Fixes: 84f8e36f03fa ("cmd: bind: allow to bind driver with driver data") Signed-off-by: Patrice Chotard Reported-by: Herbert Poetzl Cc: Marek Vasut Cc: Herbert Poetzl Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass --- board/congatec/cgtqmx8/spl.c | 2 +- cmd/bind.c | 2 +- drivers/core/device.c | 2 +- drivers/core/lists.c | 4 +++- drivers/core/root.c | 2 +- drivers/misc/imx8/scu.c | 2 +- drivers/serial/serial-uclass.c | 2 +- drivers/timer/timer-uclass.c | 2 +- include/dm/lists.h | 3 ++- test/dm/nop.c | 2 +- 10 files changed, 13 insertions(+), 10 deletions(-) diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c index 2a5d4c1bcd..37b7221c52 100644 --- a/board/congatec/cgtqmx8/spl.c +++ b/board/congatec/cgtqmx8/spl.c @@ -32,7 +32,7 @@ void spl_board_init(void) offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); while (offset != -FDT_ERR_NOTFOUND) { lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), - NULL, true); + NULL, NULL, true); offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, "nxp,imx8-pd"); } diff --git a/cmd/bind.c b/cmd/bind.c index 07c629eff7..4d1b7885e6 100644 --- a/cmd/bind.c +++ b/cmd/bind.c @@ -152,7 +152,7 @@ static int bind_by_node_path(const char *path, const char *drv_name) } ofnode = ofnode_path(path); - ret = lists_bind_fdt(parent, ofnode, &dev, false); + ret = lists_bind_fdt(parent, ofnode, &dev, drv, false); if (!dev || ret) { printf("Unable to bind. err:%d\n", ret); diff --git a/drivers/core/device.c b/drivers/core/device.c index 29668f6fb3..6f84762ebd 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -1135,7 +1135,7 @@ int dev_enable_by_path(const char *path) if (ret) return ret; - return lists_bind_fdt(parent, node, NULL, false); + return lists_bind_fdt(parent, node, NULL, NULL, false); } #endif diff --git a/drivers/core/lists.c b/drivers/core/lists.c index e214306b90..c9cd74a484 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -182,7 +182,7 @@ static int driver_check_compatible(const struct udevice_id *of_match, } int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, - bool pre_reloc_only) + struct driver *drv, bool pre_reloc_only) { struct driver *driver = ll_entry_start(struct driver, driver); const int n_ents = ll_entry_count(struct driver, driver); @@ -225,6 +225,8 @@ int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, for (entry = driver; entry != driver + n_ents; entry++) { ret = driver_check_compatible(entry->of_match, &id, compat); + if ((drv) && (drv == entry)) + break; if (!ret) break; } diff --git a/drivers/core/root.c b/drivers/core/root.c index 78eee082c9..86f9776733 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -276,7 +276,7 @@ static int dm_scan_fdt_node(struct udevice *parent, ofnode parent_node, pr_debug(" - ignoring disabled device\n"); continue; } - err = lists_bind_fdt(parent, node, NULL, pre_reloc_only); + err = lists_bind_fdt(parent, node, NULL, NULL, pre_reloc_only); if (err && !ret) { ret = err; debug("%s: ret=%d\n", node_name, ret); diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 035a600f71..4ab5cb4bf1 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -219,7 +219,7 @@ static int imx8_scu_bind(struct udevice *dev) debug("%s(dev=%p)\n", __func__, dev); ofnode_for_each_subnode(node, dev_ofnode(dev)) { - ret = lists_bind_fdt(dev, node, &child, true); + ret = lists_bind_fdt(dev, node, &child, NULL, true); if (ret) return ret; debug("bind child dev %s\n", child->name); diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 8171b17faf..01387c1119 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -69,7 +69,7 @@ static int serial_check_stdout(const void *blob, struct udevice **devp) * anyway. */ if (node > 0 && !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node), - devp, false)) { + devp, NULL, false)) { if (!device_probe(*devp)) return 0; } diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index c8e8419b22..ebea168789 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -146,7 +146,7 @@ int notrace dm_timer_init(void) * If the timer is not marked to be bound before * relocation, bind it anyway. */ - if (!lists_bind_fdt(dm_root(), node, &dev, false)) { + if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) { ret = device_probe(dev); if (ret) return ret; diff --git a/include/dm/lists.h b/include/dm/lists.h index 1a86552546..5896ae3658 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -53,13 +53,14 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); * @parent: parent device (root) * @node: device tree node to bind * @devp: if non-NULL, returns a pointer to the bound device + * @drv: if non-NULL, force this driver to be bound * @pre_reloc_only: If true, bind only nodes with special devicetree properties, * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers. * @return 0 if device was bound, -EINVAL if the device tree is invalid, * other -ve value on error */ int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp, - bool pre_reloc_only); + struct driver *drv, bool pre_reloc_only); /** * device_bind_driver() - bind a device to a driver diff --git a/test/dm/nop.c b/test/dm/nop.c index 2cd92c5240..75b9e7b6cc 100644 --- a/test/dm/nop.c +++ b/test/dm/nop.c @@ -25,7 +25,7 @@ static int noptest_bind(struct udevice *parent) const char *bind_flag = ofnode_read_string(ofnode, "bind"); if (bind_flag && (strcmp(bind_flag, "True") == 0)) - lists_bind_fdt(parent, ofnode, &dev, false); + lists_bind_fdt(parent, ofnode, &dev, NULL, false); ofnode = dev_read_next_subnode(ofnode); } From 9d591106dc22bae57a614a7b42ab9d52c6b921f8 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 10 Sep 2021 16:16:21 +0200 Subject: [PATCH 159/228] usb: gadget: Add bcdDevice for the DWC2 USB Gadget Controller Add an entry in usb_gadget_controller_number() for the DWC2 gadget controller. It is used to bind the USB Ethernet driver. Signed-off-by: Patrice Chotard Reported-by: Herbert Poetzl Cc: Marek Vasut Cc: Herbert Poetzl --- drivers/usb/gadget/gadget_chips.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 0cdf47c2dd..06e6a48949 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -167,6 +167,12 @@ #define gadget_is_mtu3(g) 0 #endif +#ifdef CONFIG_USB_GADGET_DWC2_OTG +#define gadget_is_dwc2(g) (!strcmp("dwc2-udc", (g)->name)) +#else +#define gadget_is_dwc2(g) 0 +#endif + /** * usb_gadget_controller_number - support bcdDevice id convention * @gadget: the controller being driven @@ -232,5 +238,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x25; else if (gadget_is_mtu3(gadget)) return 0x26; + else if (gadget_is_dwc2(gadget)) + return 0x27; return -ENOENT; } From 4c3dc6f69afa47923451fb6baf6c2a60947e45f8 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 10 Sep 2021 16:16:22 +0200 Subject: [PATCH 160/228] usb: sandbox: Add gadget callbacks Add usb_gadget_handle_interrupts(), usb_gadget_register_driver() and usb_gadget_unregister_driver() to be able to test binding usb gadget. Signed-off-by: Patrice Chotard Cc: Marek Vasut Cc: Herbert Poetzl Reviewed-by: Simon Glass --- drivers/usb/host/usb-sandbox.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/usb/host/usb-sandbox.c b/drivers/usb/host/usb-sandbox.c index d7cc92aa54..d1103dcb2e 100644 --- a/drivers/usb/host/usb-sandbox.c +++ b/drivers/usb/host/usb-sandbox.c @@ -9,6 +9,13 @@ #include #include #include +#include + +struct sandbox_udc { + struct usb_gadget gadget; +}; + +struct sandbox_udc *this_controller; struct sandbox_usb_ctrl { int rootdev; @@ -117,6 +124,27 @@ static int sandbox_submit_int(struct udevice *bus, struct usb_device *udev, return ret; } +int usb_gadget_handle_interrupts(int index) +{ + return 0; +} + +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + struct sandbox_udc *dev = this_controller; + + return driver->bind(&dev->gadget); +} + +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + struct sandbox_udc *dev = this_controller; + + driver->unbind(&dev->gadget); + + return 0; +} + static int sandbox_alloc_device(struct udevice *dev, struct usb_device *udev) { struct sandbox_usb_ctrl *ctrl = dev_get_priv(dev); From 299f12508b16c5751a173bf0f32154aeb7b71cce Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 10 Sep 2021 16:16:23 +0200 Subject: [PATCH 161/228] configs: sandbox: add USB_ETHER and GADGET_DOWNLOAD gadget support This is needed for new gadget binding test. Signed-off-by: Patrice Chotard Cc: Marek Vasut Cc: Herbert Poetzl Reviewed-by: Simon Glass --- configs/sandbox_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index ea08a9e5bd..4bd01118d0 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -266,6 +266,10 @@ CONFIG_SANDBOX_TIMER=y CONFIG_USB=y CONFIG_USB_EMUL=y CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_COPY=y CONFIG_CONSOLE_ROTATION=y From 39bd2c8e1aa9143c22f1fd20d054fc895a0880d2 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 10 Sep 2021 16:16:24 +0200 Subject: [PATCH 162/228] test/py: Add usb gadget binding test Add a specific usb gadget binding test which check that binding a driver without compatible string is working as expected. the command "bind /usb@1 usb_ether" should give the following "dm tree" command output: [...] usb 0 [ ] usb_sandbox |-- usb@1 usb_hub 0 [ ] usb_hub | |-- hub usb_emul 0 [ ] usb_sandbox_hub | | `-- hub-emul usb_emul 1 [ ] usb_sandbox_flash | | |-- flash-stick@0 usb_emul 2 [ ] usb_sandbox_flash | | |-- flash-stick@1 usb_emul 3 [ ] usb_sandbox_flash | | |-- flash-stick@2 usb_emul 4 [ ] usb_sandbox_keyb | | `-- keyb@3 eth 4 [ ] usb_ether | `-- usb@1 [...] Signed-off-by: Patrice Chotard Cc: Marek Vasut Cc: Herbert Poetzl Reviewed-by: Simon Glass --- test/py/tests/test_bind.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py index 6703325c0b..9f234fb635 100644 --- a/test/py/tests/test_bind.py +++ b/test/py/tests/test_bind.py @@ -33,6 +33,13 @@ def test_bind_unbind_with_node(u_boot_console): assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False) assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True) + #bind usb_ether driver (which has no compatible) to usb@1 node. + ##New entry usb_ether should appear in the dm tree + response = u_boot_console.run_command('bind /usb@1 usb_ether') + assert response == '' + tree = u_boot_console.run_command('dm tree') + assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True) + #Unbind child #1. No error expected and all devices should be there except for bind-test-child1 response = u_boot_console.run_command('unbind /bind-test/bind-test-child1') assert response == '' From 5f9338ad56e6b1168905e73ecfcd5e1b7b1a32e2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 30 Jul 2021 14:23:54 +0200 Subject: [PATCH 163/228] fastboot: fix partition name truncation in environment lookup strlcat() need to be passed the full buffer length. The incorrect call caused truncation of partition names for fastboot_raw_partition_... and fastboot_partition_alias_... env lookup to much less than PART_NAME_LEN. Fixes: 69a752983171 ("fastboot: Fix possible buffer overrun") Signed-off-by: Matthias Schiffer Reviewed-by: Sean Anderson --- drivers/fastboot/fb_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index cbb3f7b1de..2738dc836e 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -40,7 +40,7 @@ static int raw_part_get_info_by_name(struct blk_desc *dev_desc, /* check for raw partition descriptor */ strcpy(env_desc_name, "fastboot_raw_partition_"); - strlcat(env_desc_name, name, PART_NAME_LEN); + strlcat(env_desc_name, name, sizeof(env_desc_name)); raw_part_desc = strdup(env_get(env_desc_name)); if (raw_part_desc == NULL) return -ENODEV; @@ -114,7 +114,7 @@ static int part_get_info_by_name_or_alias(struct blk_desc **dev_desc, /* check for alias */ strcpy(env_alias_name, "fastboot_partition_alias_"); - strlcat(env_alias_name, name, PART_NAME_LEN); + strlcat(env_alias_name, name, sizeof(env_alias_name)); aliased_part_name = env_get(env_alias_name); if (aliased_part_name != NULL) ret = do_get_part_info(dev_desc, aliased_part_name, From 0892a7e5fa5ce38f58e0e6636ae56c6f60c080e0 Mon Sep 17 00:00:00 2001 From: Zhengxun Li Date: Tue, 14 Sep 2021 13:43:51 +0800 Subject: [PATCH 164/228] mtd: rawnand: Add Macronix raw NAND controller driver Add a driver for Macronix raw NAND controller. This patch referred from linux mxic_nand.c. The difference from the linux version is described here. 1. In order to adapt to the uboot nand framework, add function binding (cmdfunc, read_byte, read_buf, write_buf). 2. Added parsing command format to use hardware correctly. 3. Remove the incompatible functions of Uboot. Signed-off-by: Zhengxun Li --- drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/mxic_nand.c | 603 +++++++++++++++++++++++++++++++ 3 files changed, 610 insertions(+) create mode 100644 drivers/mtd/nand/raw/mxic_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 790ee34403..332f9d7591 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -398,6 +398,12 @@ config NAND_MXS_USE_MINIMUM_ECC endif +config NAND_MXIC + bool "Macronix raw NAND controller" + select SYS_NAND_SELF_INIT + help + This selects the Macronix raw NAND controller driver. + config NAND_ZYNQ bool "Support for Zynq Nand controller" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a5ed2c536f..6ec3581d20 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o +obj-$(CONFIG_NAND_MXIC) += mxic_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o diff --git a/drivers/mtd/nand/raw/mxic_nand.c b/drivers/mtd/nand/raw/mxic_nand.c new file mode 100644 index 0000000000..e54df4615e --- /dev/null +++ b/drivers/mtd/nand/raw/mxic_nand.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Macronix International Co., Ltd. + * + * Author: + * Zhengxun Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HC_CFG 0x0 +#define HC_CFG_IF_CFG(x) ((x) << 27) +#define HC_CFG_DUAL_SLAVE BIT(31) +#define HC_CFG_INDIVIDUAL BIT(30) +#define HC_CFG_NIO(x) (((x) / 4) << 27) +#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2))) +#define HC_CFG_TYPE_SPI_NOR 0 +#define HC_CFG_TYPE_SPI_NAND 1 +#define HC_CFG_TYPE_SPI_RAM 2 +#define HC_CFG_TYPE_RAW_NAND 3 +#define HC_CFG_SLV_ACT(x) ((x) << 21) +#define HC_CFG_CLK_PH_EN BIT(20) +#define HC_CFG_CLK_POL_INV BIT(19) +#define HC_CFG_BIG_ENDIAN BIT(18) +#define HC_CFG_DATA_PASS BIT(17) +#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16) +#define HC_CFG_MAN_START_EN BIT(3) +#define HC_CFG_MAN_START BIT(2) +#define HC_CFG_MAN_CS_EN BIT(1) +#define HC_CFG_MAN_CS_ASSERT BIT(0) + +#define INT_STS 0x4 +#define INT_STS_EN 0x8 +#define INT_SIG_EN 0xc +#define INT_STS_ALL GENMASK(31, 0) +#define INT_RDY_PIN BIT(26) +#define INT_RDY_SR BIT(25) +#define INT_LNR_SUSP BIT(24) +#define INT_ECC_ERR BIT(17) +#define INT_CRC_ERR BIT(16) +#define INT_LWR_DIS BIT(12) +#define INT_LRD_DIS BIT(11) +#define INT_SDMA_INT BIT(10) +#define INT_DMA_FINISH BIT(9) +#define INT_RX_NOT_FULL BIT(3) +#define INT_RX_NOT_EMPTY BIT(2) +#define INT_TX_NOT_FULL BIT(1) +#define INT_TX_EMPTY BIT(0) + +#define HC_EN 0x10 +#define HC_EN_BIT BIT(0) + +#define TXD(x) (0x14 + ((x) * 4)) +#define RXD 0x24 + +#define SS_CTRL(s) (0x30 + ((s) * 4)) +#define LRD_CFG 0x44 +#define LWR_CFG 0x80 +#define RWW_CFG 0x70 +#define OP_READ BIT(23) +#define OP_DUMMY_CYC(x) ((x) << 17) +#define OP_ADDR_BYTES(x) ((x) << 14) +#define OP_CMD_BYTES(x) (((x) - 1) << 13) +#define OP_OCTA_CRC_EN BIT(12) +#define OP_DQS_EN BIT(11) +#define OP_ENHC_EN BIT(10) +#define OP_PREAMBLE_EN BIT(9) +#define OP_DATA_DDR BIT(8) +#define OP_DATA_BUSW(x) ((x) << 6) +#define OP_ADDR_DDR BIT(5) +#define OP_ADDR_BUSW(x) ((x) << 3) +#define OP_CMD_DDR BIT(2) +#define OP_CMD_BUSW(x) (x) +#define OP_BUSW_1 0 +#define OP_BUSW_2 1 +#define OP_BUSW_4 2 +#define OP_BUSW_8 3 + +#define OCTA_CRC 0x38 +#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) +#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16))) +#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) + +#define ONFI_DIN_CNT(s) (0x3c + (s)) + +#define LRD_CTRL 0x48 +#define RWW_CTRL 0x74 +#define LWR_CTRL 0x84 +#define LMODE_EN BIT(31) +#define LMODE_SLV_ACT(x) ((x) << 21) +#define LMODE_CMD1(x) ((x) << 8) +#define LMODE_CMD0(x) (x) + +#define LRD_ADDR 0x4c +#define LWR_ADDR 0x88 +#define LRD_RANGE 0x50 +#define LWR_RANGE 0x8c + +#define AXI_SLV_ADDR 0x54 + +#define DMAC_RD_CFG 0x58 +#define DMAC_WR_CFG 0x94 +#define DMAC_CFG_PERIPH_EN BIT(31) +#define DMAC_CFG_ALLFLUSH_EN BIT(30) +#define DMAC_CFG_LASTFLUSH_EN BIT(29) +#define DMAC_CFG_QE(x) (((x) + 1) << 16) +#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12) +#define DMAC_CFG_BURST_SZ(x) ((x) << 8) +#define DMAC_CFG_DIR_READ BIT(1) +#define DMAC_CFG_START BIT(0) + +#define DMAC_RD_CNT 0x5c +#define DMAC_WR_CNT 0x98 + +#define SDMA_ADDR 0x60 + +#define DMAM_CFG 0x64 +#define DMAM_CFG_START BIT(31) +#define DMAM_CFG_CONT BIT(30) +#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2) +#define DMAM_CFG_DIR_READ BIT(1) +#define DMAM_CFG_EN BIT(0) + +#define DMAM_CNT 0x68 + +#define LNR_TIMER_TH 0x6c + +#define RDM_CFG0 0x78 +#define RDM_CFG0_POLY(x) (x) + +#define RDM_CFG1 0x7c +#define RDM_CFG1_RDM_EN BIT(31) +#define RDM_CFG1_SEED(x) (x) + +#define LWR_SUSP_CTRL 0x90 +#define LWR_SUSP_CTRL_EN BIT(31) + +#define DMAS_CTRL 0x9c +#define DMAS_CTRL_EN BIT(31) +#define DMAS_CTRL_DIR_READ BIT(30) + +#define DATA_STROB 0xa0 +#define DATA_STROB_EDO_EN BIT(2) +#define DATA_STROB_INV_POL BIT(1) +#define DATA_STROB_DELAY_2CYC BIT(0) + +#define IDLY_CODE(x) (0xa4 + ((x) * 4)) +#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8)) + +#define GPIO 0xc4 +#define GPIO_PT(x) BIT(3 + ((x) * 16)) +#define GPIO_RESET(x) BIT(2 + ((x) * 16)) +#define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) +#define GPIO_WPB(x) BIT((x) * 16) + +#define HC_VER 0xd0 + +#define HW_TEST(x) (0xe0 + ((x) * 4)) + +#define MXIC_NFC_MAX_CLK_HZ 50000000 +#define IRQ_TIMEOUT 1000 + +struct mxic_nand_ctrl { + struct clk *send_clk; + struct clk *send_dly_clk; + void __iomem *regs; + struct nand_chip nand_chip; +}; + +/* + * struct mxic_nfc_command_format - Defines NAND flash command format + * @start_cmd: First cycle command (Start command) + * @end_cmd: Second cycle command (Last command) + * @addr_len: Number of address cycles required to send the address + * @read: Direction of command + */ + +struct mxic_nfc_command_format { + int start_cmd; + int end_cmd; + u8 addr_len; + bool read; +}; + +/* The NAND flash operations command format */ +static const struct mxic_nfc_command_format mxic_nand_commands[] = { + {NAND_CMD_READ0, NAND_CMD_READSTART, 5, 1 }, + {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, 1 }, + {NAND_CMD_READID, NAND_CMD_NONE, 1, 1 }, + {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 1 }, + {NAND_CMD_SEQIN, NAND_CMD_NONE, 5, 0 }, + {NAND_CMD_PAGEPROG, NAND_CMD_NONE, 0, 0 }, + {NAND_CMD_CACHEDPROG, NAND_CMD_NONE, 0, 0 }, + {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0 }, + {NAND_CMD_ERASE1, NAND_CMD_NONE, 3, 0 }, + {NAND_CMD_ERASE2, NAND_CMD_NONE, 0, 0 }, + {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0 }, + {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 1 }, + {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 1 }, + {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0 }, + {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0 }, +}; + +static int mxic_nfc_clk_enable(struct mxic_nand_ctrl *nfc) +{ + int ret; + + ret = clk_prepare_enable(nfc->send_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(nfc->send_dly_clk); + if (ret) + goto err_send_dly_clk; + + return ret; + +err_send_dly_clk: + clk_disable_unprepare(nfc->send_clk); + + return ret; +} + +static void mxic_nfc_clk_disable(struct mxic_nand_ctrl *nfc) +{ + clk_disable_unprepare(nfc->send_clk); + clk_disable_unprepare(nfc->send_dly_clk); +} + +static void mxic_nfc_set_input_delay(struct mxic_nand_ctrl *nfc, u8 idly_code) +{ + writel(IDLY_CODE_VAL(0, idly_code) | + IDLY_CODE_VAL(1, idly_code) | + IDLY_CODE_VAL(2, idly_code) | + IDLY_CODE_VAL(3, idly_code), + nfc->regs + IDLY_CODE(0)); + writel(IDLY_CODE_VAL(4, idly_code) | + IDLY_CODE_VAL(5, idly_code) | + IDLY_CODE_VAL(6, idly_code) | + IDLY_CODE_VAL(7, idly_code), + nfc->regs + IDLY_CODE(1)); +} + +static int mxic_nfc_clk_setup(struct mxic_nand_ctrl *nfc, unsigned long freq) +{ + int ret; + + ret = clk_set_rate(nfc->send_clk, freq); + if (ret) + return ret; + + ret = clk_set_rate(nfc->send_dly_clk, freq); + if (ret) + return ret; + + /* + * A constant delay range from 0x0 ~ 0x1F for input delay, + * the unit is 78 ps, the max input delay is 2.418 ns. + */ + mxic_nfc_set_input_delay(nfc, 0xf); + + return 0; +} + +static int mxic_nfc_set_freq(struct mxic_nand_ctrl *nfc, unsigned long freq) +{ + int ret; + + if (freq > MXIC_NFC_MAX_CLK_HZ) + freq = MXIC_NFC_MAX_CLK_HZ; + + mxic_nfc_clk_disable(nfc); + ret = mxic_nfc_clk_setup(nfc, freq); + if (ret) + return ret; + + ret = mxic_nfc_clk_enable(nfc); + if (ret) + return ret; + + return 0; +} + +static void mxic_nfc_hw_init(struct mxic_nand_ctrl *nfc) +{ + writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) | + HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | + HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG); + writel(INT_STS_ALL, nfc->regs + INT_STS_EN); + writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN); + writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); + writel(0, nfc->regs + LRD_CFG); + writel(0, nfc->regs + LRD_CTRL); + writel(0x0, nfc->regs + HC_EN); +} + +static void mxic_nfc_cs_enable(struct mxic_nand_ctrl *nfc) +{ + writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN, + nfc->regs + HC_CFG); + writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG), + nfc->regs + HC_CFG); +} + +static void mxic_nfc_cs_disable(struct mxic_nand_ctrl *nfc) +{ + writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG), + nfc->regs + HC_CFG); +} + +static int mxic_nfc_data_xfer(struct mxic_nand_ctrl *nfc, const void *txbuf, + void *rxbuf, unsigned int len) +{ + unsigned int pos = 0; + + while (pos < len) { + unsigned int nbytes = len - pos; + u32 data = 0xffffffff; + u32 sts; + int ret; + + if (nbytes > 4) + nbytes = 4; + + if (txbuf) + memcpy(&data, txbuf + pos, nbytes); + + ret = readl_poll_timeout(nfc->regs + INT_STS, sts, + sts & INT_TX_EMPTY, 1000000); + if (ret) + return ret; + + writel(data, nfc->regs + TXD(nbytes % 4)); + + ret = readl_poll_timeout(nfc->regs + INT_STS, sts, + sts & INT_TX_EMPTY, 1000000); + if (ret) + return ret; + + ret = readl_poll_timeout(nfc->regs + INT_STS, sts, + sts & INT_RX_NOT_EMPTY, 1000000); + if (ret) + return ret; + + data = readl(nfc->regs + RXD); + if (rxbuf) { + data >>= (8 * (4 - nbytes)); + memcpy(rxbuf + pos, &data, nbytes); + } + + WARN_ON(readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY); + + pos += nbytes; + } + + return 0; +} + +static uint8_t mxic_nfc_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); + u8 data; + + writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); + writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | + OP_READ, nfc->regs + SS_CTRL(0)); + + mxic_nfc_data_xfer(nfc, NULL, &data, 1); + + return data; +} + +static void mxic_nfc_read_buf(struct mtd_info *mtd, uint8_t *rxbuf, int rlen) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); + + writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); + writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | + OP_READ, nfc->regs + SS_CTRL(0)); + + mxic_nfc_data_xfer(nfc, NULL, rxbuf, rlen); +} + +static void mxic_nfc_write_buf(struct mtd_info *mtd, const uint8_t *txbuf, + int wlen) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); + + writel(wlen, nfc->regs + ONFI_DIN_CNT(0)); + writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F), + nfc->regs + SS_CTRL(0)); + + mxic_nfc_data_xfer(nfc, txbuf, NULL, wlen); +} + +static void mxic_nfc_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); + const struct mxic_nfc_command_format *cmd = NULL; + u32 sts; + u8 index, addr[5]; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Get the command format */ + for (index = 0; index < ARRAY_SIZE(mxic_nand_commands); index++) + if (command == mxic_nand_commands[index].start_cmd) + break; + + cmd = &mxic_nand_commands[index]; + + if (!(command == NAND_CMD_PAGEPROG || + command == NAND_CMD_CACHEDPROG || + command == NAND_CMD_ERASE2)) + mxic_nfc_cs_disable(nfc); + + mxic_nfc_cs_enable(nfc); + + if (column != -1) { + addr[0] = column; + addr[1] = column >> 8; + + if (page_addr != -1) { + addr[2] = page_addr; + addr[3] = page_addr >> 8; + addr[4] = page_addr >> 16; + } + } else if (page_addr != -1) { + addr[0] = page_addr; + addr[1] = page_addr >> 8; + addr[2] = page_addr >> 16; + } + + writel(0, nfc->regs + HC_EN); + writel(HC_EN_BIT, nfc->regs + HC_EN); + writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | OP_CMD_BYTES(0), + nfc->regs + SS_CTRL(0)); + + mxic_nfc_data_xfer(nfc, &cmd->start_cmd, NULL, 1); + + if (cmd->addr_len) { + writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | + OP_ADDR_BYTES(cmd->addr_len), nfc->regs + SS_CTRL(0)); + + mxic_nfc_data_xfer(nfc, &addr, NULL, cmd->addr_len); + } + + if (cmd->end_cmd != NAND_CMD_NONE) { + writel(0, nfc->regs + HC_EN); + writel(HC_EN_BIT, nfc->regs + HC_EN); + writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | + OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0)); + + mxic_nfc_data_xfer(nfc, &cmd->end_cmd, NULL, 1); + } + + readl_poll_timeout(nfc->regs + INT_STS, sts, sts & INT_RDY_PIN, + 1000000); + + if (command == NAND_CMD_PAGEPROG || + command == NAND_CMD_CACHEDPROG || + command == NAND_CMD_ERASE2 || + command == NAND_CMD_RESET) { + mxic_nfc_cs_disable(nfc); + } +} + +static int mxic_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); + const struct nand_sdr_timings *sdr; + unsigned long freq; + int ret; + + sdr = nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) + return 0; + + freq = 1000000000 / (sdr->tRC_min / 1000); + + ret = mxic_nfc_set_freq(nfc, freq); + if (ret) + WARN_ON("Set freq failed\n"); + + if (sdr->tRC_min < 30000) + writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB); + + return 0; +} + +/* Dummy implementation: we don't support multiple chips */ +static void mxic_nfc_select_chip(struct mtd_info *mtd, int chipnr) +{ + switch (chipnr) { + case -1: + case 0: + break; + + default: + BUG(); + } +} + +static int mxic_nfc_probe(struct udevice *dev) +{ + struct mxic_nand_ctrl *nfc = dev_get_priv(dev); + struct nand_chip *nand_chip = &nfc->nand_chip; + struct mtd_info *mtd; + ofnode child; + int err; + + nfc->regs = (void *)dev_read_addr(dev); + + nfc->send_clk = devm_clk_get(dev, "send"); + if (IS_ERR(nfc->send_clk)) + return PTR_ERR(nfc->send_clk); + + nfc->send_dly_clk = devm_clk_get(dev, "send_dly"); + if (IS_ERR(nfc->send_dly_clk)) + return PTR_ERR(nfc->send_dly_clk); + + mtd = nand_to_mtd(nand_chip); + + ofnode_for_each_subnode(child, dev_ofnode(dev)) + nand_set_flash_node(nand_chip, child); + + nand_set_controller_data(nand_chip, nfc); + + nand_chip->select_chip = mxic_nfc_select_chip; + nand_chip->setup_data_interface = mxic_nfc_setup_data_interface; + nand_chip->cmdfunc = mxic_nfc_cmd_function; + nand_chip->read_byte = mxic_nfc_read_byte; + nand_chip->read_buf = mxic_nfc_read_buf; + nand_chip->write_buf = mxic_nfc_write_buf; + + mxic_nfc_hw_init(nfc); + + err = nand_scan(mtd, 1); + if (err) + return err; + + err = nand_register(0, mtd); + if (err) { + dev_err(dev, "Failed to register MTD: %d\n", err); + return err; + } + + return 0; +} + +static const struct udevice_id mxic_nfc_of_ids[] = { + { .compatible = "mxic,multi-itfc-v009-nand-controller" }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(mxic_nfc) = { + .name = "mxic_nfc", + .id = UCLASS_MTD, + .of_match = mxic_nfc_of_ids, + .probe = mxic_nfc_probe, + .priv_auto = sizeof(struct mxic_nand_ctrl), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(mxic_nfc), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} From 41130eb8937e43b2307fb67ebb60f0190fc01438 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti Date: Sun, 26 Sep 2021 21:36:04 +0300 Subject: [PATCH 165/228] fs: fat: check for buffer size before reading blocks This patch optimizes the commit mentioned below by avoiding running a set of commands which are useless in the case when size < mydata->sect_size and sect_count would be 0. Fixes: 5b3ddb17ba ("fs/fat/fat.c: Do not perform zero block reads if there are no blocks left") Signed-off-by: Ricardo Salveti Co-developed-by: Oleksandr Suvorov Signed-off-by: Oleksandr Suvorov --- fs/fat/fat.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 7021138b98..65f77c4f75 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -275,22 +275,19 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) buffer += mydata->sect_size; size -= mydata->sect_size; } - } else { - __u32 idx; + } else if (size >= mydata->sect_size) { + __u32 bytes_read; + __u32 sect_count = size / mydata->sect_size; - idx = size / mydata->sect_size; - if (idx == 0) - ret = 0; - else - ret = disk_read(startsect, idx, buffer); - if (ret != idx) { + ret = disk_read(startsect, sect_count, buffer); + if (ret != sect_count) { debug("Error reading data (got %d)\n", ret); return -1; } - startsect += idx; - idx *= mydata->sect_size; - buffer += idx; - size -= idx; + bytes_read = sect_count * mydata->sect_size; + startsect += sect_count; + buffer += bytes_read; + size -= bytes_read; } if (size) { ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size); From 07c652400d4e67cd11ada02b84c60e73bb031130 Mon Sep 17 00:00:00 2001 From: Mark Tomlinson Date: Tue, 28 Sep 2021 10:10:42 +1300 Subject: [PATCH 166/228] rtc: ds1307: Handle oscillator-stop bit correctly The DS1307 driver was originally based on the DS1337 driver. However, the functionality of the clock set/get functions has diverged. In the original DS1337 driver, the set/get functions did the following: 1) Setting the clock ensured the oscillator was enabled. 2) Getting the clock checked and reset the oscillator-stop flag. The DS1307 does not have an oscillator-stop flag, but the driver tried (incorrectly) to emulate this by ensuring the oscillator was running. It really makes no sense to start a stopped clock without setting it. This patch makes the DS1307 driver behave like the original DS1337 driver again. For the DS1307 itself, this is just a removal of code, since there is no oscillator-fail bit to check or reset, and the clock is started when it is set. Since the DS1307 driver can now also be used for the DS1337 and DS1340 which do have this bit, add code to handle the oscillator-stop bit in the same was the original DS1337 driver did -- i.e. report that the oscillator had stopped and clear the flag. This means that setting the date using the date command (which does both a get and a set) will now clear the oscillator-stop flag in addition to setting and starting the clock. The old-style (non-DM) code has not been updated and will be removed in a future patch. Note that this older code does not support the DS1337, as there is a separate driver for this. Also note that the original (DM) code used the wrong control-register address for the DS1337. Signed-off-by: Mark Tomlinson --- drivers/rtc/ds1307.c | 72 ++++++++++++-------------------------------- 1 file changed, 20 insertions(+), 52 deletions(-) diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 3be97c9d93..1963565c5e 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -41,6 +41,12 @@ enum ds_type { #define RTC_YR_REG_ADDR 0x06 #define RTC_CTL_REG_ADDR 0x07 +#define DS1337_CTL_REG_ADDR 0x0e +#define DS1337_STAT_REG_ADDR 0x0f +#define DS1340_STAT_REG_ADDR 0x09 + +#define RTC_STAT_BIT_OSF 0x80 + #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ /* DS1307-specific bits */ @@ -248,6 +254,11 @@ static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm) if (ret < 0) return ret; + if (type == ds_1337) { + /* Ensure oscillator is enabled */ + dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR, 0); + } + return 0; } @@ -257,62 +268,19 @@ static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm) uchar buf[7]; enum ds_type type = dev_get_driver_data(dev); -read_rtc: ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); if (ret < 0) return ret; - if (type == ds_1307) { - if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) { - printf("### Warning: RTC oscillator has stopped\n"); - /* clear the CH flag */ - buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH; - dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, - buf[RTC_SEC_REG_ADDR]); - return -1; - } - } else if (type == ds_1337) { - if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) { - printf("### Warning: RTC oscillator has stopped\n"); - /* clear the not oscillator enable (~EOSC) flag */ - buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC; - dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, - buf[RTC_CTL_REG_ADDR]); - return -1; - } - } else if (type == ds_1340) { - if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) { - printf("### Warning: RTC oscillator has stopped\n"); - /* clear the not oscillator enable (~EOSC) flag */ - buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC; - dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, - buf[RTC_SEC_REG_ADDR]); - return -1; - } - } else if (type == m41t11) { - /* clock halted? turn it on, so clock can tick. */ - if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) { - buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH; - dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, - MCP7941X_BIT_ST); - dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, - buf[RTC_SEC_REG_ADDR]); - goto read_rtc; - } - } else if (type == mcp794xx) { - /* make sure that the backup battery is enabled */ - if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) { - dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR, - buf[RTC_DAY_REG_ADDR] | - MCP7941X_BIT_VBATEN); - } + if (type == ds_1337 || type == ds_1340) { + uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR : + DS1340_STAT_REG_ADDR; + int status = dm_i2c_reg_read(dev, reg); - /* clock halted? turn it on, so clock can tick. */ - if (!(buf[RTC_SEC_REG_ADDR] & MCP7941X_BIT_ST)) { - dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, - MCP7941X_BIT_ST); - printf("Started RTC\n"); - goto read_rtc; + if (status >= 0 && (status & RTC_STAT_BIT_OSF)) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the OSF flag */ + dm_i2c_reg_write(dev, reg, status & ~RTC_STAT_BIT_OSF); } } @@ -361,7 +329,7 @@ static int ds1307_rtc_reset(struct udevice *dev) /* Write control register in order to enable oscillator output * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1). */ - ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + ret = dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR, DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1); } else if (type == ds_1340 || type == mcp794xx || type == m41t11) { /* Reset clock calibration, frequency test and output level. */ From 2c6bcab6e6e11030611b785d5bad50484424b128 Mon Sep 17 00:00:00 2001 From: Vagrant Cascadian Date: Tue, 28 Sep 2021 10:11:46 -0700 Subject: [PATCH 167/228] tools/image-host.c: Fix spelling of "expected". Signed-off-by: Vagrant Cascadian Reviewed-by: Simon Glass --- tools/image-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/image-host.c b/tools/image-host.c index d3a882ec29..a6b0a94420 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -313,7 +313,7 @@ static int fit_image_read_data(char *filename, unsigned char *data, /* Check that we have read all the file */ if (n != sbuf.st_size) { - printf("Can't read all file %s (read %zd bytes, expexted %lld)\n", + printf("Can't read all file %s (read %zd bytes, expected %lld)\n", filename, n, (long long)sbuf.st_size); goto err; } From 30ac0b496b842ee38d941a3790c8c004f6275d04 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 4 Oct 2021 11:24:51 +0200 Subject: [PATCH 168/228] nvme: invalidate correct memory range after read The current code invalidates the range after the read buffer since the buffer pointer gets incremented in the read loop. Use a temporary pointer to make sure we have a pristine pointer to invalidate the correct memory range after read. Fixes: 704e040a51d2 ("nvme: Apply cache operations on the DMA buffers") Reviewed-by: Andre Przywara Signed-off-by: Stefan Agner --- drivers/nvme/nvme.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index f6465ea7f4..3c529a2fce 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -743,6 +743,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, u64 prp2; u64 total_len = blkcnt << desc->log2blksz; u64 temp_len = total_len; + uintptr_t temp_buffer = (uintptr_t)buffer; u64 slba = blknr; u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); @@ -770,19 +771,19 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, } if (nvme_setup_prps(dev, &prp2, - lbas << ns->lba_shift, (ulong)buffer)) + lbas << ns->lba_shift, temp_buffer)) return -EIO; c.rw.slba = cpu_to_le64(slba); slba += lbas; c.rw.length = cpu_to_le16(lbas - 1); - c.rw.prp1 = cpu_to_le64((ulong)buffer); + c.rw.prp1 = cpu_to_le64(temp_buffer); c.rw.prp2 = cpu_to_le64(prp2); status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], &c, NULL, IO_TIMEOUT); if (status) break; temp_len -= (u32)lbas << ns->lba_shift; - buffer += lbas << ns->lba_shift; + temp_buffer += lbas << ns->lba_shift; } if (read) From d5598cfa9bcab50812b2b416af91c2a37be67531 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:17 +0200 Subject: [PATCH 169/228] fdtdec: Allow using fdtdec_get_carveout() in loops In order make it possible to use fdtdec_get_carveout() in loops, return FDT_ERR_NOTFOUND when the passed-in index exceeds the number of phandles present in the given property. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- lib/fdtdec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index af92e65bde..f2861eb395 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1431,7 +1431,7 @@ int fdtdec_get_carveout(const void *blob, const char *node, const char *name, if (len < (sizeof(phandle) * (index + 1))) { debug("invalid phandle index\n"); - return -FDT_ERR_BADPHANDLE; + return -FDT_ERR_NOTFOUND; } phandle = fdt32_to_cpu(prop[index]); From 4bf88ba76abb224b3ca258a2f502384ec6c86bd6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:18 +0200 Subject: [PATCH 170/228] fdtdec: Support retrieving the name of a carveout When retrieving a given carveout for a device, allow callers to query the name. This helps differentiating between carveouts when there are more than one. This is also useful when copying carveouts to help assign a meaningful name that cannot always be guessed. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- board/nvidia/p2371-2180/p2371-2180.c | 2 +- board/nvidia/p2771-0000/p2771-0000.c | 2 +- board/nvidia/p3450-0000/p3450-0000.c | 2 +- include/fdtdec.h | 8 +++++--- lib/fdtdec.c | 12 ++++++++---- lib/fdtdec_test.c | 3 ++- 6 files changed, 18 insertions(+), 11 deletions(-) diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 7423a97ad0..1f7aa0050c 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -128,7 +128,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) struct fdt_memory fb; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 508c4d27b7..aca86c3426 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -104,7 +104,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) struct fdt_memory fb; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index e6b66966c1..7c1e75307f 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -127,7 +127,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) struct fdt_memory fb; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb); + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, diff --git a/include/fdtdec.h b/include/fdtdec.h index 23efbe710c..f961f03012 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1038,14 +1038,16 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, * * @param blob FDT blob * @param node name of a node - * @param name name of the property in the given node that contains + * @param prop_name name of the property in the given node that contains * the phandle for the carveout * @param index index of the phandle for which to read the carveout * @param carveout return location for the carveout information + * @param name return location for the carveout name * @return 0 on success or a negative error code on failure */ -int fdtdec_get_carveout(const void *blob, const char *node, const char *name, - unsigned int index, struct fdt_memory *carveout); +int fdtdec_get_carveout(const void *blob, const char *node, + const char *prop_name, unsigned int index, + struct fdt_memory *carveout, const char **name); /** * fdtdec_set_carveout() - sets a carveout region for a given node diff --git a/lib/fdtdec.c b/lib/fdtdec.c index f2861eb395..3ada77d80c 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1406,8 +1406,9 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, return 0; } -int fdtdec_get_carveout(const void *blob, const char *node, const char *name, - unsigned int index, struct fdt_memory *carveout) +int fdtdec_get_carveout(const void *blob, const char *node, + const char *prop_name, unsigned int index, + struct fdt_memory *carveout, const char **name) { const fdt32_t *prop; uint32_t phandle; @@ -1418,9 +1419,9 @@ int fdtdec_get_carveout(const void *blob, const char *node, const char *name, if (offset < 0) return offset; - prop = fdt_getprop(blob, offset, name, &len); + prop = fdt_getprop(blob, offset, prop_name, &len); if (!prop) { - debug("failed to get %s for %s\n", name, node); + debug("failed to get %s for %s\n", prop_name, node); return -FDT_ERR_NOTFOUND; } @@ -1442,6 +1443,9 @@ int fdtdec_get_carveout(const void *blob, const char *node, const char *name, return offset; } + if (name) + *name = fdt_get_name(blob, offset, NULL); + carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset, "reg", 0, &size, true); diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c index e0c6e0971c..760aca2669 100644 --- a/lib/fdtdec_test.c +++ b/lib/fdtdec_test.c @@ -214,7 +214,8 @@ static int check_fdt_carveout(void *fdt, uint32_t address_cells, printf("carveout: %pap-%pap na=%u ns=%u: ", &expected.start, &expected.end, address_cells, size_cells); - CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout)); + CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout, + NULL)); if ((carveout.start != expected.start) || (carveout.end != expected.end)) { From 46cb067803bef50cb8a1334a56897d05b5f85e02 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:19 +0200 Subject: [PATCH 171/228] fdtdec: Support compatible string list for reserved memory Reserved memory nodes can have a compatible string list to identify the type of reserved memory that they represent. Support specifying an optional compatible string list when creating these nodes. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +- arch/riscv/lib/fdt_fixup.c | 2 +- board/nvidia/p2371-2180/p2371-2180.c | 5 +- board/nvidia/p2771-0000/p2771-0000.c | 5 +- board/nvidia/p3450-0000/p3450-0000.c | 5 +- include/fdtdec.h | 17 ++++-- lib/fdtdec.c | 69 ++++++++++++++++++++++++- lib/fdtdec_test.c | 4 +- lib/optee/optee.c | 1 + test/dm/fdtdec.c | 18 +++---- 10 files changed, 105 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 41f3e95019..4f17c327af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -54,7 +54,8 @@ int ls_gic_rd_tables_init(void *blob) lpi_base.start = addr; lpi_base.end = addr + size - 1; - ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false); + ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, + NULL, 0, false); if (ret) { debug("%s: failed to add reserved memory\n", __func__); return ret; diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 61cf893526..7ac30a4f7c 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) pmp_mem.start = addr; pmp_mem.end = addr + size - 1; err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, - &phandle, false); + NULL, 0, &phandle, false); if (err < 0 && err != -FDT_ERR_EXISTS) { log_err("failed to add reserved memory: %d\n", err); return err; diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 1f7aa0050c..58077255d0 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -128,7 +128,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) struct fdt_memory fb; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL); + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, + NULL, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, @@ -138,7 +139,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) } err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", - &fb); + NULL, 0, &fb); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index aca86c3426..e35e6b6f48 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -104,7 +104,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) struct fdt_memory fb; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL); + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, + NULL, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, @@ -114,7 +115,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) } err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", - &fb); + NULL, 0, &fb); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index 7c1e75307f..f16916460e 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -127,7 +127,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) struct fdt_memory fb; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL); + err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, + NULL, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, @@ -137,7 +138,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) } err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", - &fb); + NULL, 0, &fb); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/include/fdtdec.h b/include/fdtdec.h index f961f03012..5a6a7cbd99 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -995,7 +995,8 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * }; * uint32_t phandle; * - * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false); + * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, NULL, 0, &phandle, + * false); * * This results in the following subnode being added to the top-level * /reserved-memory node: @@ -1020,6 +1021,8 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * @param blob FDT blob * @param basename base name of the node to create * @param carveout information about the carveout region + * @param compatibles list of compatible strings for the carveout region + * @param count number of compatible strings for the carveout region * @param phandlep return location for the phandle of the carveout region * can be NULL if no phandle should be added * @param no_map add "no-map" property if true @@ -1027,6 +1030,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) */ int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, + const char **compatibles, unsigned int count, uint32_t *phandlep, bool no_map); /** @@ -1043,11 +1047,14 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, * @param index index of the phandle for which to read the carveout * @param carveout return location for the carveout information * @param name return location for the carveout name + * @param compatiblesp return location for compatible strings + * @param countp return location for the number of compatible strings * @return 0 on success or a negative error code on failure */ int fdtdec_get_carveout(const void *blob, const char *node, const char *prop_name, unsigned int index, - struct fdt_memory *carveout, const char **name); + struct fdt_memory *carveout, const char **name, + const char ***compatiblesp, unsigned int *countp); /** * fdtdec_set_carveout() - sets a carveout region for a given node @@ -1065,7 +1072,8 @@ int fdtdec_get_carveout(const void *blob, const char *node, * .end = 0x934b2fff, * }; * - * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb); + * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", NULL, + * 0, &fb); * * dc@54200000 is a display controller and was set up by the bootloader to * scan out the framebuffer specified by "fb". This would cause the following @@ -1104,10 +1112,13 @@ int fdtdec_get_carveout(const void *blob, const char *node, * @param index index of the phandle to store * @param name base name of the reserved-memory node to create * @param carveout information about the carveout to add + * @param compatibles compatible strings to set for the carveout + * @param count number of compatible strings * @return 0 on success or a negative error code on failure */ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, unsigned int index, const char *name, + const char **compatibles, unsigned int count, const struct fdt_memory *carveout); /** diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 3ada77d80c..f124f0555b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1293,6 +1293,7 @@ static int fdtdec_init_reserved_memory(void *blob) int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, + const char **compatibles, unsigned int count, uint32_t *phandlep, bool no_map) { fdt32_t cells[4] = {}, *ptr = cells; @@ -1399,6 +1400,28 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, return err; } + if (compatibles && count > 0) { + size_t length = 0, len = 0; + unsigned int i; + char *buffer; + + for (i = 0; i < count; i++) + length += strlen(compatibles[i]) + 1; + + buffer = malloc(length); + if (!buffer) + return -FDT_ERR_INTERNAL; + + for (i = 0; i < count; i++) + len += strlcpy(buffer + len, compatibles[i], + length - len) + 1; + + err = fdt_setprop(blob, node, "compatible", buffer, length); + free(buffer); + if (err < 0) + return err; + } + /* return the phandle for the new node for the caller to use */ if (phandlep) *phandlep = phandle; @@ -1408,7 +1431,8 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, int fdtdec_get_carveout(const void *blob, const char *node, const char *prop_name, unsigned int index, - struct fdt_memory *carveout, const char **name) + struct fdt_memory *carveout, const char **name, + const char ***compatiblesp, unsigned int *countp) { const fdt32_t *prop; uint32_t phandle; @@ -1446,6 +1470,45 @@ int fdtdec_get_carveout(const void *blob, const char *node, if (name) *name = fdt_get_name(blob, offset, NULL); + if (compatiblesp) { + const char **compatibles = NULL; + const char *start, *end, *ptr; + unsigned int count = 0; + + prop = fdt_getprop(blob, offset, "compatible", &len); + if (!prop) + goto skip_compat; + + start = ptr = (const char *)prop; + end = start + len; + + while (ptr < end) { + ptr = strchrnul(ptr, '\0'); + count++; + ptr++; + } + + compatibles = malloc(sizeof(ptr) * count); + if (!compatibles) + return -FDT_ERR_INTERNAL; + + ptr = start; + count = 0; + + while (ptr < end) { + compatibles[count] = ptr; + ptr = strchrnul(ptr, '\0'); + count++; + ptr++; + } + +skip_compat: + *compatiblesp = compatibles; + + if (countp) + *countp = count; + } + carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset, "reg", 0, &size, true); @@ -1461,6 +1524,7 @@ int fdtdec_get_carveout(const void *blob, const char *node, int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, unsigned int index, const char *name, + const char **compatibles, unsigned int count, const struct fdt_memory *carveout) { uint32_t phandle; @@ -1468,7 +1532,8 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, fdt32_t value; void *prop; - err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false); + err = fdtdec_add_reserved_memory(blob, name, carveout, compatibles, + count, &phandle, false); if (err < 0) { debug("failed to add reserved memory: %d\n", err); return err; diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c index 760aca2669..72c3001a21 100644 --- a/lib/fdtdec_test.c +++ b/lib/fdtdec_test.c @@ -190,7 +190,7 @@ static int make_fdt_carveout_device(void *fdt, uint32_t na, uint32_t ns) CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) * sizeof(*cells))); return fdtdec_set_carveout(fdt, name, "memory-region", 0, - "framebuffer", &carveout); + "framebuffer", NULL, 0, &carveout); } static int check_fdt_carveout(void *fdt, uint32_t address_cells, @@ -215,7 +215,7 @@ static int check_fdt_carveout(void *fdt, uint32_t address_cells, &expected.end, address_cells, size_cells); CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout, - NULL)); + NULL, NULL, NULL)); if ((carveout.start != expected.start) || (carveout.end != expected.end)) { diff --git a/lib/optee/optee.c b/lib/optee/optee.c index 766d0d9e3f..3fbde934fb 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -177,6 +177,7 @@ int optee_copy_fdt_nodes(void *new_blob) ret = fdtdec_add_reserved_memory(new_blob, nodename, &carveout, + NULL, 0, NULL, true); free(oldname); diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 1f630ea3ee..7b543e7b99 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -30,19 +30,19 @@ static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts) resv.end = 0x2000; ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 2, "test_resv1", - &resv)); + NULL, 0, &resv)); resv.start = 0x10000; resv.end = 0x20000; ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 1, "test_resv2", - &resv)); + NULL, 0, &resv)); resv.start = 0x100000; resv.end = 0x200000; ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 0, "test_resv3", - &resv)); + NULL, 0, &resv)); offset = fdt_path_offset(blob, "/a-test"); ut_assert(offset > 0); @@ -80,8 +80,8 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) /* Insert a memory region in /reserved-memory node */ resv.start = 0x1000; resv.end = 0x1fff; - ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", - &resv, &phandle, false)); + ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", &resv, + NULL, 0, &phandle, false)); /* Test /reserve-memory and its subnode should exist */ parent = fdt_path_offset(blob, "/reserved-memory"); @@ -101,8 +101,8 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x2000; resv.end = 0x2fff; - ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", - &resv, &phandle1, true)); + ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", &resv, + NULL, 0, &phandle1, true)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1"); ut_assert(subnode > 0); @@ -118,8 +118,8 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) */ resv.start = 0x1000; resv.end = 0x1fff; - ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", - &resv, &phandle1, false)); + ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", &resv, + NULL, 0, &phandle1, false)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2"); ut_assert(subnode < 0); From 9019487608c8afe7d3fc34cb5192df064b60cdb7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:20 +0200 Subject: [PATCH 172/228] fdtdec: Reorder fdtdec_set_carveout() parameters for consistency The fdtdec_set_carveout() function's parameters are inconsistent with the parameters passed to fdtdec_add_reserved_memory(). Fix up the order to make it more consistent. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- board/nvidia/p2371-2180/p2371-2180.c | 4 ++-- board/nvidia/p2771-0000/p2771-0000.c | 4 ++-- board/nvidia/p3450-0000/p3450-0000.c | 4 ++-- include/fdtdec.h | 8 ++++---- lib/fdtdec.c | 6 +++--- lib/fdtdec_test.c | 4 ++-- test/dm/fdtdec.c | 15 ++++++--------- 7 files changed, 21 insertions(+), 24 deletions(-) diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 58077255d0..bc0a133725 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -138,8 +138,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) return err; } - err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", - NULL, 0, &fb); + err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, + "framebuffer", NULL, 0); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index e35e6b6f48..cde5eff02f 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -114,8 +114,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) return err; } - err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", - NULL, 0, &fb); + err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, + "framebuffer", NULL, 0); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index f16916460e..e737fc1dab 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -137,8 +137,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) return err; } - err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer", - NULL, 0, &fb); + err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, + "framebuffer", NULL, 0); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/include/fdtdec.h b/include/fdtdec.h index 5a6a7cbd99..d360d7bce4 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1110,16 +1110,16 @@ int fdtdec_get_carveout(const void *blob, const char *node, * @param prop_name name of the property in which to store the phandle of * the carveout * @param index index of the phandle to store - * @param name base name of the reserved-memory node to create * @param carveout information about the carveout to add + * @param name base name of the reserved-memory node to create * @param compatibles compatible strings to set for the carveout * @param count number of compatible strings * @return 0 on success or a negative error code on failure */ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, - unsigned int index, const char *name, - const char **compatibles, unsigned int count, - const struct fdt_memory *carveout); + unsigned int index, const struct fdt_memory *carveout, + const char *name, const char **compatibles, + unsigned int count); /** * Set up the device tree ready for use diff --git a/lib/fdtdec.c b/lib/fdtdec.c index f124f0555b..a0ecc72b6c 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1523,9 +1523,9 @@ skip_compat: } int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, - unsigned int index, const char *name, - const char **compatibles, unsigned int count, - const struct fdt_memory *carveout) + unsigned int index, const struct fdt_memory *carveout, + const char *name, const char **compatibles, + unsigned int count) { uint32_t phandle; int err, offset, len; diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c index 72c3001a21..3af9fb5da6 100644 --- a/lib/fdtdec_test.c +++ b/lib/fdtdec_test.c @@ -189,8 +189,8 @@ static int make_fdt_carveout_device(void *fdt, uint32_t na, uint32_t ns) offset = CHECK(fdt_add_subnode(fdt, 0, name + 1)); CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) * sizeof(*cells))); - return fdtdec_set_carveout(fdt, name, "memory-region", 0, - "framebuffer", NULL, 0, &carveout); + return fdtdec_set_carveout(fdt, name, "memory-region", 0, &carveout, + "framebuffer", NULL, 0); } static int check_fdt_carveout(void *fdt, uint32_t address_cells, diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 7b543e7b99..385aa77a68 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -28,21 +28,18 @@ static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x2000; - ut_assertok(fdtdec_set_carveout(blob, "/a-test", - "memory-region", 2, "test_resv1", - NULL, 0, &resv)); + ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 2, + &resv, "test_resv1", NULL, 0)); resv.start = 0x10000; resv.end = 0x20000; - ut_assertok(fdtdec_set_carveout(blob, "/a-test", - "memory-region", 1, "test_resv2", - NULL, 0, &resv)); + ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 1, + &resv, "test_resv2", NULL, 0)); resv.start = 0x100000; resv.end = 0x200000; - ut_assertok(fdtdec_set_carveout(blob, "/a-test", - "memory-region", 0, "test_resv3", - NULL, 0, &resv)); + ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 0, + &resv, "test_resv3", NULL, 0)); offset = fdt_path_offset(blob, "/a-test"); ut_assert(offset > 0); From b9aad375917d4ae0dec5aedcdfa79929e1dbb730 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:21 +0200 Subject: [PATCH 173/228] fdtdec: Support reserved-memory flags Reserved memory nodes can have additional flags. Support reading and writing these flags to ensure that reserved memory nodes can be properly parsed and emitted. This converts support for the existing "no-map" flag to avoid extending the argument list for fdtdec_add_reserved_memory() to excessive length. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- arch/riscv/lib/fdt_fixup.c | 2 +- board/nvidia/p2371-2180/p2371-2180.c | 4 ++-- board/nvidia/p2771-0000/p2771-0000.c | 4 ++-- board/nvidia/p3450-0000/p3450-0000.c | 4 ++-- include/fdtdec.h | 20 +++++++++++------- lib/fdtdec.c | 28 ++++++++++++++++--------- lib/fdtdec_test.c | 4 ++-- lib/optee/optee.c | 3 ++- test/dm/fdtdec.c | 13 ++++++------ 10 files changed, 50 insertions(+), 34 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 4f17c327af..adf3b4eea5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -55,7 +55,7 @@ int ls_gic_rd_tables_init(void *blob) lpi_base.start = addr; lpi_base.end = addr + size - 1; ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, - NULL, 0, false); + NULL, 0, 0); if (ret) { debug("%s: failed to add reserved memory\n", __func__); return ret; diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 7ac30a4f7c..36c16e9be2 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) pmp_mem.start = addr; pmp_mem.end = addr + size - 1; err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, - NULL, 0, &phandle, false); + NULL, 0, &phandle, 0); if (err < 0 && err != -FDT_ERR_EXISTS) { log_err("failed to add reserved memory: %d\n", err); return err; diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index bc0a133725..137c7d3b12 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -129,7 +129,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) int err; err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, - NULL, NULL); + NULL, NULL, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, @@ -139,7 +139,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) } err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, - "framebuffer", NULL, 0); + "framebuffer", NULL, 0, 0); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index cde5eff02f..3d2653d1f0 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -105,7 +105,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) int err; err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, - NULL, NULL); + NULL, NULL, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, @@ -115,7 +115,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) } err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, - "framebuffer", NULL, 0); + "framebuffer", NULL, 0, 0); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index e737fc1dab..2770862a49 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -128,7 +128,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) int err; err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, - NULL, NULL); + NULL, NULL, NULL); if (err < 0) { if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, @@ -138,7 +138,7 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) } err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, - "framebuffer", NULL, 0); + "framebuffer", NULL, 0, 0); if (err < 0) { printf("failed to set carveout for %s: %d\n", node, err); return err; diff --git a/include/fdtdec.h b/include/fdtdec.h index d360d7bce4..f94d1f4f3a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -977,6 +977,9 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) return fdt_setprop_u32(blob, node, "phandle", phandle); } +/* add "no-map" property */ +#define FDTDEC_RESERVED_MEMORY_NO_MAP (1 << 0) + /** * fdtdec_add_reserved_memory() - add or find a reserved-memory node * @@ -996,7 +999,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * uint32_t phandle; * * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, NULL, 0, &phandle, - * false); + * 0); * * This results in the following subnode being added to the top-level * /reserved-memory node: @@ -1025,13 +1028,13 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * @param count number of compatible strings for the carveout region * @param phandlep return location for the phandle of the carveout region * can be NULL if no phandle should be added - * @param no_map add "no-map" property if true + * @param flags bitmask of flags to set for the carveout region * @return 0 on success or a negative error code on failure */ int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, const char **compatibles, unsigned int count, - uint32_t *phandlep, bool no_map); + uint32_t *phandlep, unsigned long flags); /** * fdtdec_get_carveout() - reads a carveout from an FDT @@ -1048,13 +1051,15 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, * @param carveout return location for the carveout information * @param name return location for the carveout name * @param compatiblesp return location for compatible strings - * @param countp return location for the number of compatible strings + * @param countp return location for the number of compatible strings + * @param flags return location for the flags of the carveout * @return 0 on success or a negative error code on failure */ int fdtdec_get_carveout(const void *blob, const char *node, const char *prop_name, unsigned int index, struct fdt_memory *carveout, const char **name, - const char ***compatiblesp, unsigned int *countp); + const char ***compatiblesp, unsigned int *countp, + unsigned long *flags); /** * fdtdec_set_carveout() - sets a carveout region for a given node @@ -1073,7 +1078,7 @@ int fdtdec_get_carveout(const void *blob, const char *node, * }; * * fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", NULL, - * 0, &fb); + * 0, &fb, 0); * * dc@54200000 is a display controller and was set up by the bootloader to * scan out the framebuffer specified by "fb". This would cause the following @@ -1114,12 +1119,13 @@ int fdtdec_get_carveout(const void *blob, const char *node, * @param name base name of the reserved-memory node to create * @param compatibles compatible strings to set for the carveout * @param count number of compatible strings + * @param flags bitmask of flags to set for the carveout * @return 0 on success or a negative error code on failure */ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, unsigned int index, const struct fdt_memory *carveout, const char *name, const char **compatibles, - unsigned int count); + unsigned int count, unsigned long flags); /** * Set up the device tree ready for use diff --git a/lib/fdtdec.c b/lib/fdtdec.c index a0ecc72b6c..ad090ea51e 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1294,7 +1294,7 @@ static int fdtdec_init_reserved_memory(void *blob) int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, const char **compatibles, unsigned int count, - uint32_t *phandlep, bool no_map) + uint32_t *phandlep, unsigned long flags) { fdt32_t cells[4] = {}, *ptr = cells; uint32_t upper, lower, phandle; @@ -1364,6 +1364,12 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, if (node < 0) return node; + if (flags & FDTDEC_RESERVED_MEMORY_NO_MAP) { + err = fdt_setprop(blob, node, "no-map", NULL, 0); + if (err < 0) + return err; + } + if (phandlep) { err = fdt_generate_phandle(blob, &phandle); if (err < 0) @@ -1394,12 +1400,6 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, if (err < 0) return err; - if (no_map) { - err = fdt_setprop(blob, node, "no-map", NULL, 0); - if (err < 0) - return err; - } - if (compatibles && count > 0) { size_t length = 0, len = 0; unsigned int i; @@ -1432,7 +1432,8 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, int fdtdec_get_carveout(const void *blob, const char *node, const char *prop_name, unsigned int index, struct fdt_memory *carveout, const char **name, - const char ***compatiblesp, unsigned int *countp) + const char ***compatiblesp, unsigned int *countp, + unsigned long *flags) { const fdt32_t *prop; uint32_t phandle; @@ -1519,13 +1520,20 @@ skip_compat: carveout->end = carveout->start + size - 1; + if (flags) { + *flags = 0; + + if (fdtdec_get_bool(blob, offset, "no-map")) + *flags |= FDTDEC_RESERVED_MEMORY_NO_MAP; + } + return 0; } int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, unsigned int index, const struct fdt_memory *carveout, const char *name, const char **compatibles, - unsigned int count) + unsigned int count, unsigned long flags) { uint32_t phandle; int err, offset, len; @@ -1533,7 +1541,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, void *prop; err = fdtdec_add_reserved_memory(blob, name, carveout, compatibles, - count, &phandle, false); + count, &phandle, flags); if (err < 0) { debug("failed to add reserved memory: %d\n", err); return err; diff --git a/lib/fdtdec_test.c b/lib/fdtdec_test.c index 3af9fb5da6..85351c75ca 100644 --- a/lib/fdtdec_test.c +++ b/lib/fdtdec_test.c @@ -190,7 +190,7 @@ static int make_fdt_carveout_device(void *fdt, uint32_t na, uint32_t ns) CHECK(fdt_setprop(fdt, offset, "reg", cells, (na + ns) * sizeof(*cells))); return fdtdec_set_carveout(fdt, name, "memory-region", 0, &carveout, - "framebuffer", NULL, 0); + "framebuffer", NULL, 0, 0); } static int check_fdt_carveout(void *fdt, uint32_t address_cells, @@ -215,7 +215,7 @@ static int check_fdt_carveout(void *fdt, uint32_t address_cells, &expected.end, address_cells, size_cells); CHECK(fdtdec_get_carveout(fdt, name, "memory-region", 0, &carveout, - NULL, NULL, NULL)); + NULL, NULL, NULL, NULL)); if ((carveout.start != expected.start) || (carveout.end != expected.end)) { diff --git a/lib/optee/optee.c b/lib/optee/optee.c index 3fbde934fb..b036224044 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -161,6 +161,7 @@ int optee_copy_fdt_nodes(void *new_blob) .start = res.start, .end = res.end, }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; char *oldname, *nodename, *tmp; oldname = strdup(name); @@ -178,7 +179,7 @@ int optee_copy_fdt_nodes(void *new_blob) nodename, &carveout, NULL, 0, - NULL, true); + NULL, flags); free(oldname); if (ret < 0) diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 385aa77a68..087d4846da 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -29,17 +29,17 @@ static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x2000; ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 2, - &resv, "test_resv1", NULL, 0)); + &resv, "test_resv1", NULL, 0, 0)); resv.start = 0x10000; resv.end = 0x20000; ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 1, - &resv, "test_resv2", NULL, 0)); + &resv, "test_resv2", NULL, 0, 0)); resv.start = 0x100000; resv.end = 0x200000; ut_assertok(fdtdec_set_carveout(blob, "/a-test", "memory-region", 0, - &resv, "test_resv3", NULL, 0)); + &resv, "test_resv3", NULL, 0, 0)); offset = fdt_path_offset(blob, "/a-test"); ut_assert(offset > 0); @@ -64,6 +64,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) fdt_addr_t addr; fdt_size_t size; void *blob; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; int blob_sz, parent, subnode; uint32_t phandle, phandle1; @@ -78,7 +79,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x1fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", &resv, - NULL, 0, &phandle, false)); + NULL, 0, &phandle, 0)); /* Test /reserve-memory and its subnode should exist */ parent = fdt_path_offset(blob, "/reserved-memory"); @@ -99,7 +100,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x2000; resv.end = 0x2fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", &resv, - NULL, 0, &phandle1, true)); + NULL, 0, &phandle1, flags)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1"); ut_assert(subnode > 0); @@ -116,7 +117,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x1fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", &resv, - NULL, 0, &phandle1, false)); + NULL, 0, &phandle1, 0)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2"); ut_assert(subnode < 0); From db8a0306c91c470854fcfb9b3373ab98b18d3eba Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:22 +0200 Subject: [PATCH 174/228] ARM: tegra: Support multiple reserved memory regions Support multiple reserved memory regions per device to support platforms that use both a framebuffer and color conversion lookup table for early boot display splash. While at it, also pass along the name, compatible strings and flags of the carveouts. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- board/nvidia/p2371-2180/p2371-2180.c | 55 +++++++++++++++++++++------- board/nvidia/p2771-0000/p2771-0000.c | 55 +++++++++++++++++++++------- board/nvidia/p3450-0000/p3450-0000.c | 55 +++++++++++++++++++++------- 3 files changed, 126 insertions(+), 39 deletions(-) diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 137c7d3b12..f5126c552b 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -125,24 +126,52 @@ static void ft_mac_address_setup(void *fdt) static int ft_copy_carveout(void *dst, const void *src, const char *node) { - struct fdt_memory fb; + unsigned int index = 0; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, - NULL, NULL, NULL); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to get carveout for %s: %d\n", node, + while (true) { + const char **compatibles = NULL; + unsigned int num_compatibles; + struct fdt_memory carveout; + unsigned long flags; + char *copy = NULL; + const char *name; + + err = fdtdec_get_carveout(src, node, "memory-region", index, + &carveout, &name, &compatibles, + &num_compatibles, &flags); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", + node, err); + + return err; + } + + if (name) { + const char *ptr = strchr(name, '@'); + + if (ptr) { + copy = strndup(name, ptr - name); + name = copy; + } + } else { + name = "carveout"; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", index, + &carveout, name, compatibles, + num_compatibles, flags); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, err); + return err; + } - return err; - } + if (copy) + free(copy); - err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, - "framebuffer", NULL, 0, 0); - if (err < 0) { - printf("failed to set carveout for %s: %d\n", node, err); - return err; + index++; } return 0; diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 3d2653d1f0..46c36a22db 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "../p2571/max77620_init.h" @@ -101,24 +102,52 @@ static void ft_mac_address_setup(void *fdt) static int ft_copy_carveout(void *dst, const void *src, const char *node) { - struct fdt_memory fb; + unsigned int index = 0; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, - NULL, NULL, NULL); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to get carveout for %s: %d\n", node, + while (true) { + const char **compatibles = NULL; + unsigned int num_compatibles; + struct fdt_memory carveout; + unsigned long flags; + char *copy = NULL; + const char *name; + + err = fdtdec_get_carveout(src, node, "memory-region", index, + &carveout, &name, &compatibles, + &num_compatibles, &flags); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", + node, err); + + return err; + } + + if (name) { + const char *ptr = strchr(name, '@'); + + if (ptr) { + copy = strndup(name, ptr - name); + name = copy; + } + } else { + name = "carveout"; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", index, + &carveout, name, compatibles, + num_compatibles, flags); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, err); + return err; + } - return err; - } + if (copy) + free(copy); - err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, - "framebuffer", NULL, 0, 0); - if (err < 0) { - printf("failed to set carveout for %s: %d\n", node, err); - return err; + index++; } return 0; diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index 2770862a49..97b99001a9 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -124,24 +125,52 @@ static void ft_mac_address_setup(void *fdt) static int ft_copy_carveout(void *dst, const void *src, const char *node) { - struct fdt_memory fb; + unsigned int index = 0; int err; - err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb, NULL, - NULL, NULL, NULL); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to get carveout for %s: %d\n", node, + while (true) { + const char **compatibles = NULL; + unsigned int num_compatibles; + struct fdt_memory carveout; + unsigned long flags; + char *copy = NULL; + const char *name; + + err = fdtdec_get_carveout(src, node, "memory-region", index, + &carveout, &name, &compatibles, + &num_compatibles, &flags); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", + node, err); + + return err; + } + + if (name) { + const char *ptr = strchr(name, '@'); + + if (ptr) { + copy = strndup(name, ptr - name); + name = copy; + } + } else { + name = "carveout"; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", index, + &carveout, name, compatibles, + num_compatibles, flags); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, err); + return err; + } - return err; - } + if (copy) + free(copy); - err = fdtdec_set_carveout(dst, node, "memory-region", 0, &fb, - "framebuffer", NULL, 0, 0); - if (err < 0) { - printf("failed to set carveout for %s: %d\n", node, err); - return err; + index++; } return 0; From f814ff5e0b10a0b6a1b303a849e68f302f0d8627 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 13 Oct 2021 13:06:02 -0700 Subject: [PATCH 175/228] ARM: tegra: Support EMC frequency tables on Tegra210 The EMC frequency tables are created from a training sequence performed during early boot and passed in via a reserved memory region by nvtboot. Copy this table to the kernel DTB so that the kernel can use it to scale the EMC frequency at runtime. Note that early bootloaders store the EMC table at an address that currently intersects with the load address of the initial ramdisk. In order to avoid copying the table to a different address, simply change the load address for the initial ramdisk in U-Boot. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- board/nvidia/p2371-2180/p2371-2180.c | 1 + board/nvidia/p3450-0000/p3450-0000.c | 1 + include/configs/tegra210-common.h | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index f5126c552b..cd5dc2de62 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -183,6 +183,7 @@ static void ft_carveout_setup(void *fdt) static const char * const nodes[] = { "/host1x@50000000/dc@54200000", "/host1x@50000000/dc@54240000", + "/external-memory-controller@7001b000", }; unsigned int i; int err; diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index 97b99001a9..ba57528265 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -182,6 +182,7 @@ static void ft_carveout_setup(void *fdt) static const char * const nodes[] = { "/host1x@50000000/dc@54200000", "/host1x@50000000/dc@54240000", + "/external-memory-controller@7001b000", }; unsigned int i; int err; diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index b9e04147be..e1b91f6250 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -44,7 +44,7 @@ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83200000\0" + "ramdisk_addr_r=0x83420000\0" /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI From 77409c7f83622a71060bf78142149d39540ba405 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:24 +0200 Subject: [PATCH 176/228] ARM: tegra: Refactor DT update helpers Rather than duplicate the Ethernet MAC address and carveout updating code for each board, move it to a common location and make it more reusable. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/board.h | 10 ++ arch/arm/mach-tegra/dt-setup.c | 118 ++++++++++++++++++++++ board/nvidia/p2371-2180/p2371-2180.c | 123 ++--------------------- board/nvidia/p2771-0000/p2771-0000.c | 126 ++--------------------- board/nvidia/p3450-0000/p3450-0000.c | 127 ++---------------------- 5 files changed, 149 insertions(+), 355 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 24d0db8ced..cd4d0ee3c9 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -30,4 +30,14 @@ void pin_mux_nand(void); /* overridable NAND pinmux setup */ void pin_mux_mmc(void); /* overridable mmc pinmux setup */ void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ +/* + * Helpers for various standard DT update mechanisms. + */ + +#if defined(CONFIG_ARM64) +void ft_mac_address_setup(void *fdt); +void ft_carveout_setup(void *fdt, const char *const *nodes, + unsigned int count); +#endif + #endif diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index 602b20e6b7..894a6358a2 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include /* @@ -31,3 +34,118 @@ int ft_system_setup(void *blob, struct bd_info *bd) return 0; } + +#if defined(CONFIG_ARM64) +void ft_mac_address_setup(void *fdt) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; + const char *path; + int offset, err; + + err = cboot_get_ethaddr(cboot_fdt, local_mac); + if (err < 0) + memset(local_mac, 0, ETH_ALEN); + + path = fdt_get_alias(fdt, "ethernet"); + if (!path) + return; + + debug("ethernet alias found: %s\n", path); + + offset = fdt_path_offset(fdt, path); + if (offset < 0) { + printf("ethernet alias points to absent node %s\n", path); + return; + } + + if (is_valid_ethaddr(local_mac)) { + err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, + ETH_ALEN); + if (!err) + debug("Local MAC address set: %pM\n", local_mac); + } + + if (eth_env_get_enetaddr("ethaddr", mac)) { + if (memcmp(local_mac, mac, ETH_ALEN) != 0) { + err = fdt_setprop(fdt, offset, "mac-address", mac, + ETH_ALEN); + if (!err) + debug("MAC address set: %pM\n", mac); + } + } +} + +static int ft_copy_carveout(void *dst, const void *src, const char *node) +{ + struct fdt_memory carveout; + unsigned int index = 0; + int err; + + while (true) { + const char **compatibles = NULL; + unsigned int num_compatibles; + unsigned long flags; + char *copy = NULL; + const char *name; + + err = fdtdec_get_carveout(src, node, "memory-region", index, + &carveout, &name, &compatibles, + &num_compatibles, &flags); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to get carveout for %s: %d\n", + node, err); + + return err; + } + + if (name) { + const char *ptr = strchr(name, '@'); + + if (ptr) { + copy = strndup(name, ptr - name); + name = copy; + } + } else { + name = "carveout"; + } + + err = fdtdec_set_carveout(dst, node, "memory-region", index, + &carveout, name, compatibles, + num_compatibles, flags); + if (err < 0) { + printf("failed to set carveout for %s: %d\n", node, + err); + return err; + } + + if (copy) + free(copy); + + index++; + } + + return 0; +} + +void ft_carveout_setup(void *fdt, const char * const *nodes, unsigned int count) +{ + const void *cboot_fdt = (const void *)cboot_boot_x0; + unsigned int i; + int err; + + for (i = 0; i < count; i++) { + printf("copying carveout for %s...\n", nodes[i]); + + err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); + if (err < 0) { + if (err != -FDT_ERR_NOTFOUND) + printf("failed to copy carveout for %s: %d\n", + nodes[i], err); + + continue; + } + } +} +#endif diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index cd5dc2de62..816c7bec6a 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include "../p2571/max77620_init.h" void pin_mux_mmc(void) @@ -84,125 +84,16 @@ int tegra_pcie_board_init(void) } #endif /* PCI */ -static void ft_mac_address_setup(void *fdt) -{ - const void *cboot_fdt = (const void *)cboot_boot_x0; - uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; - const char *path; - int offset, err; - - err = cboot_get_ethaddr(cboot_fdt, local_mac); - if (err < 0) - memset(local_mac, 0, ETH_ALEN); - - path = fdt_get_alias(fdt, "ethernet"); - if (!path) - return; - - debug("ethernet alias found: %s\n", path); - - offset = fdt_path_offset(fdt, path); - if (offset < 0) { - printf("ethernet alias points to absent node %s\n", path); - return; - } - - if (is_valid_ethaddr(local_mac)) { - err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, - ETH_ALEN); - if (!err) - debug("Local MAC address set: %pM\n", local_mac); - } - - if (eth_env_get_enetaddr("ethaddr", mac)) { - if (memcmp(local_mac, mac, ETH_ALEN) != 0) { - err = fdt_setprop(fdt, offset, "mac-address", mac, - ETH_ALEN); - if (!err) - debug("MAC address set: %pM\n", mac); - } - } -} - -static int ft_copy_carveout(void *dst, const void *src, const char *node) -{ - unsigned int index = 0; - int err; - - while (true) { - const char **compatibles = NULL; - unsigned int num_compatibles; - struct fdt_memory carveout; - unsigned long flags; - char *copy = NULL; - const char *name; - - err = fdtdec_get_carveout(src, node, "memory-region", index, - &carveout, &name, &compatibles, - &num_compatibles, &flags); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to get carveout for %s: %d\n", - node, err); - - return err; - } - - if (name) { - const char *ptr = strchr(name, '@'); - - if (ptr) { - copy = strndup(name, ptr - name); - name = copy; - } - } else { - name = "carveout"; - } - - err = fdtdec_set_carveout(dst, node, "memory-region", index, - &carveout, name, compatibles, - num_compatibles, flags); - if (err < 0) { - printf("failed to set carveout for %s: %d\n", node, - err); - return err; - } - - if (copy) - free(copy); - - index++; - } - - return 0; -} - -static void ft_carveout_setup(void *fdt) -{ - const void *cboot_fdt = (const void *)cboot_boot_x0; - static const char * const nodes[] = { - "/host1x@50000000/dc@54200000", - "/host1x@50000000/dc@54240000", - "/external-memory-controller@7001b000", - }; - unsigned int i; - int err; - - for (i = 0; i < ARRAY_SIZE(nodes); i++) { - err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to copy carveout for %s: %d\n", - nodes[i], err); - continue; - } - } -} +static const char * const nodes[] = { + "/host1x@50000000/dc@54200000", + "/host1x@50000000/dc@54240000", + "/external-memory-controller@7001b000", +}; int ft_board_setup(void *fdt, struct bd_info *bd) { ft_mac_address_setup(fdt); - ft_carveout_setup(fdt); + ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes)); return 0; } diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 46c36a22db..5ff89c4542 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "../p2571/max77620_init.h" void pin_mux_mmc(void) @@ -60,128 +60,16 @@ int tegra_pcie_board_init(void) } #endif -static void ft_mac_address_setup(void *fdt) -{ - const void *cboot_fdt = (const void *)cboot_boot_x0; - uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; - const char *path; - int offset, err; - - err = cboot_get_ethaddr(cboot_fdt, local_mac); - if (err < 0) - memset(local_mac, 0, ETH_ALEN); - - path = fdt_get_alias(fdt, "ethernet"); - if (!path) - return; - - debug("ethernet alias found: %s\n", path); - - offset = fdt_path_offset(fdt, path); - if (offset < 0) { - printf("ethernet alias points to absent node %s\n", path); - return; - } - - if (is_valid_ethaddr(local_mac)) { - err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, - ETH_ALEN); - if (!err) - debug("Local MAC address set: %pM\n", local_mac); - } - - if (eth_env_get_enetaddr("ethaddr", mac)) { - if (memcmp(local_mac, mac, ETH_ALEN) != 0) { - err = fdt_setprop(fdt, offset, "mac-address", mac, - ETH_ALEN); - if (!err) - debug("MAC address set: %pM\n", mac); - } - } -} - -static int ft_copy_carveout(void *dst, const void *src, const char *node) -{ - unsigned int index = 0; - int err; - - while (true) { - const char **compatibles = NULL; - unsigned int num_compatibles; - struct fdt_memory carveout; - unsigned long flags; - char *copy = NULL; - const char *name; - - err = fdtdec_get_carveout(src, node, "memory-region", index, - &carveout, &name, &compatibles, - &num_compatibles, &flags); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to get carveout for %s: %d\n", - node, err); - - return err; - } - - if (name) { - const char *ptr = strchr(name, '@'); - - if (ptr) { - copy = strndup(name, ptr - name); - name = copy; - } - } else { - name = "carveout"; - } - - err = fdtdec_set_carveout(dst, node, "memory-region", index, - &carveout, name, compatibles, - num_compatibles, flags); - if (err < 0) { - printf("failed to set carveout for %s: %d\n", node, - err); - return err; - } - - if (copy) - free(copy); - - index++; - } - - return 0; -} - -static void ft_carveout_setup(void *fdt) -{ - const void *cboot_fdt = (const void *)cboot_boot_x0; - static const char * const nodes[] = { - "/host1x@13e00000/display-hub@15200000/display@15200000", - "/host1x@13e00000/display-hub@15200000/display@15210000", - "/host1x@13e00000/display-hub@15200000/display@15220000", - }; - unsigned int i; - int err; - - for (i = 0; i < ARRAY_SIZE(nodes); i++) { - printf("copying carveout for %s...\n", nodes[i]); - - err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to copy carveout for %s: %d\n", - nodes[i], err); - - continue; - } - } -} +static const char * const nodes[] = { + "/host1x@13e00000/display-hub@15200000/display@15200000", + "/host1x@13e00000/display-hub@15200000/display@15210000", + "/host1x@13e00000/display-hub@15200000/display@15220000", +}; int ft_board_setup(void *fdt, struct bd_info *bd) { ft_mac_address_setup(fdt); - ft_carveout_setup(fdt); + ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes)); return 0; } diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c index ba57528265..fb1a224daa 100644 --- a/board/nvidia/p3450-0000/p3450-0000.c +++ b/board/nvidia/p3450-0000/p3450-0000.c @@ -11,10 +11,9 @@ #include #include #include -#include -#include #include #include +#include #include "../p2571/max77620_init.h" void pin_mux_mmc(void) @@ -83,128 +82,16 @@ int tegra_pcie_board_init(void) } #endif /* PCI */ -static void ft_mac_address_setup(void *fdt) -{ - const void *cboot_fdt = (const void *)cboot_boot_x0; - uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN]; - const char *path; - int offset, err; - - err = cboot_get_ethaddr(cboot_fdt, local_mac); - if (err < 0) - memset(local_mac, 0, ETH_ALEN); - - path = fdt_get_alias(fdt, "ethernet"); - if (!path) - return; - - debug("ethernet alias found: %s\n", path); - - offset = fdt_path_offset(fdt, path); - if (offset < 0) { - printf("ethernet alias points to absent node %s\n", path); - return; - } - - if (is_valid_ethaddr(local_mac)) { - err = fdt_setprop(fdt, offset, "local-mac-address", local_mac, - ETH_ALEN); - if (!err) - debug("Local MAC address set: %pM\n", local_mac); - } - - if (eth_env_get_enetaddr("ethaddr", mac)) { - if (memcmp(local_mac, mac, ETH_ALEN) != 0) { - err = fdt_setprop(fdt, offset, "mac-address", mac, - ETH_ALEN); - if (!err) - debug("MAC address set: %pM\n", mac); - } - } -} - -static int ft_copy_carveout(void *dst, const void *src, const char *node) -{ - unsigned int index = 0; - int err; - - while (true) { - const char **compatibles = NULL; - unsigned int num_compatibles; - struct fdt_memory carveout; - unsigned long flags; - char *copy = NULL; - const char *name; - - err = fdtdec_get_carveout(src, node, "memory-region", index, - &carveout, &name, &compatibles, - &num_compatibles, &flags); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to get carveout for %s: %d\n", - node, err); - - return err; - } - - if (name) { - const char *ptr = strchr(name, '@'); - - if (ptr) { - copy = strndup(name, ptr - name); - name = copy; - } - } else { - name = "carveout"; - } - - err = fdtdec_set_carveout(dst, node, "memory-region", index, - &carveout, name, compatibles, - num_compatibles, flags); - if (err < 0) { - printf("failed to set carveout for %s: %d\n", node, - err); - return err; - } - - if (copy) - free(copy); - - index++; - } - - return 0; -} - -static void ft_carveout_setup(void *fdt) -{ - const void *cboot_fdt = (const void *)cboot_boot_x0; - static const char * const nodes[] = { - "/host1x@50000000/dc@54200000", - "/host1x@50000000/dc@54240000", - "/external-memory-controller@7001b000", - }; - unsigned int i; - int err; - - for (i = 0; i < ARRAY_SIZE(nodes); i++) { - printf("copying carveout for %s...\n", nodes[i]); - - err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]); - if (err < 0) { - if (err != -FDT_ERR_NOTFOUND) - printf("failed to copy carveout for %s: %d\n", - nodes[i], err); - - continue; - } - } -} +static const char * const nodes[] = { + "/host1x@50000000/dc@54200000", + "/host1x@50000000/dc@54240000", + "/external-memory-controller@7001b000", +}; int ft_board_setup(void *fdt, struct bd_info *bd) { ft_mac_address_setup(fdt); - ft_carveout_setup(fdt); + ft_carveout_setup(fdt, nodes, ARRAY_SIZE(nodes)); return 0; } From a0ba216ed420a8953f57f777256f310370b95338 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 3 Sep 2021 15:16:25 +0200 Subject: [PATCH 177/228] ARM: tegra: Copy memory-region-names property If multiple entries are present in the memory-region property, this new memory-region-names property can be used to specify names for each of them so that they can be more easily distinguished. Signed-off-by: Thierry Reding Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/mach-tegra/dt-setup.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index 894a6358a2..c11494722b 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -78,9 +78,11 @@ void ft_mac_address_setup(void *fdt) static int ft_copy_carveout(void *dst, const void *src, const char *node) { + const char *names = "memory-region-names"; struct fdt_memory carveout; unsigned int index = 0; - int err; + int err, offset, len; + const void *prop; while (true) { const char **compatibles = NULL; @@ -96,6 +98,8 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) if (err != -FDT_ERR_NOTFOUND) printf("failed to get carveout for %s: %d\n", node, err); + else + break; return err; } @@ -126,6 +130,31 @@ static int ft_copy_carveout(void *dst, const void *src, const char *node) index++; } + offset = fdt_path_offset(src, node); + if (offset < 0) { + debug("failed to find source offset for %s: %s\n", node, + fdt_strerror(err)); + return err; + } + + prop = fdt_getprop(src, offset, names, &len); + if (prop) { + offset = fdt_path_offset(dst, node); + if (offset < 0) { + debug("failed to find destination offset for %s: %s\n", + node, fdt_strerror(err)); + return err; + } + + err = fdt_setprop(dst, offset, "memory-region-names", prop, + len); + if (err < 0) { + debug("failed to copy \"%s\" property: %s\n", names, + fdt_strerror(err)); + return err; + } + } + return 0; } From 927e0eedfcd8f773fc89da1a750ea191aa94492c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 5 Oct 2021 13:51:38 -0400 Subject: [PATCH 178/228] CI: Update to LLVM-13 - Switch sources and CI scripts to install and use LLVM-13 - Update to latest "focal" tag. Signed-off-by: Tom Rini --- .azure-pipelines.yml | 4 ++-- .gitlab-ci.yml | 4 ++-- tools/docker/Dockerfile | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 53f86f5184..2ca146c0fd 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 macos_vm: macOS-10.15 - ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021 + ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -183,7 +183,7 @@ jobs: TEST_PY_BD: "sandbox" sandbox_clang: TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-12" + OVERRIDE: "-O clang-13" sandbox_spl: TEST_PY_BD: "sandbox_spl" TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5a3e2f0ceb..699ce991fb 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://source.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:focal-20210827-30Sep2021 +image: trini/u-boot-gitlab-ci-runner:focal-20210921-05Oct2021 # We run some tests in different order, to catch some failures quicker. stages: @@ -190,7 +190,7 @@ sandbox test.py: sandbox with clang test.py: variables: TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-12" + OVERRIDE: "-O clang-13" <<: *buildman_and_testpy_dfn sandbox_spl test.py: diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 92113dcb72..1a44423d77 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:focal-20210827 +FROM ubuntu:focal-20210921 MAINTAINER Tom Rini LABEL Description=" This image is for building U-Boot inside a container" @@ -12,7 +12,7 @@ ENV DEBIAN_FRONTEND=noninteractive # Add LLVM repository RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/* RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - -RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-12 main | tee /etc/apt/sources.list.d/llvm.list +RUN echo deb http://apt.llvm.org/focal/ llvm-toolchain-focal-13 main | tee /etc/apt/sources.list.d/llvm.list # Manually install the kernel.org "Crosstool" based toolchains for gcc-11.1.0 RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ @@ -39,7 +39,7 @@ RUN apt-get update && apt-get install -y \ binutils-dev \ bison \ build-essential \ - clang-12 \ + clang-13 \ coreutils \ cpio \ cppcheck \ From b04f64aa48eeaf099fe52c28c512f956690f5eec Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 5 Oct 2021 20:18:00 -0600 Subject: [PATCH 179/228] pytest: Shorten traceback length by default This produces a lot of code output which is not very helpful and is quite annoying to wade through. Use the short format by default. Signed-off-by: Simon Glass --- doc/develop/py_testing.rst | 7 +++++++ test/py/test.py | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst index 4f1e1f66e7..52238ca54d 100644 --- a/doc/develop/py_testing.rst +++ b/doc/develop/py_testing.rst @@ -103,6 +103,13 @@ will be written to `${build_dir}/test-log.html`. This is best viewed in a web browser, but may be read directly as plain text, perhaps with the aid of the `html2text` utility. +Controlling output +~~~~~~~~~~~~~~~~~~ + +By default a short backtrace is reported. If you would like a longer one, +pass ``--tb=long`` when running the test. See the pytest documentation for +more options. + Running tests in parallel ~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/test/py/test.py b/test/py/test.py index 285fda5425..95859a66e2 100755 --- a/test/py/test.py +++ b/test/py/test.py @@ -17,4 +17,9 @@ if __name__ == '__main__': # argv; py.test test_directory_name user-supplied-arguments args = [os.path.dirname(__file__) + '/tests'] args.extend(sys.argv) + + # Use short format by default + if not [arg for arg in args if '--tb=' in arg]: + args.append('--tb=short') + sys.exit(pytest.main(args)) From b9caab8b47ae6ad6a317a9ed05e90475248739d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Oct 2021 14:50:57 +0200 Subject: [PATCH 180/228] pci: Skip configuring PCI Rom Address for unsupported header types MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCI Rom Address is currently supported only for Normal (0x00) and Bridge (0x01) header types. Fix code accordingly. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_auto.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 08082460eb..288f7996c7 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -131,7 +131,8 @@ static void dm_pciauto_setup_device(struct udevice *dev, int bars_num, /* Configure the expansion ROM address */ dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); header_type &= 0x7f; - if (header_type != PCI_HEADER_TYPE_CARDBUS) { + if (header_type == PCI_HEADER_TYPE_NORMAL || + header_type == PCI_HEADER_TYPE_BRIDGE) { rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1; dm_pci_write_config32(dev, rom_addr, 0xfffffffe); From 63ae80dd98d4c0d1123317043cdf2596e724e43a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Oct 2021 14:50:58 +0200 Subject: [PATCH 181/228] pci: Skip configuring invalid P2P bridge devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Function dm_pci_hose_probe_bus() expects that bus is valid PCI device with Bridge header type (0x01). So add check before touching PCI config space to prevent misconfiguring some non-standard device. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci-uclass.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 044babee16..5da3515f5f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -627,6 +627,7 @@ int pci_generic_mmap_read_config( int dm_pci_hose_probe_bus(struct udevice *bus) { + u8 header_type; int sub_bus; int ret; int ea_pos; @@ -634,6 +635,14 @@ int dm_pci_hose_probe_bus(struct udevice *bus) debug("%s\n", __func__); + dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type); + header_type &= 0x7f; + if (header_type != PCI_HEADER_TYPE_BRIDGE) { + debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n", + __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type); + return log_msg_ret("probe", -EINVAL); + } + ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA); if (ea_pos) { dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8), From c7cd6f734b7cded1e1e1967c2374b08f344a6878 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Oct 2021 14:50:59 +0200 Subject: [PATCH 182/228] pci: Fix configuring BARs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_auto.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 288f7996c7..5af4ee6e56 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -19,7 +19,7 @@ #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 #endif -static void dm_pciauto_setup_device(struct udevice *dev, int bars_num, +static void dm_pciauto_setup_device(struct udevice *dev, struct pci_region *mem, struct pci_region *prefetch, struct pci_region *io) @@ -28,6 +28,7 @@ static void dm_pciauto_setup_device(struct udevice *dev, int bars_num, pci_size_t bar_size; u16 cmdstat = 0; int bar, bar_nr = 0; + int bars_num; u8 header_type; int rom_addr; pci_addr_t bar_value; @@ -39,6 +40,26 @@ static void dm_pciauto_setup_device(struct udevice *dev, int bars_num, cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; + dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + header_type &= 0x7f; + + switch (header_type) { + case PCI_HEADER_TYPE_NORMAL: + bars_num = 6; + break; + case PCI_HEADER_TYPE_BRIDGE: + bars_num = 2; + break; + case PCI_HEADER_TYPE_CARDBUS: + /* CardBus header does not have any BAR */ + bars_num = 0; + break; + default: + /* Skip configuring BARs for unknown header types */ + bars_num = 0; + break; + } + for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { int ret = 0; @@ -129,8 +150,6 @@ static void dm_pciauto_setup_device(struct udevice *dev, int bars_num, } /* Configure the expansion ROM address */ - dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); - header_type &= 0x7f; if (header_type == PCI_HEADER_TYPE_NORMAL || header_type == PCI_HEADER_TYPE_BRIDGE) { rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? @@ -343,7 +362,7 @@ int dm_pciauto_config_device(struct udevice *dev) debug("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dm_pci_get_bdf(dev))); - dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io); + dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); ret = dm_pci_hose_probe_bus(dev); if (ret < 0) @@ -356,7 +375,7 @@ int dm_pciauto_config_device(struct udevice *dev) * just do a minimal setup of the bridge, * let the OS take care of the rest */ - dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io); + dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dm_pci_get_bdf(dev))); @@ -388,7 +407,7 @@ int dm_pciauto_config_device(struct udevice *dev) /* fall through */ default: - dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io); + dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io); break; } From e6335d3eaafc60b74bd05761b2bf0e57ad429aa7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Oct 2021 14:51:00 +0200 Subject: [PATCH 183/228] pci: Fix showing bars MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Header type is 7-bit number so properly clear upper 8th bit which indicates multifunction device. And do not try to show bars for unsupported header types. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- cmd/pci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cmd/pci.c b/cmd/pci.c index cfabdc0f30..4a82854db7 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -71,10 +71,15 @@ static int pci_bar_show(struct udevice *dev) int prefetchable; dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + header_type &= 0x7f; if (header_type == PCI_HEADER_TYPE_CARDBUS) { printf("CardBus doesn't support BARs\n"); return -ENOSYS; + } else if (header_type != PCI_HEADER_TYPE_NORMAL && + header_type != PCI_HEADER_TYPE_BRIDGE) { + printf("unknown header type\n"); + return -ENOSYS; } bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2; From 43dad07cd45dba129487a8dc55de9f4f850ae7d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Oct 2021 14:51:01 +0200 Subject: [PATCH 184/228] pci: Fix showing registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Header type is 7-bit number so use all 7 bits when detecting header type and not only 2 bits. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- cmd/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/pci.c b/cmd/pci.c index 4a82854db7..3b1863f139 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -239,7 +239,7 @@ static void pci_header_show(struct udevice *dev) pci_class_str(class)); pci_show_regs(dev, regs_rest); - switch (header_type & 0x03) { + switch (header_type & 0x7f) { case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ pci_show_regs(dev, regs_normal); break; From c3aea6870595bfb41c8ea0108874e3ee3ee42407 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Oct 2021 17:01:24 +0200 Subject: [PATCH 185/228] pci: Fix printf format for regions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct printf format for unsigned long long is %llx and not %llxx. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci_auto_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c index c0a53dcc92..2f4aff0104 100644 --- a/drivers/pci/pci_auto_common.c +++ b/drivers/pci/pci_auto_common.c @@ -74,7 +74,7 @@ static void pciauto_show_region(const char *name, struct pci_region *region) { pciauto_region_init(region); debug("PCI Autoconfig: Bus %s region: [%llx-%llx],\n" - "\t\tPhysical Memory [%llx-%llxx]\n", name, + "\t\tPhysical Memory [%llx-%llx]\n", name, (unsigned long long)region->bus_start, (unsigned long long)(region->bus_start + region->size - 1), (unsigned long long)region->phys_start, From 35839eda8b17f85a94e8f83a681079ac2d30413f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 8 Oct 2021 09:15:23 -0600 Subject: [PATCH 186/228] pytest: Show a message when sandbox crashes When a test hands on a real board there is no way on the console to obtain any information about why it hung. With sandbox we can actually find out that it died and get a signal or exit code. Add this to make it easier to figure out what happened. So instead of: test/py/u_boot_spawn.py:171: in expect c = os.read(self.fd, 1024).decode(errors='replace') E OSError: [Errno 5] Input/output error We get: test/py/u_boot_spawn.py:171: in expect c = os.read(self.fd, 1024).decode(errors='replace') E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV) Signed-off-by: Simon Glass --- doc/develop/py_testing.rst | 8 ++++++ test/py/u_boot_spawn.py | 58 +++++++++++++++++++++++++++++--------- 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst index 52238ca54d..06f919609b 100644 --- a/doc/develop/py_testing.rst +++ b/doc/develop/py_testing.rst @@ -103,6 +103,14 @@ will be written to `${build_dir}/test-log.html`. This is best viewed in a web browser, but may be read directly as plain text, perhaps with the aid of the `html2text` utility. +If sandbox crashes (e.g. with a segfault) you will see message like this:: + + + test/py/u_boot_spawn.py:171: in expect + c = os.read(self.fd, 1024).decode(errors='replace') + E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV) + + Controlling output ~~~~~~~~~~~~~~~~~~ diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py index 6991b78cca..e34cb217e8 100644 --- a/test/py/u_boot_spawn.py +++ b/test/py/u_boot_spawn.py @@ -35,6 +35,8 @@ class Spawn(object): """ self.waited = False + self.exit_code = 0 + self.exit_info = '' self.buf = '' self.output = '' self.logfile_read = None @@ -80,6 +82,34 @@ class Spawn(object): os.kill(self.pid, sig) + def checkalive(self): + """Determine whether the child process is still running. + + Returns: + tuple: + True if process is alive, else False + 0 if process is alive, else exit code of process + string describing what happened ('' or 'status/signal n') + """ + + if self.waited: + return False, self.exit_code, self.exit_info + + w = os.waitpid(self.pid, os.WNOHANG) + if w[0] == 0: + return True, 0, 'running' + status = w[1] + + if os.WIFEXITED(status): + self.exit_code = os.WEXITSTATUS(status) + self.exit_info = 'status %d' % self.exit_code + elif os.WIFSIGNALED(status): + signum = os.WTERMSIG(status) + self.exit_code = -signum + self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum)) + self.waited = True + return False, self.exit_code, self.exit_info + def isalive(self): """Determine whether the child process is still running. @@ -89,16 +119,7 @@ class Spawn(object): Returns: Boolean indicating whether process is alive. """ - - if self.waited: - return False - - w = os.waitpid(self.pid, os.WNOHANG) - if w[0] == 0: - return True - - self.waited = True - return False + return self.checkalive()[0] def send(self, data): """Send data to the sub-process's stdin. @@ -168,9 +189,20 @@ class Spawn(object): events = self.poll.poll(poll_maxwait) if not events: raise Timeout() - c = os.read(self.fd, 1024).decode(errors='replace') - if not c: - raise EOFError() + try: + c = os.read(self.fd, 1024).decode(errors='replace') + except OSError as err: + # With sandbox, try to detect when U-Boot exits when it + # shouldn't and explain why. This is much more friendly than + # just dying with an I/O error + if err.errno == 5: # Input/output error + alive, exit_code, info = self.checkalive() + if alive: + raise + else: + raise ValueError('U-Boot exited with %s' % info) + else: + raise if self.logfile_read: self.logfile_read.write(c) self.buf += c From 35b2b5f04c71efb73ec0f1a01535542e4b602e15 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Tue, 12 Oct 2021 08:50:38 +0200 Subject: [PATCH 187/228] board/km: update MAINTAINERS files Update the e-mail addresses and person responsible. Signed-off-by: Holger Brunck CC: Aleksandar Gerasimovski CC: Rainer Boschung --- board/keymile/km83xx/MAINTAINERS | 2 +- board/keymile/km_arm/MAINTAINERS | 2 +- board/keymile/pg-wcom-ls102xa/MAINTAINERS | 5 ++--- board/keymile/secu1/MAINTAINERS | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 9268719a74..9fd5a8500d 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,5 +1,5 @@ KM83XX BOARD -M: Holger Brunck +M: Holger Brunck M: Heiko Schocher S: Maintained F: board/keymile/km83xx/ diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS index 8da58da962..bc6858be13 100644 --- a/board/keymile/km_arm/MAINTAINERS +++ b/board/keymile/km_arm/MAINTAINERS @@ -1,5 +1,5 @@ KM_ARM BOARD -M: Valentin Longchamp +M: Holger Brunck S: Maintained F: board/keymile/km_arm/ F: include/configs/km_kirkwood.h diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS index 26b202316c..966c88b681 100644 --- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -1,7 +1,6 @@ Hitachi Power Grids LS102XA BOARD -M: Aleksandar Gerasimovski -M: Rainer Boschung -M: Matteo Ghidoni +M: Aleksandar Gerasimovski +M: Rainer Boschung S: Maintained F: board/keymile/pg-wcom-ls102xa/ F: include/configs/km/pg-wcom-ls102xa.h diff --git a/board/keymile/secu1/MAINTAINERS b/board/keymile/secu1/MAINTAINERS index 3e40eef3cc..833b3fdeab 100644 --- a/board/keymile/secu1/MAINTAINERS +++ b/board/keymile/secu1/MAINTAINERS @@ -1,5 +1,5 @@ Hitachi Power Grids SECU1 BOARD -M: Holger Brunck +M: Holger Brunck S: Maintained F: include/configs/socfpga_arria5_secu1.h F: configs/socfpga_secu1_defconfig From ff07cc9ed106982727935ff0d6369e4da0fec6a9 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:59:50 +0200 Subject: [PATCH 188/228] scripts: remove some configs in config_whitelist.txt Remove some config finishing by _ badly added by scripts/build-whitelist.sh when joker is used in comments. for example: doc/uImage.FIT/command_syntax_extensions.txt: ... #ifdef CONFIG_OF_* | ... cmd/nvedit.c:# error Define one of CONFIG_ENV_IS_IN_{EEPROM| \ FLASH|MMC|FAT|EXT4|\ Remove also configs only used in comments: - CONFIG_BOOGER in include/linux/kconfig.h - CONFIG_COMMANDS - CONFIG_INIT_IGNORE_ERROR - CONFIG_REG_* - CONFIG_HOTPLUG : drivers/watchdog/omap_wdt.c:18 Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass Tested-by: Simon Glass --- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 8 ++++---- include/configs/M5235EVB.h | 2 +- include/configs/dra7xx_evm.h | 1 - scripts/config_whitelist.txt | 14 -------------- 4 files changed, 5 insertions(+), 20 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index ea2f113f98..df392a2714 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -11,7 +11,7 @@ #include -/* CONFIG_REG_0 */ +/* CFG REG_0 */ #define CFG_REG_0_OFFSET 0xC #define CFG_REG_ROM_READ_SHIFT 1 #define CFG_REG_ROM_READ_MASK (1 << 1) @@ -22,18 +22,18 @@ #define CFG_REG_ROM_READ_START (1 << 1) #define CFG_REG_ROM_READ_END (0 << 1) -/* CONFIG_REG_2 */ +/* CFG REG_2 */ #define CFG_REG_2_OFFSET 0x14 #define CFG_REG_REFCLK_PERIOD_SHIFT 0 #define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) #define CFG_REG_REFCLK_PERIOD 0x2EF -/* CONFIG_REG_8 */ +/* CFG REG_8 */ #define CFG_REG_8_OFFSET 0x2C #define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA #define CFG_IODELAY_LOCK_KEY 0x0000AAAB -/* CONFIG_REG_3/4 */ +/* CFG REG_3/4 */ #define CFG_REG_3_OFFSET 0x18 #define CFG_REG_4_OFFSET 0x1C #define CFG_REG_DLY_CNT_SHIFT 16 diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index f983281cc1..b37c915538 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -54,7 +54,7 @@ #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ #define CONFIG_BOOTFILE "u-boot.bin" #ifdef CONFIG_MCFFEC # define CONFIG_IPADDR 192.162.1.2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index c54f375689..900c5fd233 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -103,7 +103,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ -/* #define CONFIG_INIT_IGNORE_ERROR */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3a6865dc70..566f31a76e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -71,10 +71,8 @@ CONFIG_BOARD_IS_OPENRD_ULTIMATE CONFIG_BOARD_NAME CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_SIZE_LIMIT -CONFIG_BOOGER CONFIG_BOOTFILE CONFIG_BOOTMODE -CONFIG_BOOTP_ CONFIG_BOOTP_BOOTFILESIZE CONFIG_BOOTP_DHCP_REQUEST_DELAY CONFIG_BOOTP_ID_CACHE_SIZE @@ -140,7 +138,6 @@ CONFIG_CM_REMAP CONFIG_CM_SPD_DETECT CONFIG_CM_TCRAM CONFIG_COLDFIRE -CONFIG_COMMANDS CONFIG_COMMON_BOOT CONFIG_COMPAT CONFIG_CONS_EXTC_PINSEL @@ -220,7 +217,6 @@ CONFIG_DNET_AUTONEG_TIMEOUT CONFIG_DP_DDR_CTRL CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR CONFIG_DP_DDR_NUM_CTRLS -CONFIG_DRAM_TIMINGS_ CONFIG_DRIVER_DM9000 CONFIG_DSP_CLUSTER_START CONFIG_DWCDDR21MCTL @@ -260,7 +256,6 @@ CONFIG_ENV_CALLBACK_LIST_STATIC CONFIG_ENV_FLAGS_LIST_DEFAULT CONFIG_ENV_FLAGS_LIST_STATIC CONFIG_ENV_IS_EMBEDDED -CONFIG_ENV_IS_IN_ CONFIG_ENV_MAX_ENTRIES CONFIG_ENV_MIN_ENTRIES CONFIG_ENV_OFFSET_OOB @@ -450,7 +445,6 @@ CONFIG_HIKEY_GPIO CONFIG_HITACHI_SX14 CONFIG_HOSTNAME CONFIG_HOST_MAX_DEVICES -CONFIG_HOTPLUG CONFIG_HPS_ALTERAGRP_DBGATCLK CONFIG_HPS_ALTERAGRP_MAINCLK CONFIG_HPS_ALTERAGRP_MPUCLK @@ -624,7 +618,6 @@ CONFIG_IMX6_PWM_PER_CLK CONFIG_IMX_HDMI CONFIG_IMX_VIDEO_SKIP CONFIG_INETSPACE_V2 -CONFIG_INIT_IGNORE_ERROR CONFIG_INI_ALLOW_MULTILINE CONFIG_INI_CASE_INSENSITIVE CONFIG_INI_MAX_LINE @@ -888,7 +881,6 @@ CONFIG_NUM_DSP_CPUS CONFIG_NUM_PAMU CONFIG_ODROID_REV_AIN CONFIG_OFF_PADCONF -CONFIG_OF_ CONFIG_ORIGEN CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE @@ -1009,10 +1001,6 @@ CONFIG_RD_LVL CONFIG_REALMODE_DEBUG CONFIG_RED_LED CONFIG_REG -CONFIG_REG_0 -CONFIG_REG_2 -CONFIG_REG_3 -CONFIG_REG_8 CONFIG_REMAKE_ELF CONFIG_REQ CONFIG_RESERVED_01_BASE @@ -1163,7 +1151,6 @@ CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_IDLE_VAL CONFIG_SPI_N25Q256A_RESET -CONFIG_SPL_ CONFIG_SPL_ATMEL_SIZE CONFIG_SPL_BOARD_LOAD_IMAGE CONFIG_SPL_BOOTROM_SAVE @@ -2260,7 +2247,6 @@ CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_SIZE CONFIG_SYS_MMC_U_BOOT_START -CONFIG_SYS_MONITOR_ CONFIG_SYS_MONITOR_BASE CONFIG_SYS_MONITOR_LEN CONFIG_SYS_MONITOR_SEC From e7421b0e4135009f5ffd30670ed8f4b3e880040d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:59:51 +0200 Subject: [PATCH 189/228] am33x: Remove unused define CONFIG_MUSB_HOST This define was left over from a previous revision, and was never used. Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- include/configs/am335x_sl50.h | 7 ------- scripts/config_whitelist.txt | 1 - 2 files changed, 8 deletions(-) diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index dff946801c..7fbf421149 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -62,13 +62,6 @@ /* Bootcount using the RTC block */ #define CONFIG_SYS_BOOTCOUNT_BE -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) -/* Remove other SPL modes. */ -/* disable host part of MUSB in SPL */ -#undef CONFIG_MUSB_HOST -/* disable EFI partitions and partition UUID support */ -#endif - /* Network. */ #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 566f31a76e..5c3800a4e3 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -811,7 +811,6 @@ CONFIG_MTD_UBI_DEBUG_PARANOID CONFIG_MTD_UBI_GLUEBI CONFIG_MTD_UBI_MODULE CONFIG_MULTI_CS -CONFIG_MUSB_HOST CONFIG_MVGBE_PORTS CONFIG_MVMFP_V2 CONFIG_MVS From 155fb86e2c1435aa3887a1b2000573a4ceea9975 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:59:52 +0200 Subject: [PATCH 190/228] Remove unused CONFIG_NO_RELOCATION Remove the latest reference of CONFIG_NO_RELOCATION in code Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- include/configs/thunderx_88xx.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 1ce0347300..600689843b 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -58,7 +58,6 @@ /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 64 /* max command args */ -#define CONFIG_NO_RELOCATION 1 #define PLL_REF_CLK 50000000 /* 50 MHz */ #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5c3800a4e3..63da9777b8 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -872,7 +872,6 @@ CONFIG_NON_SECURE CONFIG_NORBOOT CONFIG_NORFLASH_PS32BIT CONFIG_NO_ETH -CONFIG_NO_RELOCATION CONFIG_NO_WAIT CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NS8382X From 0d76e4ec8dc121471127f68a9795443a02251116 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:59:53 +0200 Subject: [PATCH 191/228] Remove unused CONFIG_SYS_FLASH_AMD_CHECK_DQ7 Remove the latest reference of CONFIG_SYS_FLASH_AMD_CHECK_DQ7 in code Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- include/configs/P2041RDB.h | 1 - include/configs/corenet_ds.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 3 deletions(-) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 21e56d68f5..198b698f21 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -203,7 +203,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_NAND_FSL_ELBC */ #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} #define CONFIG_HWCONFIG diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7fd1ad14b5..8819935de1 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -205,7 +205,6 @@ #endif /* CONFIG_NAND_FSL_ELBC */ #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_HWCONFIG diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 63da9777b8..ca7ca822cb 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1637,7 +1637,6 @@ CONFIG_SYS_FLASH1 CONFIG_SYS_FLASH1_BASE_PHYS CONFIG_SYS_FLASH1_BASE_PHYS_EARLY CONFIG_SYS_FLASHBOOT -CONFIG_SYS_FLASH_AMD_CHECK_DQ7 CONFIG_SYS_FLASH_AUTOPROTECT_LIST CONFIG_SYS_FLASH_BANKS_LIST CONFIG_SYS_FLASH_BANKS_SIZES From 42d32c35524b79c8cfd8f5dd568bd8d55417c84e Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 4 Oct 2021 11:59:54 +0200 Subject: [PATCH 192/228] Remove unused CONFIG_CONS_NONE Remove the latest reference of CONFIG_CONS_NONE in code Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- include/configs/MPC8560ADS.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 3a9ea03292..dcd538fdf1 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -191,7 +191,6 @@ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ca7ca822cb..21c0e70e02 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -142,7 +142,6 @@ CONFIG_COMMON_BOOT CONFIG_COMPAT CONFIG_CONS_EXTC_PINSEL CONFIG_CONS_EXTC_RATE -CONFIG_CONS_NONE CONFIG_CONS_ON_SCC CONFIG_CONS_SCIF0 CONFIG_CONS_SCIF1 From ef120e0b30d05ca444753e995bcfc4e4333261f1 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 5 Aug 2021 11:48:47 -0500 Subject: [PATCH 193/228] rockchip: px30: add support for setting cpll clock Starting with commit 92f1e9a4b31c ("clk: Detect failure to set defaults") the clk driver for the PX30 for the Odroid Go Advance would no longer probe correctly, because setting the cpll and gpu clocks are not supported with the clk_px30 U-Boot driver. This adds support for setting the cpll clock to the clk_px30 driver. Another patch will update the U-Boot specific device-tree to remove the GPU clock which is not used by U-Boot. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_px30.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index 617ce0dce5..ea874e3f4b 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1291,6 +1291,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) case PLL_NPLL: ret = px30_clk_set_pll_rate(priv, NPLL, rate); break; + case PLL_CPLL: + ret = px30_clk_set_pll_rate(priv, CPLL, rate); + break; case ARMCLK: ret = px30_armclk_set_clk(priv, rate); break; From 8d43e2412ade9b833b489d37b240e520405bcdb8 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 5 Aug 2021 11:48:48 -0500 Subject: [PATCH 194/228] rockchip: board: remove SCLK_GPU from U-Boot DT Starting with commit 92f1e9a4b31c ("clk: Detect failure to set defaults") the clk driver for the PX30 would fail to probe for the Odroid Go Advance. This patch is to remove the clock for the GPU from the U-Boot specific devicetree, as that clock is not supported by the U-Boot clk_px30 driver. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 741e8dd935..72f0ede4cf 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -18,8 +18,18 @@ }; }; +/* U-Boot clk driver for px30 cannot set GPU_CLK */ &cru { u-boot,dm-pre-reloc; + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <17000000>; }; &dmc { From 63e13530fc6fb0169ee70abf5cfd5c272238609d Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 12 Aug 2021 10:11:32 +0100 Subject: [PATCH 195/228] rockchip: rk33xx: Drop ROCKCHIP_USB2_PHY on boards without it The 64 bit rk33xx chips don't have the ROCKCHIP_USB2_PHY IP so drop the configs as they were likely copied over from other boards during enablement. Signed-off-by: Peter Robinson Reviewed-by: Kever Yang --- configs/lion-rk3368_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/roc-pc-mezzanine-rk3399_defconfig | 1 - configs/roc-pc-rk3399_defconfig | 1 - configs/rock-pi-n10-rk3399pro_defconfig | 1 - 5 files changed, 5 deletions(-) diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index e214cf5707..7f62811909 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -96,7 +96,6 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC2=y -CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index d86faf196c..f31668c5c2 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -53,7 +53,6 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y -CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 199624fe0d..ca2fb9e13f 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -71,7 +71,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index bc124c8fec..de35a62da9 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -68,7 +68,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 0b89ae9a8a..bd8b1201ef 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -62,7 +62,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_USB_KEYBOARD=y # CONFIG_USB_KEYBOARD_FN_KEYS is not set CONFIG_USB_GADGET=y From 734dcdcbf27dab0f43c0a8946759db98d9147d26 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 20 Aug 2021 19:27:58 +0200 Subject: [PATCH 196/228] doc: rockchip: sort rockchip support list for rk3188 In the list of mainline U-boot supported Rockchip boards rk3188 is placed below under the name rv3188. Give back it's original name and sort the list in alphabetical order. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index fbb9983988..8d75efc023 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -26,6 +26,8 @@ List of mainline supported rockchip boards: - Kylin (kylin_rk3036) * rk3128 - Rockchip Evb-RK3128 (evb-rk3128) +* rk3188 + - Radxa Rock (rock) * rk3229 - Rockchip Evb-RK3229 (evb-rk3229) * rk3288 @@ -75,8 +77,6 @@ List of mainline supported rockchip boards: * rv1108 - Rockchip Evb-rv1108 (evb-rv1108) - Elgin-R1 (elgin-rv1108) -* rv3188 - - Radxa Rock (rock) Building -------- From 3ad88ecc6bede44b8bf22d62f290be4cb0962e18 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 20 Aug 2021 19:27:59 +0200 Subject: [PATCH 197/228] doc: rockchip: write all brand names with a capital Brand names are supposed to be written with a capital, so change them all. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- doc/board/rockchip/rockchip.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 8d75efc023..144cb98ef9 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -16,10 +16,10 @@ Rockchip boards Rockchip is SoC solutions provider for tablets & PCs, streaming media TV boxes, AI audio & vision, IoT hardware. -A wide range of Rockchip SoCs with associated boardsare supported in +A wide range of Rockchip SoCs with associated boards are supported in mainline U-Boot. -List of mainline supported rockchip boards: +List of mainline supported Rockchip boards: * rk3036 - Rockchip Evb-RK3036 (evb-rk3036) @@ -93,7 +93,7 @@ To build TF-A:: make realclean make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 -Specify the PLAT= with desired rockchip platform to build TF-A for. +Specify the PLAT= with desired Rockchip platform to build TF-A for. U-Boot ^^^^^^ @@ -130,7 +130,7 @@ Flashing SD Card ^^^^^^^ -All rockchip platforms, except rk3128 (which doesn't use SPL) are now +All Rockchip platforms, except rk3128 (which doesn't use SPL) are now supporting single boot image using binman and pad_cat. To write an image that boots from an SD card (assumed to be /dev/sda):: @@ -141,7 +141,7 @@ To write an image that boots from an SD card (assumed to be /dev/sda):: eMMC ^^^^ -eMMC flash would probe on mmc0 in most of the rockchip platforms. +eMMC flash would probe on mmc0 in most of the Rockchip platforms. Create GPT partition layout as defined in configurations:: @@ -164,7 +164,7 @@ Program the flash:: sudo fastboot -i 0x2207 flash loader1 idbloader.img sudo fastboot -i 0x2207 flash loader2 u-boot.itb -Note: for rockchip 32-bit platforms the U-Boot proper image +Note: for Rockchip 32-bit platforms the U-Boot proper image is u-boot-dtb.img SPI @@ -227,8 +227,8 @@ Note: TODO ---- -- Add rockchip idbloader image building -- Add rockchip TPL image building +- Add Rockchip idbloader image building +- Add Rockchip TPL image building - Document SPI flash boot - Add missing SoC's with it boards list From 193ab22797247bd286dabfb857888bee8810a68a Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 20 Aug 2021 20:46:58 -0500 Subject: [PATCH 198/228] rockchip: px30: sync serial flash controller bindings with mainline The devicetree submitted and approved for the mainline linux kernel is slightly different than the one present here. This syncs both devicetrees (for the Rockchip SFC node at least) present on the PX30 and the Odroid Go Advance. Changes include renaming the flash node, reordering the values in the SFC node for the rk3326-odroid-go2, changing the name of the cs pinctrl node to cs0, and updating the u-boot specific tree to utilize the new flash node value. Signed-off-by: Chris Morgan Reviewed-by: Kever Yang --- arch/arm/dts/px30.dtsi | 4 ++-- arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 2 +- arch/arm/dts/rk3326-odroid-go2.dts | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index aaa8ae2235..ef706486dc 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -967,7 +967,7 @@ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; clock-names = "clk_sfc", "hclk_sfc"; pinctrl-names = "default"; - pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; power-domains = <&power PX30_PD_MMC_NAND>; status = "disabled"; }; @@ -1953,7 +1953,7 @@ <1 RK_PA1 3 &pcfg_pull_none>; }; - sfc_cs: sfc-cs { + sfc_cs0: sfc-cs0 { rockchip,pins = <1 RK_PA4 3 &pcfg_pull_none>; }; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index 72f0ede4cf..bffaa3edf3 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -80,7 +80,7 @@ u-boot,dm-pre-reloc; }; -&spi_flash { +&{/sfc@ff3a0000/flash@0} { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts index 6f91f5040b..4e3dceecbe 100644 --- a/arch/arm/dts/rk3326-odroid-go2.dts +++ b/arch/arm/dts/rk3326-odroid-go2.dts @@ -618,18 +618,18 @@ }; &sfc { + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; status = "okay"; - spi_flash: xt25f128b@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <108000000>; spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; + spi-tx-bus-width = <1>; }; }; From 51f29239b75208200db2cb2a5ef9924725423374 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 17 Sep 2021 21:14:58 +0800 Subject: [PATCH 199/228] spi: rockchip_sfc: Implement set_speed logic Set clock related processing into set_speed logic. And Optimize printing format. Tested-by: Chris Morgan Signed-off-by: Jon Lin Reviewed-by: Kever Yang --- drivers/spi/rockchip_sfc.c | 82 ++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 43 deletions(-) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 4e2b861f22..94222df5ce 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -116,6 +116,7 @@ /* Master trigger */ #define SFC_DMA_TRIGGER 0x80 +#define SFC_DMA_TRIGGER_START 1 /* Src or Dst addr for master */ #define SFC_DMA_ADDR 0x84 @@ -163,14 +164,12 @@ #define SFC_DMA_TRANS_THRETHOLD (0x40) /* Maximum clock values from datasheet suggest keeping clock value under - * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver - * has a minimum of 10MHz and a default of 80MHz which seems reasonable. + * 150MHz. No minimum or average value is suggested. */ -#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) -#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) -#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) +#define SFC_MAX_SPEED (150 * 1000 * 1000) struct rockchip_sfc { + struct udevice *dev; void __iomem *regbase; struct clk hclk; struct clk clk; @@ -197,8 +196,6 @@ static int rockchip_sfc_reset(struct rockchip_sfc *sfc) /* Still need to clear the masked interrupt from RISR */ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); - debug("reset\n"); - return err; } @@ -261,15 +258,11 @@ static int rockchip_sfc_probe(struct udevice *bus) #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&sfc->hclk); if (ret) - debug("Enable ahb clock fail %s: %d\n", bus->name, ret); + dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); ret = clk_enable(&sfc->clk); if (ret) - debug("Enable clock fail for %s: %d\n", bus->name, ret); - - ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ); - if (ret) - debug("Could not set sfc clock for %s: %d\n", bus->name, ret); + dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); #endif ret = rockchip_sfc_init(sfc); @@ -278,7 +271,8 @@ static int rockchip_sfc_probe(struct udevice *bus) sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); sfc->version = rockchip_sfc_get_version(sfc); - sfc->speed = SFC_DEFAULT_SPEED_HZ; + sfc->max_freq = SFC_MAX_SPEED; + sfc->dev = bus; return 0; @@ -411,11 +405,11 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; cmd |= plat->cs << SFC_CMD_CS_SHIFT; - debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", - op->addr.nbytes, op->addr.buswidth, - op->dummy.nbytes, op->dummy.buswidth); - debug("ctrl=%x cmd=%x addr=%llx len=%x\n", - ctrl, cmd, op->addr.val, len); + dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", + op->addr.nbytes, op->addr.buswidth, + op->dummy.nbytes, op->dummy.buswidth); + dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", + ctrl, cmd, op->addr.val, len); writel(ctrl, sfc->regbase + SFC_CTRL); writel(cmd, sfc->regbase + SFC_CMD); @@ -492,7 +486,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d { writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); - writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); + writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); return len; } @@ -500,7 +494,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, const struct spi_mem_op *op, u32 len) { - debug("xfer_poll len=%x\n", len); + dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); if (op->data.dir == SPI_MEM_DATA_OUT) return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); @@ -516,7 +510,7 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, void *dma_buf; int ret; - debug("xfer_dma len=%x\n", len); + dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); if (op->data.dir == SPI_MEM_DATA_OUT) { dma_buf = (void *)op->data.buf.out; @@ -564,33 +558,16 @@ static int rockchip_sfc_exec_op(struct spi_slave *mem, u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); int ret; -#if CONFIG_IS_ENABLED(CLK) - if (unlikely(mem->max_hz != sfc->speed)) { - ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ, - (uint)SFC_MAX_SPEED_HZ)); - if (ret < 0) { - printf("set_freq=%dHz fail, check if it's the cru support level\n", - mem->max_hz); - return ret; - } - - sfc->max_freq = mem->max_hz; - sfc->speed = mem->max_hz; - debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed); - } -#endif - rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); - rockchip_sfc_xfer_setup(sfc, mem, op, len); if (len) { - if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD) + if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) ret = rockchip_sfc_xfer_data_dma(sfc, op, len); else ret = rockchip_sfc_xfer_data_poll(sfc, op, len); if (ret != len) { - printf("xfer data failed ret %d dir %d\n", ret, op->data.dir); + dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); return -EIO; } @@ -604,13 +581,32 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); + return 0; } static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) { - /* We set up speed later for each transmission. - */ + struct rockchip_sfc *sfc = dev_get_plat(bus); + + if (speed > sfc->max_freq) + speed = sfc->max_freq; + + if (speed == sfc->speed) + return 0; + +#if CONFIG_IS_ENABLED(CLK) + int ret = clk_set_rate(&sfc->clk, speed); + + if (ret < 0) { + dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", + speed); + return ret; + } + sfc->speed = speed; +#else + dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); +#endif return 0; } From 24c627b57a090b141a3088208e3f70b6f28dc3d8 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Fri, 17 Sep 2021 21:14:59 +0800 Subject: [PATCH 200/228] spi: rockchip_sfc: Using read_poll Using read_poll logic. Tested-by: Chris Morgan Signed-off-by: Jon Lin Reviewed-by: Kever Yang --- drivers/spi/rockchip_sfc.c | 75 ++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 36 deletions(-) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 94222df5ce..e098addddc 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -285,33 +285,38 @@ err_init: return ret; } -static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr) +static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) { - u32 fsr = readl(sfc->regbase + SFC_FSR); - int level; + int ret = 0; + u32 status; - if (wr) - level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; - else - level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; + ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, + status & SFC_FSR_TXLV_MASK, + timeout_us); + if (ret) { + dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); - return level; -} - -static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout) -{ - unsigned long tbase = get_timer(0); - int level; - - while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) { - if (get_timer(tbase) > timeout) { - debug("%s fifo timeout\n", wr ? "write" : "read"); - return -ETIMEDOUT; - } - udelay(1); + return -ETIMEDOUT; } - return level; + return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; +} + +static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) +{ + int ret = 0; + u32 status; + + ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, + status & SFC_FSR_RXLV_MASK, + timeout_us); + if (ret) { + dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); + + return -ETIMEDOUT; + } + + return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; } static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) @@ -429,7 +434,7 @@ static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int dwords = len >> 2; while (dwords) { - tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); + tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); if (tx_level < 0) return tx_level; write_words = min_t(u32, tx_level, dwords); @@ -440,7 +445,7 @@ static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int /* write the rest non word aligned bytes */ if (bytes) { - tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000); + tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); if (tx_level < 0) return tx_level; memcpy(&tmp, buf, bytes); @@ -461,7 +466,7 @@ static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) /* word aligned access only */ dwords = len >> 2; while (dwords) { - rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); + rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); if (rx_level < 0) return rx_level; read_words = min_t(u32, rx_level, dwords); @@ -472,7 +477,7 @@ static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) /* read the rest non word aligned bytes */ if (bytes) { - rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000); + rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); if (rx_level < 0) return rx_level; tmp = readl(sfc->regbase + SFC_DATA); @@ -533,19 +538,17 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) { - unsigned long tbase = get_timer(0); int ret = 0; - u32 timeout = timeout_us; + u32 status; - while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) { - if (get_timer(tbase) > timeout) { - printf("wait sfc idle timeout\n"); - rockchip_sfc_reset(sfc); + ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, + !(status & SFC_SR_IS_BUSY), + timeout_us); + if (ret) { + dev_err(sfc->dev, "wait sfc idle timeout\n"); + rockchip_sfc_reset(sfc); - return -ETIMEDOUT; - } - - udelay(1); + ret = -EIO; } return ret; From f2cdd44adb9f06f455185b4882cfd91e8d75d58a Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 12 Oct 2021 16:43:00 +0800 Subject: [PATCH 201/228] clk: rockchip: rk3568: update clks fix up ppll init freq. support tclk_emmc. add freq (26M) for mmc device. fix up the sfc clk rate unit error. Change in V2: remove change id. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 +- drivers/clk/rockchip/clk_rk3568.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 6c59033f03..399f19ad21 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -14,7 +14,7 @@ #define APLL_HZ (816 * MHz) #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (1000 * MHz) -#define PPLL_HZ (100 * MHz) +#define PPLL_HZ (200 * MHz) /* RK3568 pll id */ enum rk3568_pll_id { diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 553c6c0daf..d5e45e7602 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1441,6 +1441,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, switch (rate) { case OSC_HZ: + case 26 * MHz: src_clk = CLK_SDMMC_SEL_24M; break; case 400 * MHz: @@ -1507,7 +1508,7 @@ static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv) case SCLK_SFC_SEL_125M: return 125 * MHz; case SCLK_SFC_SEL_150M: - return 150 * KHz; + return 150 * MHz; default: return -ENOENT; } @@ -1534,7 +1535,7 @@ static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) case 125 * MHz: src_clk = SCLK_SFC_SEL_125M; break; - case 150 * KHz: + case 150 * MHz: src_clk = SCLK_SFC_SEL_150M; break; default: @@ -2406,6 +2407,9 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case BCLK_EMMC: rate = rk3568_emmc_get_bclk(priv); break; + case TCLK_EMMC: + rate = OSC_HZ; + break; #ifndef CONFIG_SPL_BUILD case ACLK_VOP: rate = rk3568_aclk_vop_get_clk(priv); @@ -2582,6 +2586,9 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case BCLK_EMMC: ret = rk3568_emmc_set_bclk(priv, rate); break; + case TCLK_EMMC: + ret = OSC_HZ; + break; #ifndef CONFIG_SPL_BUILD case ACLK_VOP: ret = rk3568_aclk_vop_set_clk(priv, rate); From 022f552704b6467966e4fad39c85a6aca9204c94 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Fri, 15 Oct 2021 16:41:27 +0800 Subject: [PATCH 202/228] mmc: rockchip_sdhci: enable strobe line for HS400 The default configuration of rk3399 EMMC PHY does not enable the strobe line, and EMMC controller will got data transmission error at HS400 mode. Signed-off-by: Yifeng Zhao Reviewed-by: Kever Yang --- drivers/mmc/rockchip_sdhci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 1ac00587d4..278473899c 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -143,6 +143,9 @@ static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); + /* REN Enable on STRB Line for HS400 */ + writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]); + read_poll_timeout(readl, &phy->emmcphy_status, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1, 5000); } From 92832045c54586e9dffa082ff8cd8c2ef6040757 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sat, 9 Oct 2021 15:27:32 +0200 Subject: [PATCH 203/228] Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation for moving this option to Kconfig, rename it to be consistent with other USB EHCI Kconfig options. Signed-off-by: Marek Behún --- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- drivers/usb/host/ehci-hcd.c | 2 +- include/configs/clearfog.h | 2 +- include/configs/controlcenterdc.h | 2 +- include/configs/crs3xx-98dx3236.h | 2 +- include/configs/db-88f6720.h | 2 +- include/configs/db-88f6820-amc.h | 2 +- include/configs/db-88f6820-gp.h | 2 +- include/configs/db-mv784mp-gp.h | 2 +- include/configs/db-xc3-24g4xg.h | 2 +- include/configs/ds414.h | 2 +- include/configs/helios4.h | 2 +- include/configs/mxs.h | 2 +- include/configs/nas220.h | 2 +- include/configs/tegra114-common.h | 2 +- include/configs/tegra124-common.h | 2 +- include/configs/tegra20-common.h | 2 +- include/configs/tegra210-common.h | 2 +- include/configs/tegra30-common.h | 2 +- include/configs/theadorable.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/turris_omnia.h | 2 +- include/configs/x530.h | 2 +- include/configs/zynq-common.h | 2 +- scripts/config_whitelist.txt | 2 +- 25 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 9002e26d75..f262d70b14 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -66,7 +66,7 @@ * USB/EHCI */ #ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ /* diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index ba75c27d04..e6355263cb 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -108,7 +108,7 @@ static struct descriptor { }, }; -#if defined(CONFIG_EHCI_IS_TDI) +#if defined(CONFIG_USB_EHCI_IS_TDI) #define ehci_is_TDI() (1) #else #define ehci_is_TDI() (0) diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 705217067b..a12e1582d6 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -19,7 +19,7 @@ */ /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_ENV_MIN_ENTRIES 128 diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index efd04c6fb8..12e9b8d06d 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -28,7 +28,7 @@ CONFIG_SYS_SCSI_MAX_LUN) /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 3feaa60eda..5300467a76 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 95f5cf0056..76c02f6656 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -20,7 +20,7 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 41216b8b4f..c5f0a1d2e0 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -11,7 +11,7 @@ */ /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 6bae063ae4..ecda30bab5 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -23,7 +23,7 @@ CONFIG_SYS_SCSI_MAX_LUN) /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 48471993b8..defe480613 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -21,7 +21,7 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 2c543fe12a..206afae590 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -13,7 +13,7 @@ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 58ecc5f699..85abed5d3b 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -25,7 +25,7 @@ #endif /* USB/EHCI/XHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/helios4.h b/include/configs/helios4.h index b5814ed55c..7ed70602d1 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -19,7 +19,7 @@ */ /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_ENV_MIN_ENTRIES 128 diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 45d1766482..d7d3e9d57f 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -124,7 +124,7 @@ /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI_MXS -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #endif #endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 16bbc9b049..f071ee6e1c 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -65,7 +65,7 @@ */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index f714c52bb5..06b687d556 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -58,7 +58,7 @@ #define CONFIG_SPL_STACK 0x800ffffc /* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 4a92954c9b..de78ac9924 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -60,7 +60,7 @@ #define CONFIG_SPL_STACK 0x800ffffc /* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 /* GPU needs setup */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 19934a4cf0..d2bed64ccd 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -78,7 +78,7 @@ * packets depending on the buffer address and size. */ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_SYS_NAND_SELF_INIT diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index b9e04147be..6c58ccc3d5 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -47,7 +47,7 @@ "ramdisk_addr_r=0x83200000\0" /* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 /* GPU needs setup */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 0ee13a226d..56b2671e43 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -55,7 +55,7 @@ #define CONFIG_SPL_STACK 0x800ffffc /* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 64b7f25092..073855592b 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -29,7 +29,7 @@ #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index f9a0b7d1aa..ede94e95f7 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -41,7 +41,7 @@ /* USB, USB storage, USB ethernet */ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* * Diagnostics diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 8646633ea4..4d8a7c37de 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -18,7 +18,7 @@ */ /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/x530.h b/include/configs/x530.h index d6aec6d7f2..23b1121460 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -46,7 +46,7 @@ /* Additional FS support/configuration */ /* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_EHCI_IS_TDI /* Environment in SPI NOR flash */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0c87f19ac3..f3c8512641 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -55,7 +55,7 @@ #endif #ifdef CONFIG_USB_EHCI_ZYNQ -# define CONFIG_EHCI_IS_TDI +# define CONFIG_USB_EHCI_IS_TDI # define DFU_DEFAULT_POLL_TIMEOUT 300 # define CONFIG_THOR_RESET_OFF diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 21c0e70e02..de592646b2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -241,7 +241,6 @@ CONFIG_EDB93XX_SDCS3 CONFIG_EFLASH_PROTSECTORS CONFIG_EHCI_DESC_BIG_ENDIAN CONFIG_EHCI_HCD_INIT_AFTER_RESET -CONFIG_EHCI_IS_TDI CONFIG_EHCI_MMIO_BIG_ENDIAN CONFIG_EHCI_MXS_PORT0 CONFIG_EHCI_MXS_PORT1 @@ -3014,6 +3013,7 @@ CONFIG_USB_EHCI_BASE CONFIG_USB_EHCI_BASE_LIST CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY +CONFIG_USB_EHCI_IS_TDI CONFIG_USB_EHCI_KIRKWOOD CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_TXFIFO_THRESH From 7b805009fab3fae923ccc17db11de64769a3947c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sat, 9 Oct 2021 15:27:33 +0200 Subject: [PATCH 204/228] Convert CONFIG_USB_EHCI_MXS to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This option is only used for mx23evk_defconfig mx23_olinuxino_defconfig which are the only i.MX23 boards. Add depend on ARCH_MX23 and default to y. Signed-off-by: Marek Behún --- drivers/usb/host/Kconfig | 7 +++++++ include/configs/mxs.h | 1 - scripts/config_whitelist.txt | 1 - 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 10b0479a8a..be5e4b994d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -175,6 +175,13 @@ config USB_EHCI_MX7 ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. +config USB_EHCI_MXS + bool "Support for i.MX23 EHCI USB controller" + depends on ARCH_MX23 + default y + help + Enables support for the on-chip EHCI controller on i.MX23 SoCs. + config USB_EHCI_OMAP bool "Support for OMAP3+ on-chip EHCI USB controller" depends on ARCH_OMAP2PLUS diff --git a/include/configs/mxs.h b/include/configs/mxs.h index d7d3e9d57f..ee2d7fa1b7 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -123,7 +123,6 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MXS #define CONFIG_USB_EHCI_IS_TDI #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index de592646b2..619e7260d4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3015,7 +3015,6 @@ CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY CONFIG_USB_EHCI_IS_TDI CONFIG_USB_EHCI_KIRKWOOD -CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_ETH_QMULT CONFIG_USB_ETH_SUBSET From 645a0afb328725afa817eb15d86aca2644c33579 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sat, 9 Oct 2021 15:27:34 +0200 Subject: [PATCH 205/228] Drop CONFIG_USB_EHCI_KIRKWOOD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This config option doesn't do anything. nas220 uses USB_EHCI_MARVELL. Signed-off-by: Marek Behún --- include/configs/nas220.h | 1 - scripts/config_whitelist.txt | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/nas220.h b/include/configs/nas220.h index f071ee6e1c..52c55be061 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -64,7 +64,6 @@ * USB/EHCI */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ #define CONFIG_USB_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 619e7260d4..3269293428 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3014,7 +3014,6 @@ CONFIG_USB_EHCI_BASE_LIST CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY CONFIG_USB_EHCI_IS_TDI -CONFIG_USB_EHCI_KIRKWOOD CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_ETH_QMULT CONFIG_USB_ETH_SUBSET From 56882dc4cbc7f70a9984c33eb9bf609e1dd60763 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sat, 9 Oct 2021 15:27:35 +0200 Subject: [PATCH 206/228] Convert CONFIG_USB_EHCI_IS_TDI to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On mvebu this is defined if and only if !ARM64. Otherwise it is defined for boards with ARCH_MX23, ARCH_TEGRA and ARCH_ZYNQ, and also for SOC_AR934X (tplink_wdr4300). Signed-off-by: Marek Behún --- arch/arm/mach-kirkwood/include/mach/config.h | 7 ------- arch/mips/mach-ath79/Kconfig | 1 + drivers/usb/host/Kconfig | 7 +++++++ include/configs/clearfog.h | 3 --- include/configs/controlcenterdc.h | 3 --- include/configs/crs3xx-98dx3236.h | 3 --- include/configs/db-88f6720.h | 1 - include/configs/db-88f6820-amc.h | 3 --- include/configs/db-88f6820-gp.h | 3 --- include/configs/db-mv784mp-gp.h | 1 - include/configs/db-xc3-24g4xg.h | 3 --- include/configs/ds414.h | 3 --- include/configs/helios4.h | 3 --- include/configs/mxs.h | 5 ----- include/configs/nas220.h | 7 ------- include/configs/tegra114-common.h | 1 - include/configs/tegra124-common.h | 1 - include/configs/tegra20-common.h | 1 - include/configs/tegra210-common.h | 1 - include/configs/tegra30-common.h | 1 - include/configs/theadorable.h | 1 - include/configs/tplink_wdr4300.h | 1 - include/configs/turris_omnia.h | 3 --- include/configs/x530.h | 3 --- include/configs/zynq-common.h | 2 -- scripts/config_whitelist.txt | 1 - 26 files changed, 8 insertions(+), 61 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index f262d70b14..cf6b1b9b63 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -62,13 +62,6 @@ #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ #endif /* CONFIG_CMD_NET */ -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - /* * IDE Support on SATA ports */ diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index bdb23b5765..cd85d1b6c3 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -20,6 +20,7 @@ config SOC_AR934X select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select USB_EHCI_IS_TDI if USB_EHCI_HCD help This supports QCA/Atheros ar934x family SOCs. diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index be5e4b994d..ccecb5a3b0 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -139,6 +139,9 @@ config USB_EHCI_HCD if USB_EHCI_HCD +config USB_EHCI_IS_TDI + bool + config USB_EHCI_ATMEL bool "Support for Atmel on-chip EHCI USB controller" depends on ARCH_AT91 @@ -150,6 +153,7 @@ config USB_EHCI_MARVELL bool "Support for Marvell on-chip EHCI USB controller" depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X default y + select USB_EHCI_IS_TDI if !ARM64 ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. @@ -179,6 +183,7 @@ config USB_EHCI_MXS bool "Support for i.MX23 EHCI USB controller" depends on ARCH_MX23 default y + select USB_EHCI_IS_TDI help Enables support for the on-chip EHCI controller on i.MX23 SoCs. @@ -258,12 +263,14 @@ config USB_EHCI_PCI config USB_EHCI_TEGRA bool "Support for NVIDIA Tegra on-chip EHCI USB controller" depends on ARCH_TEGRA + select USB_EHCI_IS_TDI ---help--- Enable support for Tegra on-chip EHCI USB controller config USB_EHCI_ZYNQ bool "Support for Xilinx Zynq on-chip EHCI USB controller" default y if ARCH_ZYNQ + select USB_EHCI_IS_TDI ---help--- Enable support for Zynq on-chip EHCI USB controller diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index a12e1582d6..a30bca5147 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -18,9 +18,6 @@ * U-Boot into it. */ -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - #define CONFIG_ENV_MIN_ENTRIES 128 /* Environment in MMC */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 12e9b8d06d..21e61e5e8f 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -27,9 +27,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 5300467a76..27b45a7605 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -13,9 +13,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ /* Keep device tree and initrd in lower memory so the kernel can access them */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 76c02f6656..19fc669f89 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -20,7 +20,6 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index c5f0a1d2e0..1f70c609d2 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -10,9 +10,6 @@ * High Level Configuration Options (easy to change) */ -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index ecda30bab5..41dadfebb9 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -22,9 +22,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index defe480613..dbbc33ebf9 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -21,7 +21,6 @@ #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 206afae590..6a4c5a7ab5 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ /* NAND */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 85abed5d3b..1f2d2c5e44 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -24,9 +24,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -/* USB/EHCI/XHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 7ed70602d1..56d35d6fdb 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -18,9 +18,6 @@ * U-Boot into it. */ -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - #define CONFIG_ENV_MIN_ENTRIES 128 /* Environment in MMC */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index ee2d7fa1b7..51624a27c4 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -121,9 +121,4 @@ #define CONFIG_SPI_HALF_DUPLEX #endif -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_IS_TDI -#endif - #endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 52c55be061..99b14ba621 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -60,13 +60,6 @@ #define CONFIG_PHY_BASE_ADR 8 #endif /* CONFIG_CMD_NET */ -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - /* * File system */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 06b687d556..0973721180 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -58,7 +58,6 @@ #define CONFIG_SPL_STACK 0x800ffffc /* For USB EHCI controller */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index de78ac9924..df688dabd1 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -60,7 +60,6 @@ #define CONFIG_SPL_STACK 0x800ffffc /* For USB EHCI controller */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 /* GPU needs setup */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d2bed64ccd..063213cbfe 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -78,7 +78,6 @@ * packets depending on the buffer address and size. */ #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_SYS_NAND_SELF_INIT diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 6c58ccc3d5..c36bdb0bb9 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -47,7 +47,6 @@ "ramdisk_addr_r=0x83200000\0" /* For USB EHCI controller */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 /* GPU needs setup */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 56b2671e43..b878b1a9e6 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -55,7 +55,6 @@ #define CONFIG_SPL_STACK 0x800ffffc /* For USB EHCI controller */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 #endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 073855592b..b43c03d3e8 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -29,7 +29,6 @@ #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* Environment in SPI NOR flash */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index ede94e95f7..3e76d638c9 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -41,7 +41,6 @@ /* USB, USB storage, USB ethernet */ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_USB_EHCI_IS_TDI /* * Diagnostics diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 4d8a7c37de..8d7d5c2bfc 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -17,9 +17,6 @@ * U-Boot into it. */ -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 23b1121460..f8b808ec7c 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -45,9 +45,6 @@ /* Additional FS support/configuration */ -/* USB/EHCI configuration */ -#define CONFIG_USB_EHCI_IS_TDI - /* Environment in SPI NOR flash */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index f3c8512641..4de2f94b04 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -55,8 +55,6 @@ #endif #ifdef CONFIG_USB_EHCI_ZYNQ -# define CONFIG_USB_EHCI_IS_TDI - # define DFU_DEFAULT_POLL_TIMEOUT 300 # define CONFIG_THOR_RESET_OFF #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3269293428..64a13c2a24 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3013,7 +3013,6 @@ CONFIG_USB_EHCI_BASE CONFIG_USB_EHCI_BASE_LIST CONFIG_USB_EHCI_EXYNOS CONFIG_USB_EHCI_FARADAY -CONFIG_USB_EHCI_IS_TDI CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_ETH_QMULT CONFIG_USB_ETH_SUBSET From cdcbd593ad9a2111eaebad63f020b6c756cd9b8b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 15 Oct 2021 08:06:20 -0400 Subject: [PATCH 207/228] configs: Resync with savedefconfig Resync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- configs/Bananapi_M2_Ultra_defconfig | 1 - configs/Cubieboard4_defconfig | 2 +- configs/Cubietruck_plus_defconfig | 1 - configs/Merrii_A80_Optimus_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 - configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 - configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 - configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 - configs/P1010RDB-PA_NAND_defconfig | 1 - configs/P1010RDB-PA_NOR_defconfig | 1 - configs/P1010RDB-PA_SDCARD_defconfig | 1 - configs/P1010RDB-PA_SPIFLASH_defconfig | 1 - configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 - configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 - configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 - configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 - configs/P1010RDB-PB_NAND_defconfig | 1 - configs/P1010RDB-PB_NOR_defconfig | 1 - configs/P1010RDB-PB_SDCARD_defconfig | 1 - configs/P1010RDB-PB_SPIFLASH_defconfig | 1 - configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 - configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 - configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 - configs/P1020RDB-PC_36BIT_defconfig | 1 - configs/P1020RDB-PC_NAND_defconfig | 1 - configs/P1020RDB-PC_SDCARD_defconfig | 1 - configs/P1020RDB-PC_SPIFLASH_defconfig | 1 - configs/P1020RDB-PC_defconfig | 1 - configs/P1020RDB-PD_NAND_defconfig | 1 - configs/P1020RDB-PD_SDCARD_defconfig | 1 - configs/P1020RDB-PD_SPIFLASH_defconfig | 1 - configs/P1020RDB-PD_defconfig | 1 - configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 - configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 - configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 - configs/P2020RDB-PC_36BIT_defconfig | 1 - configs/P2020RDB-PC_NAND_defconfig | 1 - configs/P2020RDB-PC_SDCARD_defconfig | 1 - configs/P2020RDB-PC_SPIFLASH_defconfig | 1 - configs/P2020RDB-PC_defconfig | 1 - configs/P2041RDB_NAND_defconfig | 1 - configs/P2041RDB_SDCARD_defconfig | 1 - configs/P2041RDB_SPIFLASH_defconfig | 1 - configs/P2041RDB_defconfig | 1 - configs/P3041DS_NAND_defconfig | 1 - configs/P3041DS_SDCARD_defconfig | 1 - configs/P3041DS_SPIFLASH_defconfig | 1 - configs/P3041DS_defconfig | 1 - configs/P4080DS_SDCARD_defconfig | 1 - configs/P4080DS_SPIFLASH_defconfig | 1 - configs/P4080DS_defconfig | 1 - configs/P5040DS_NAND_defconfig | 1 - configs/P5040DS_SDCARD_defconfig | 1 - configs/P5040DS_SPIFLASH_defconfig | 1 - configs/P5040DS_defconfig | 1 - configs/T1024RDB_NAND_defconfig | 1 - configs/T1024RDB_SDCARD_defconfig | 1 - configs/T1024RDB_SPIFLASH_defconfig | 1 - configs/T1024RDB_defconfig | 1 - configs/T1042D4RDB_NAND_defconfig | 1 - configs/T1042D4RDB_SDCARD_defconfig | 1 - configs/T1042D4RDB_SPIFLASH_defconfig | 1 - configs/T1042D4RDB_defconfig | 1 - configs/T2080QDS_NAND_defconfig | 1 - configs/T2080QDS_SDCARD_defconfig | 1 - configs/T2080QDS_SECURE_BOOT_defconfig | 1 - configs/T2080QDS_SPIFLASH_defconfig | 1 - configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 - configs/T2080QDS_defconfig | 1 - configs/T2080RDB_NAND_defconfig | 1 - configs/T2080RDB_SDCARD_defconfig | 1 - configs/T2080RDB_SPIFLASH_defconfig | 1 - configs/T2080RDB_defconfig | 1 - configs/T2080RDB_revD_NAND_defconfig | 1 - configs/T2080RDB_revD_SDCARD_defconfig | 1 - configs/T2080RDB_revD_SPIFLASH_defconfig | 1 - configs/T2080RDB_revD_defconfig | 1 - configs/T4240RDB_SDCARD_defconfig | 1 - configs/T4240RDB_defconfig | 1 - configs/am57xx_evm_defconfig | 1 - configs/am57xx_hs_evm_defconfig | 1 - configs/am57xx_hs_evm_usb_defconfig | 1 - configs/am64x_evm_a53_defconfig | 1 - configs/am64x_evm_r5_defconfig | 1 - configs/aristainetos2c_defconfig | 2 -- configs/aristainetos2ccslb_defconfig | 2 -- configs/bananapi_m2_berry_defconfig | 1 - configs/beaver_defconfig | 1 - configs/cardhu_defconfig | 1 - configs/cei-tk1-som_defconfig | 1 - configs/cl-som-imx7_defconfig | 1 - configs/clearfog_defconfig | 1 - configs/clearfog_gt_8k_defconfig | 1 - configs/cm_fx6_defconfig | 1 - configs/colibri-imx6ull_defconfig | 2 +- configs/colibri_imx7_defconfig | 2 +- configs/controlcenterdc_defconfig | 1 - configs/dalmore_defconfig | 1 - configs/db-88f6720_defconfig | 1 - configs/db-88f6820-amc_defconfig | 1 - configs/db-88f6820-gp_defconfig | 1 - configs/dh_imx6_defconfig | 1 - configs/display5_defconfig | 1 - configs/display5_factory_defconfig | 1 - configs/dra7xx_evm_defconfig | 1 - configs/dra7xx_hs_evm_defconfig | 1 - configs/dra7xx_hs_evm_usb_defconfig | 1 - configs/evb-px30_defconfig | 1 - configs/firefly-px30_defconfig | 1 - configs/gardena-smart-gateway-at91sam_defconfig | 2 +- configs/ge_b1x5v2_defconfig | 2 -- configs/ge_bx50v3_defconfig | 1 - configs/helios4_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig | 1 - configs/imx8mn_beacon_defconfig | 1 - configs/imx8ulp_evk_defconfig | 1 - configs/imxrt1050-evk_defconfig | 2 +- configs/jetson-tk1_defconfig | 1 - configs/kp_imx53_defconfig | 1 - configs/ls1012aqds_qspi_defconfig | 1 - configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1012aqds_tfa_defconfig | 1 - configs/marsboard_defconfig | 1 - configs/mccmon6_nor_defconfig | 2 -- configs/mccmon6_sd_defconfig | 2 -- configs/mvebu_crb_cn9130_defconfig | 1 - configs/mvebu_db-88f3720_defconfig | 1 - configs/mvebu_db_armada8k_defconfig | 1 - configs/mvebu_db_cn9130_defconfig | 1 - configs/mvebu_espressobin-88f3720_defconfig | 1 - configs/mvebu_mcbin-88f8040_defconfig | 1 - configs/mvebu_puzzle-m801-88f8040_defconfig | 1 - configs/mx6qsabrelite_defconfig | 1 - configs/mx6sabreauto_defconfig | 1 - configs/mx6sabresd_defconfig | 1 - configs/mx6slevk_defconfig | 1 - configs/mx6slevk_spinor_defconfig | 1 - configs/mx6slevk_spl_defconfig | 1 - configs/mx6sxsabreauto_defconfig | 1 - configs/mx6sxsabresd_defconfig | 1 - configs/mx6ul_14x14_evk_defconfig | 3 +-- configs/mx6ul_9x9_evk_defconfig | 3 +-- configs/mx6ull_14x14_evk_defconfig | 1 - configs/mx6ull_14x14_evk_plugin_defconfig | 1 - configs/mx6ulz_14x14_evk_defconfig | 1 - configs/mx7dsabresd_qspi_defconfig | 1 - configs/mx7ulp_com_defconfig | 1 - configs/myir_mys_6ulx_defconfig | 1 - configs/nitrogen6dl2g_defconfig | 1 - configs/nitrogen6dl_defconfig | 1 - configs/nitrogen6q2g_defconfig | 1 - configs/nitrogen6q_defconfig | 1 - configs/nitrogen6s1g_defconfig | 1 - configs/nitrogen6s_defconfig | 1 - configs/nyan-big_defconfig | 1 - configs/odroid-go2_defconfig | 3 +-- configs/odroid-hc4_defconfig | 2 +- configs/opos6uldev_defconfig | 2 +- configs/orangepi_zero2_defconfig | 1 - configs/p2371-0000_defconfig | 1 - configs/p2371-2180_defconfig | 1 - configs/p2571_defconfig | 1 - configs/p3450-0000_defconfig | 1 - configs/pcm058_defconfig | 1 - configs/peach-pi_defconfig | 1 - configs/peach-pit_defconfig | 1 - configs/phycore_pcl063_defconfig | 1 - configs/phycore_pcl063_ull_defconfig | 1 - configs/pico-imx7d_bl33_defconfig | 2 +- configs/pico-imx7d_defconfig | 2 +- configs/pinecube_defconfig | 1 - configs/px30-core-ctouch2-px30_defconfig | 1 - configs/px30-core-edimm2.2-px30_defconfig | 1 - configs/radxa-zero_defconfig | 2 +- configs/riotboard_defconfig | 1 - configs/sama5d2_icp_qspiflash_defconfig | 2 +- configs/seeed_npi_imx6ull_defconfig | 1 - configs/sifive_unmatched_defconfig | 2 +- configs/smdk5250_defconfig | 1 - configs/smdk5420_defconfig | 1 - configs/snow_defconfig | 1 - configs/spring_defconfig | 1 - configs/stm32f429-discovery_defconfig | 1 - configs/synquacer_developerbox_defconfig | 1 - configs/tec-ng_defconfig | 1 - configs/topic_miami_defconfig | 1 - configs/topic_miamilite_defconfig | 1 - configs/topic_miamiplus_defconfig | 1 - configs/tqma6dl_mba6_mmc_defconfig | 1 - configs/tqma6dl_mba6_spi_defconfig | 1 - configs/tqma6q_mba6_mmc_defconfig | 1 - configs/tqma6q_mba6_spi_defconfig | 1 - configs/tqma6s_mba6_mmc_defconfig | 1 - configs/tqma6s_mba6_spi_defconfig | 1 - configs/trimslice_defconfig | 1 - configs/turris_mox_defconfig | 1 - configs/turris_omnia_defconfig | 1 - configs/uDPU_defconfig | 1 - configs/variscite_dart6ul_defconfig | 1 - configs/venice2_defconfig | 1 - configs/vinco_defconfig | 1 - configs/warp7_bl33_defconfig | 2 -- configs/warp7_defconfig | 3 +-- configs/x530_defconfig | 1 - configs/xilinx_zynqmp_virt_defconfig | 1 - scripts/config_whitelist.txt | 5 ----- 206 files changed, 17 insertions(+), 220 deletions(-) diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index a24c600301..8917af3c93 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -13,7 +13,6 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y -CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 3848cab4b6..04ed79afb6 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -11,6 +11,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" -CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP_GPIO=y +CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index a4f8869731..13f958977b 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -16,7 +16,6 @@ CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y -CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 35e575327f..c5d1f40df3 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -11,6 +11,6 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" -CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP_GPIO=y +CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 628880ae0b..acd841a5ed 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -71,7 +71,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 59c7569272..32d5e38f03 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -50,7 +50,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index e8df2c3df5..9254c40357 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -62,7 +62,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 7d2ccc7a22..4d8f5d8655 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -64,7 +64,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index caac1e5e6d..24421a66b7 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -70,7 +70,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index abeb433427..09b412028f 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -49,7 +49,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index a29ff2725e..9db5a9860d 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -61,7 +61,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 51923777c8..d3e73b6bfb 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -63,7 +63,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 99dbf2c9ca..f61870784d 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -74,7 +74,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 44ba09cb31..16cb143d68 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -52,7 +52,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index a895c61c7c..cf9203eaa9 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -64,7 +64,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index ce175e8e24..9868c996f7 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -66,7 +66,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 76a81b6dad..421025e75a 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -73,7 +73,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 46fbed2e34..555cce9d28 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -51,7 +51,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index db47f4f8cd..724d6929aa 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -63,7 +63,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 5c549cc992..b79e3b8594 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -65,7 +65,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 3abcb7178d..52e6ee4246 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -71,7 +71,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 9941c14aa3..7f6ff420fa 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -63,7 +63,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 6152ef9f3e..4cac391918 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -65,7 +65,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index d7cc4dbc7d..c1dcb426ed 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -52,7 +52,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index cd573cbc5d..66ab2084c3 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -70,7 +70,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 5d668ca660..4ee631e862 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -62,7 +62,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index bc5f577468..e41c372c82 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -64,7 +64,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 0778dc6963..10f39a9c52 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -51,7 +51,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 3b5a14b1ac..b4e2322244 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -74,7 +74,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 4f4e5f5268..dee35eeb82 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -66,7 +66,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 205ca03b49..cc354f0ec6 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -68,7 +68,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index c7ba60ce32..400ab1e18e 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -55,7 +55,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3d72d46ee2..47a87acb29 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -76,7 +76,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 282ed313f8..e3496c428a 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -68,7 +68,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index fe2bf1af57..9397105eda 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -70,7 +70,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 92521518ea..c3bc4d13e3 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -57,7 +57,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index c700ee42cc..1ca78446af 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -75,7 +75,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x4000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 32e509d78b..34e9557684 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -67,7 +67,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index bfee816e3a..1fb8449303 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -69,7 +69,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index dbd2d87358..4b4bad5f14 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -56,7 +56,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_ATHEROS=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 5e6f3be594..1018275152 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -51,7 +51,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 67c4f40f2b..767b8a7d2c 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -50,7 +50,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 6e0b99adad..06aad4749e 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -51,7 +51,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 49e485defd..7d950645c1 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -46,7 +46,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 6d1f346b4a..fbaa5be1c3 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -51,7 +51,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 43d0d31259..3277be6f4d 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -50,7 +50,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index f905a5aa6c..a1f0da6a7c 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -51,7 +51,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 7406b1e4ff..d659d682a3 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -46,7 +46,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index ed46a1bcd5..ce95b17191 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -49,7 +49,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index ae46fd418d..cd4a914e61 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -50,7 +50,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index d9094b975f..4960ef048e 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -45,7 +45,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 87e88d427c..ef6a2b90ea 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -52,7 +52,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_ELBC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index a1b4cf3f7f..80c2c6803f 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -50,7 +50,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 27b009cf40..211a683009 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -51,7 +51,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 89924b4983..5ebc4c39d3 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -46,7 +46,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 9330f71f31..21e6986437 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -84,7 +84,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 82848a7ebb..47cac6b40a 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -79,7 +79,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index a9424fad1f..ef38aceb01 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -81,7 +81,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 8b07e21fbc..8da4802662 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -64,7 +64,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index b4a5ff735d..ce9c6b805b 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -78,7 +78,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 6d9f777658..7b0289fc4a 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -73,7 +73,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index b818e63157..71a39c2860 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -75,7 +75,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 2fdf4703eb..12f1349660 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -58,7 +58,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 5f3ec9c8a2..e4cbcf222b 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -76,7 +76,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 0046c7120a..6fc5f01bc9 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -71,7 +71,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index dc3e98544a..c30343328f 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -55,7 +55,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 9c1912e0d9..cb459ecf83 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -73,7 +73,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 344e2cb240..1dc5cf8778 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -48,7 +48,6 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 1679ef1481..00cd009e09 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -56,7 +56,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 72e3d50a76..7ebe8e3b59 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -82,7 +82,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 68989d722d..b8656efe8f 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -77,7 +77,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 6a9752ab41..b0d5e256e5 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -79,7 +79,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index db0c09b876..610f706473 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -62,7 +62,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index c7482d6e7c..b56314bd01 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -83,7 +83,6 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index f7f37e861b..1c42f54c96 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -78,7 +78,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index f91e7a8b44..a03b211f73 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -80,7 +80,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index d20b57673e..569efe9e7d 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -63,7 +63,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 6d6673673f..ea71242c09 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -63,7 +63,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index a3ae720f90..3a28c2a315 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -48,7 +48,6 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 9a038a6bc6..f747cff10b 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -84,7 +84,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 0a99df487e..0533dbd97e 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -80,7 +80,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index dbbe18d51b..7be951b7ef 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -87,7 +87,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 859306d1fa..d157403d84 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -94,7 +94,6 @@ CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_TI_DP83867=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 1659760674..5b04f18a63 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -95,7 +95,6 @@ CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 0a4c48fb5d..ad4e8350c3 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -78,7 +78,6 @@ CONFIG_I2C_EEPROM=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y @@ -93,7 +92,6 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_DA9063=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_DA9063=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 342e4e9a45..e4ecd81c1e 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -78,7 +78,6 @@ CONFIG_I2C_EEPROM=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MTD=y @@ -93,7 +92,6 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_DA9063=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_DA9063=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 8b7f37675a..2d65d0fd19 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -10,7 +10,6 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y -CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index ec45269075..df6a56e89e 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -39,7 +39,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 6fb808db9e..47995eab20 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -30,7 +30,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 8923fd0224..0acde45973 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -39,7 +39,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 99c46853a8..0e71364917 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -69,7 +69,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index f613107ccd..718ac7ccb2 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 89b978db6b..082ced93d2 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -48,7 +48,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index c0bc6202e2..1c8bde3de4 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -80,7 +80,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 0c0f1435ab..edb21c8772 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -95,8 +95,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 671390453a..fae8fce9a4 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -91,8 +91,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index bf0581ad16..5cfd61f415 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 8c5ac9de1b..de7879e856 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -38,7 +38,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 632a22f46f..0e9299da59 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 0bb0d5931f..fd5e648714 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 2e0f9384f2..da18e7d801 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index abbb6412e8..b113d0dc35 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -71,7 +71,6 @@ CONFIG_I2C_EEPROM=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index a49bf33179..b02f6f1567 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -98,7 +98,6 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 5a2e478c48..df84ee57c6 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -102,7 +102,6 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 19f5563e15..9bc6b796ac 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -101,7 +101,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_TI_DP83867=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index d6a752cd7a..9e7b6feb0e 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -102,7 +102,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000 CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_TI_DP83867=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 09aa07379a..f1aac202ae 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -91,7 +91,6 @@ CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 7265ac4c5c..057aa53257 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -31,7 +31,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y # CONFIG_TPL_BANNER_PRINT is not set -CONFIG_SPL_CRC32=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 363fa636f3..0fb27e9c63 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -32,7 +32,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y # CONFIG_TPL_BANNER_PRINT is not set -CONFIG_SPL_CRC32=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 9c1b6b3e34..32736720a0 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -86,13 +86,13 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y -CONFIG_MTD_UBI_FASTMAP=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 +CONFIG_MTD_UBI_FASTMAP=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index ef32a4bc6d..4642ced9e1 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -86,7 +86,6 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y @@ -100,7 +99,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 690fa11782..29df3082a4 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -59,7 +59,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index c121a3caf6..2071aa9024 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index cb37442d36..70bf747c41 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -89,7 +89,6 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 59cae55c88..d2ff02ffd0 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -91,7 +91,6 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index f156100888..23afbbb914 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -52,7 +52,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHYLIB=y diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index ace8941693..92c398e5bd 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -72,9 +72,9 @@ CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 50e85be9dc..33b850fe5c 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -39,7 +39,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index b8f6d8ad81..b611cee63d 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -49,7 +49,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX5=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_MC34708=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPECIFY_CONSOLE_INDEX=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 0903650c18..376bcf568c 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -63,7 +63,6 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 02eecf0d13..939ca2c31b 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -52,7 +52,6 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index fad0c1c3be..8ded692bc9 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -64,7 +64,6 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 8e0aa045c8..33be803d6d 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -38,7 +38,6 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 9fabc298bc..c8b8df3144 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -62,7 +62,6 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y @@ -74,7 +73,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index f9d586a900..bf32c7104b 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -60,7 +60,6 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y @@ -72,7 +71,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index f0f50a9669..334d7f2183 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -51,7 +51,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index d401f4765f..ba7ee9211e 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -50,7 +50,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index 4ad6d4d7e2..d9a5759d44 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -44,7 +44,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index e0470ce7ab..c8dffe0117 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -56,7 +56,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_PXA3XX=y CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 01cf24aec9..bf3f080422 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -60,7 +60,6 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 44f16b62cf..61cc260203 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -48,7 +48,6 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig index c521f2c101..da73dd1cbd 100644 --- a/configs/mvebu_puzzle-m801-88f8040_defconfig +++ b/configs/mvebu_puzzle-m801-88f8040_defconfig @@ -54,7 +54,6 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_MARVELL=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 419626a263..da1f030856 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -58,7 +58,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 5819fe6d8e..5fd0dee170 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -80,7 +80,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 5216bcadde..676e8a928b 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -87,7 +87,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index c041cb7095..a75a632635 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -42,7 +42,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 1e6aae68d7..94692c296f 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -42,7 +42,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 7c445e6e0c..ce1d5184dd 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -55,7 +55,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 957dc45b29..5bb481bd17 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -44,7 +44,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index b80dc94656..751aa53cf2 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -45,7 +45,6 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index ee80006635..dd3847ef9a 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -64,7 +64,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y @@ -93,8 +92,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 7abe5be359..65bc15c716 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -57,7 +57,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y @@ -83,8 +82,8 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 8ecb496571..1b70100f0a 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -40,7 +40,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 64719b1efd..aaac3719c3 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -41,7 +41,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index e233931d40..28bc8dbbfa 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -39,7 +39,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PINCTRL=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 0da33c4507..c5613b35d3 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -52,7 +52,6 @@ CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig index 6e6b821d90..84aca9617f 100644 --- a/configs/mx7ulp_com_defconfig +++ b/configs/mx7ulp_com_defconfig @@ -34,7 +34,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_ATMEL=y CONFIG_PINCTRL=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index 022f9ffd82..5f140a54b7 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -60,7 +60,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index a56cb2c497..f0d6dd1e1b 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 68d286c96c..54e5a4d397 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index cbe9ced14a..c19284c307 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -63,7 +63,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 95e60f9c05..ef23d610c6 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -63,7 +63,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 43c0787dc1..31fb783eda 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index a8428dc3ab..78d4b7b6c4 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -61,7 +61,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 9d7d54e6c3..daf01140db 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -59,7 +59,6 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_PMIC=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index df64307f8e..70ebcd3ce6 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -35,7 +35,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y # CONFIG_TPL_BANNER_PRINT is not set -CONFIG_SPL_CRC32=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_ATF=y @@ -98,7 +97,6 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SOUND=y CONFIG_SYSRESET=y -CONFIG_OPTEE_LIB=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -112,3 +110,4 @@ CONFIG_SPL_TINY_MEMSET=y CONFIG_TPL_TINY_MEMSET=y CONFIG_LZO=y CONFIG_ERRNO_STR=y +CONFIG_OPTEE_LIB=y diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig index 917d95c9c1..2fe761e939 100644 --- a/configs/odroid-hc4_defconfig +++ b/configs/odroid-hc4_defconfig @@ -11,8 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xff803000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" odroid-hc4" CONFIG_DEBUG_UART=y -CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_AHCI=y +CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index bd78f25295..0bc1c6c7b1 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -103,10 +103,10 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_SPLASH_SOURCE=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index edb765f02f..22563c864f 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -11,7 +11,6 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y -CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 43d9095adc..940c4962a6 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -33,7 +33,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index c9498b39b8..27a19d2261 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -37,7 +37,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 27cc68e220..125103934f 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -34,7 +34,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index 0587ca9c6b..dc487ff8de 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -38,7 +38,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_RTL8169=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index aefd91a48d..c29087534e 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -70,7 +70,6 @@ CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 173ed4efa1..14584419c4 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -53,7 +53,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index af4865f82a..db18bec9bc 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -52,7 +52,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 03d3e6f84a..0897aeedb1 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -55,7 +55,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 6524349840..d8ce8d2fb4 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -44,7 +44,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index cb057b66f2..2da6e9c3a3 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -81,8 +81,8 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index e840bf04f3..34c0648ee2 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -85,8 +85,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_MXS=y CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 742da36502..0c71d59418 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y CONFIG_SPL_I2C=y -CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 91461918d6..0bba43ced8 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -32,7 +32,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y # CONFIG_TPL_BANNER_PRINT is not set -CONFIG_SPL_CRC32=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 46077fa64e..f8db3d1b77 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -32,7 +32,6 @@ CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y # CONFIG_TPL_BANNER_PRINT is not set -CONFIG_SPL_CRC32=y CONFIG_SPL_ATF=y # CONFIG_TPL_FRAMEWORK is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig index 91457f5eb7..a9afb64ae0 100644 --- a/configs/radxa-zero_defconfig +++ b/configs/radxa-zero_defconfig @@ -22,10 +22,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1fb708433f..5fdbc5629b 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -50,7 +50,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig index bf442bff2a..e88a47a96a 100644 --- a/configs/sama5d2_icp_qspiflash_defconfig +++ b/configs/sama5d2_icp_qspiflash_defconfig @@ -14,9 +14,9 @@ CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=83000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_SYS_BOOT_GET_CMDLINE=y CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_QSPI_BOOT=y diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index caff2a69ad..97158c60fc 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -62,7 +62,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 55646550d3..555b19148d 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +# CONFIG_SPL_USE_ARCH_MEMMOVE is not set CONFIG_SPL_GPIO=y CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_NR_DRAM_BANKS=1 @@ -12,7 +13,6 @@ CONFIG_AHCI=y CONFIG_TARGET_SIFIVE_UNMATCHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y -# CONFIG_SPL_USE_ARCH_MEMMOVE is not set CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_FIT=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index f1d38eea66..0da76e5d2d 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -48,7 +48,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index fa0c2ea752..6c5d4b0096 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -43,7 +43,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 407777c032..55ee7c6e00 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -58,7 +58,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index a9062b29ad..a286467a61 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -58,7 +58,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y CONFIG_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 6ee6e08524..ed96c370d5 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -12,7 +12,6 @@ CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_SYS_LOAD_ADDR=0x90400000 CONFIG_BOOTDELAY=3 -CONFIG_BOOTCOMMAND="run bootcmd_romfs" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index a88856b272..72d6c8c224 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -93,4 +93,3 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -CONFIG_EFI_SECURE_BOOT=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 760e5160d0..df9c2429d5 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -30,7 +30,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index b43e546ded..f8ba64db14 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -46,7 +46,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=108000000 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index a8a0ff2247..94d7afd5d1 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -46,7 +46,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=108000000 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 7f8cb4bbdb..dc03caa649 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -45,7 +45,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=108000000 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index 8ca32b1322..9f3e8f6c85 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -39,7 +39,6 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 75b034a2c2..a7a9776254 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -43,7 +43,6 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index f2ba64943a..955877b34b 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -39,7 +39,6 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 65c52aab55..d1f3f2be5d 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -43,7 +43,6 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index fce236e5c8..c46c7e24f3 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -39,7 +39,6 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index 23aa030955..feb98a6010 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -43,7 +43,6 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_FSL_USDHC=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 8881645dc5..50b08cb8f8 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -33,7 +33,6 @@ CONFIG_ENV_SPI_MAX_HZ=48000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y CONFIG_PCI=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 82ad68b6a1..6ff551e477 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -67,7 +67,6 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 4d080baa14..9cad1e1e51 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index a06a25378e..17278ae4cc 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -60,7 +60,6 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index e93ce8e3a0..d15886c143 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -47,7 +47,6 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index dba47c99fe..d005bbfb9b 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -37,7 +37,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000 CONFIG_SYS_I2C_TEGRA=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 5297c54b59..e90e362a40 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_AT91_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 CONFIG_PHY_SMSC=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 246a1ec6fe..9b4650f835 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -53,7 +53,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_OPTEE=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -68,4 +67,3 @@ CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_OPTEE_TZDRAM_SIZE=0x02000000 diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index db8d4f625a..4d1a781d9c 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_SYS_MALLOC_LEN=0x2300000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp" +CONFIG_OPTEE_TZDRAM_SIZE=0x3000000 CONFIG_TARGET_WARP7=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set @@ -59,7 +60,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_OPTEE=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -73,5 +73,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" -CONFIG_OPTEE_TZDRAM_SIZE=0x3000000 CONFIG_BOOTM_OPTEE=y diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 0f94b54bf6..6ba7ee2131 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 78ebff7155..ff5c8dc9bf 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -210,4 +210,3 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y -CONFIG_EFI_SECURE_BOOT=y diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 64a13c2a24..cd94b5777a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1134,8 +1134,6 @@ CONFIG_SMSTP8_ENA CONFIG_SMSTP9_ENA CONFIG_SOCRATES CONFIG_SOC_OMAP3430 -CONFIG_SOFT_I2C_GPIO_SCL -CONFIG_SOFT_I2C_GPIO_SDA CONFIG_SOFT_I2C_READ_REPEATED_START CONFIG_SPD_EEPROM CONFIG_SPIFLASH @@ -3050,7 +3048,6 @@ CONFIG_USB_TTY CONFIG_USB_TUSB_OMAP_DMA CONFIG_USB_ULPI_TIMEOUT CONFIG_USB_XHCI_EXYNOS -CONFIG_USER_LOWLEVEL_INIT CONFIG_USE_INTERRUPT CONFIG_USE_ONENAND_BOARD_INIT CONFIG_UTBIPAR_INIT_TBIPA @@ -3063,9 +3060,7 @@ CONFIG_VIDEO_BCM2835 CONFIG_VIDEO_BMP_LOGO CONFIG_VIDEO_DA8XX CONFIG_VIDEO_FONT_4X6 -CONFIG_VIDEO_LCD_I2C_BUS CONFIG_VIDEO_LOGO -CONFIG_VIDEO_MXS CONFIG_VIDEO_MXS_MODE_SYSTEM CONFIG_VIDEO_STD_TIMINGS CONFIG_VID_FLS_ENV From 2e8d2f88439d7437f04a6af1d206270f9a2240d3 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Oct 2021 00:00:13 +0300 Subject: [PATCH 208/228] riscv: Remove OF_PRIOR_STAGE from RISC-V boards At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. On RISC-V some of the boards pick up the DTB from a1 and copy it in their private gd_t. Apart from that they copy it to prior_stage_fdt_address, if the Kconfig option is selected, which is unnecessary. So let's switch the config option for those boards to OF_BOARD and define the required board_fdt_blob_setup() for them. Signed-off-by: Ilias Apalodimas Reviewed-by: Simon Glass Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/cpu.c | 3 --- arch/riscv/cpu/start.S | 5 ----- arch/riscv/dts/binman.dtsi | 6 +++--- board/AndesTech/ax25-ae350/ax25-ae350.c | 7 ++++++- board/emulation/qemu-riscv/qemu-riscv.c | 8 ++++++++ configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/qemu-riscv32_defconfig | 2 +- configs/qemu-riscv32_smode_defconfig | 2 +- configs/qemu-riscv32_spl_defconfig | 2 +- configs/qemu-riscv64_defconfig | 2 +- configs/qemu-riscv64_smode_defconfig | 2 +- configs/qemu-riscv64_spl_defconfig | 2 +- dts/Kconfig | 2 +- 16 files changed, 28 insertions(+), 23 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 8e49b6d736..8d90c5e6b8 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -17,9 +17,6 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ -#ifdef CONFIG_OF_PRIOR_STAGE -phys_addr_t prior_stage_fdt_address __section(".data"); -#endif #ifndef CONFIG_XIP u32 hart_lottery __section(".data") = 0; diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 308b0a97a5..76850ec9be 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -142,11 +142,6 @@ call_harts_early_init: bnez tp, secondary_hart_loop #endif -#ifdef CONFIG_OF_PRIOR_STAGE - la t0, prior_stage_fdt_address - SREG s1, 0(t0) -#endif - jal board_init_f_init_reserve SREG s1, GD_FIRMWARE_FDT_ADDR(gp) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index d26cfdb78a..5757ef65ea 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -48,7 +48,7 @@ }; }; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD @fdt-SEQ { description = "NAME"; type = "flat_dt"; @@ -60,7 +60,7 @@ configurations { default = "conf-1"; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD @conf-SEQ { #else conf-1 { @@ -68,7 +68,7 @@ description = "NAME"; firmware = "opensbi"; loadables = "uboot"; -#ifndef CONFIG_OF_PRIOR_STAGE +#ifndef CONFIG_OF_BOARD fdt = "fdt-SEQ"; #endif }; diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 15da58a314..b28894ed46 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -21,7 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern phys_addr_t prior_stage_fdt_address; /* * Miscellaneous platform dependent initializations */ @@ -57,7 +56,13 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) void *board_fdt_blob_setup(void) { +#if CONFIG_IS_ENABLED(OF_BOARD) + return (void *)(ulong)gd->arch.firmware_fdt_addr; +#elif CONFIG_IS_ENABLED(OF_SEPARATE) return (void *)CONFIG_SYS_FDT_BASE; +#else + return NULL; +#endif } int smc_init(void) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index dcfd3f20be..2a26e265ff 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -14,6 +14,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int board_init(void) { /* @@ -69,3 +71,9 @@ int board_fit_config_name_match(const char *name) return 0; } #endif + +void *board_fdt_blob_setup(void) +{ + /* Stored the DTB address there during our init */ + return (void *)(ulong)gd->arch.firmware_fdt_addr; +} diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index dab35f9bd6..2ee5bf18a6 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 11063e9e1b..7093569422 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -21,7 +21,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index d2d0e31827..4b98531add 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -18,7 +18,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 90511ae0bf..3c072aa2a5 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -22,7 +22,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index f49d49e1d3..e77e3ed53a 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -11,6 +11,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index a009f62369..03787416f1 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -12,7 +12,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index aac6f389a7..b0e655be41 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -14,7 +14,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 506ac4382c..1f8dc2d205 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -12,6 +12,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index db2f21d8db..bdcec1fdab 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -15,7 +15,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYSRESET_SBI=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index cf33870135..9745c1a586 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -15,7 +15,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_CMD_SBI=y # CONFIG_CMD_MII is not set -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_SYSRESET_SBI=y diff --git a/dts/Kconfig b/dts/Kconfig index 0cc562c626..7a297b2f0e 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -118,7 +118,7 @@ config OF_EMBED Boards in the mainline U-Boot tree should not use it. config OF_BOARD - bool "Provided by the board at runtime" + bool "Provided by the board (e.g a previous loader) at runtime" depends on !SANDBOX help If this option is enabled, the device tree will be provided by From 2ea63271e522ff6cc9e48191b0e3b459f5e7b456 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Oct 2021 00:00:14 +0300 Subject: [PATCH 209/228] board: arm: Remove OF_PRIOR_STAGE from the remaining Arm boards At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. So let's remove the option in an effort to simplify U-Boot's config and DTB management, and use OF_BOARD instead. Signed-off-by: Ilias Apalodimas Reviewed-by: Simon Glass --- arch/arm/Kconfig | 1 - board/broadcom/bcmstb/bcmstb.c | 6 ++++++ configs/bcm7260_defconfig | 2 +- configs/bcm7445_defconfig | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d8c041a877..504abca0b7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -636,7 +636,6 @@ config ARCH_BCMSTB select DM select GPIO_EXTRA_HEADER select OF_CONTROL - select OF_PRIOR_STAGE imply CMD_DM help This enables support for Broadcom ARM-based set-top box diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index 276e59b3bd..723ebda3bd 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -130,3 +130,9 @@ int board_late_init(void) return 0; } + +void *board_fdt_blob_setup(void) +{ + /* Stored the DTB address there during our init */ + return (void *)prior_stage_fdt_address; +} diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index ec58dd2536..3afb909f71 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index d5dd4b7010..3726abd735 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_PRIOR_STAGE=y +CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y From d6f8ab30a2af4666732c2077df8f731076827b2e Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 12 Oct 2021 00:00:15 +0300 Subject: [PATCH 210/228] treewide: Remove OF_PRIOR_STAGE The previous patches removed OF_PRIOR_STAGE from the last consumers of the Kconfig option. Cleanup any references to it in documentation, code and configuration options. Signed-off-by: Ilias Apalodimas Reviewed-by: Simon Glass --- dts/Kconfig | 11 ++--------- include/fdtdec.h | 4 ---- lib/fdtdec.c | 2 -- tools/binman/binman.rst | 16 ++++++---------- 4 files changed, 8 insertions(+), 25 deletions(-) diff --git a/dts/Kconfig b/dts/Kconfig index 7a297b2f0e..fc4130545a 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -22,7 +22,7 @@ config BINMAN config BINMAN_STANDALONE_FDT bool depends on BINMAN - default y if OF_BOARD || OF_PRIOR_STAGE + default y if OF_BOARD help This option tells U-Boot build system that a standalone device tree source is explicitly required when using binman to package U-Boot. @@ -32,7 +32,7 @@ config BINMAN_STANDALONE_FDT directory for a specific board. Such device tree sources are built for OF_SEPARATE or OF_EMBED. However for a scenario like the board device tree blob is not provided in the U-Boot build tree, but fed to U-Boot - in the runtime, e.g.: in the OF_PRIOR_STAGE case that it is passed by + in the runtime, e.g.: in the OF_BOARD case that it is passed by a prior stage bootloader. For such scenario, a standalone device tree blob containing binman node to describe how to package U-Boot should be provided explicitly. @@ -133,13 +133,6 @@ config OF_HOSTFILE This is only useful for Sandbox. Use the -d flag to U-Boot to specify the file to read. -config OF_PRIOR_STAGE - bool "Prior stage bootloader DTB for DT control" - help - If this option is enabled, the device tree used for DT - control will be read from a device tree binary, at a memory - location passed to U-Boot by the prior stage bootloader. - endchoice config DEFAULT_DEVICE_TREE diff --git a/include/fdtdec.h b/include/fdtdec.h index f94d1f4f3a..239814228d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -55,10 +55,6 @@ struct bd_info; #define SPL_BUILD 0 #endif -#ifdef CONFIG_OF_PRIOR_STAGE -extern phys_addr_t prior_stage_fdt_address; -#endif - /* * Information about a resource. start is the first address of the resource * and end is the last address (inclusive). The length of the resource will diff --git a/lib/fdtdec.c b/lib/fdtdec.c index ad090ea51e..959b337cdc 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1613,8 +1613,6 @@ int fdtdec_setup(void) puts("Failed to read control FDT\n"); return -1; } -# elif defined(CONFIG_OF_PRIOR_STAGE) - gd->fdt_blob = (void *)(uintptr_t)prior_stage_fdt_address; # endif # ifndef CONFIG_SPL_BUILD /* Allow the early environment to override the fdt address */ diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index 09e7b57198..614df541c5 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -232,18 +232,18 @@ You can use other, more specific CONFIG options - see 'Automatic .dtsi inclusion' below. -Using binman with OF_BOARD or OF_PRIOR_STAGE +Using binman with OF_BOARD -------------------------------------------- Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED. This is a typical scenario where a device tree source that contains the binman node is provided in the arch//dts directory for a specific board. -However for a board configured with OF_BOARD or OF_PRIOR_STAGE, no device tree -blob is provided in the U-Boot build phase hence the binman node information -is not available. In order to support such use case, a new Kconfig option -BINMAN_STANDALONE_FDT is introduced, to tell the build system that a standalone -device tree blob containing binman node is explicitly required. +However for a board configured with OF_BOARD, no device tree blob is provided +in the U-Boot build phase hence the binman node information is not available. +In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT +is introduced, to tell the build system that a standalone device tree blob +containing binman node is explicitly required. Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to access information about binman entries, stored in the device tree in a binman @@ -252,10 +252,6 @@ For the other OF_CONTROL methods, it's quite possible binman node is not available as binman is invoked during the build phase, thus this option is not turned on by default for these OF_CONTROL methods. -See qemu-riscv64_spl_defconfig for an example of how binman is used with -OF_PRIOR_STAGE to generate u-boot.itb image. - - Access to binman entry offsets at run time (symbols) ---------------------------------------------------- From d7faa082a57eeeff9b4bbcc45d3dfed747d99a70 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 22 Sep 2021 11:34:43 -0600 Subject: [PATCH 211/228] Revert "kbuild: remove unused dtc-version.sh script" We need this to make building dtc optional. It makes no sense to build our own dtc if the system one works correctly. This reverts commit ddb87a0b40262ff99d675e946f57427642303938. Signed-off-by: Simon Glass --- MAINTAINERS | 1 + scripts/Kbuild.include | 1 + scripts/dtc-version.sh | 22 ++++++++++++++++++++++ 3 files changed, 24 insertions(+) create mode 100755 scripts/dtc-version.sh diff --git a/MAINTAINERS b/MAINTAINERS index 71f468c00a..8845c6fd75 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -756,6 +756,7 @@ F: include/fdt* F: include/linux/libfdt* F: cmd/fdt.c F: common/fdt_support.c +F: scripts/dtc-version.sh FREEBSD M: Rafal Jaworowski diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index a745cc4fcc..09506cb9a7 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -148,6 +148,7 @@ cc-ifversion = $(shell [ $(cc-version) $(1) $(2) ] && echo $(3) || echo $(4)) # added for U-Boot binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) +dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC)) # cc-ldoption # Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both) diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh new file mode 100755 index 0000000000..bd4e818e92 --- /dev/null +++ b/scripts/dtc-version.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# dtc-version dtc-command +# +# Prints the dtc version of `dtc-command' in a canonical 6-digit form +# such as `010404' for dtc 1.4.4 +# + +dtc="$*" + +if [ ${#dtc} -eq 0 ]; then + echo "Error: No dtc command specified." + printf "Usage:\n\t$0 \n" + exit 1 +fi + +MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) +MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) +PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) + +printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCH From 93b196532254366f653b4d763f69e49ff193f06c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 22 Sep 2021 11:34:44 -0600 Subject: [PATCH 212/228] Makefile: Only build dtc if needed At present U-Boot always builds dtc if CONFIG_OF_CONTROL is defined, even when DTC is provided. The built dtc is not actually used, so this is a waste of time. Update the Makefile logic to build dtc only if one is not provided to the build with the DTC variable. Add documentation to explain this. This saves about 3.5 seconds of elapsed time on a clean build of sandbox_spl for me. Signed-off-by: Simon Glass --- Makefile | 30 ++++++++++++++++++++++++++++-- doc/build/gcc.rst | 21 +++++++++++++++++++++ dts/Kconfig | 4 ---- scripts/Makefile | 1 - scripts/dtc-version.sh | 7 ++++++- 5 files changed, 55 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index f911f70344..32d29b87db 100644 --- a/Makefile +++ b/Makefile @@ -415,7 +415,13 @@ PERL = perl PYTHON ?= python PYTHON2 = python2 PYTHON3 ?= python3 -DTC ?= $(objtree)/scripts/dtc/dtc + +# The devicetree compiler and pylibfdt are automatically built unless DTC is +# provided. If DTC is provided, it is assumed the pylibfdt is available too. +DTC_INTREE := $(objtree)/scripts/dtc/dtc +DTC ?= $(DTC_INTREE) +DTC_MIN_VERSION := 010406 + CHECK = sparse CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ @@ -1954,9 +1960,29 @@ endif endif +# Check dtc and pylibfdt, if DTC is provided, else build them PHONY += scripts_dtc scripts_dtc: scripts_basic - $(Q)$(MAKE) $(build)=scripts/dtc + $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ + $(MAKE) $(build)=scripts/dtc; \ + else \ + if ! $(DTC) -v >/dev/null; then \ + echo '*** Failed to check dtc version: $(DTC)'; \ + false; \ + else \ + if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \ + echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \ + false; \ + else \ + if [ -n "$(CONFIG_PYLIBFDT)" ]; then \ + if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \ + echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \ + false; \ + fi; \ + fi; \ + fi; \ + fi; \ + fi # --------------------------------------------------------------------------- quiet_cmd_cpp_lds = LDS $@ diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst index 0cdc307d57..6c4b4ad7a0 100644 --- a/doc/build/gcc.rst +++ b/doc/build/gcc.rst @@ -120,6 +120,27 @@ Further important build parameters are * O= - generate all output files in directory , including .config * V=1 - verbose build +Devicetree compiler +~~~~~~~~~~~~~~~~~~~ + +Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the +devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python +library for accessing devicetree data. Suitable versions of these are included +in the U-Boot tree in `scripts/dtc` and built automatically as needed. + +To use the system versions of these, use the DTC parameter, for example + +.. code-block:: bash + + DTC=/usr/bin/dtc make + +In this case, dtc and pylibfdt are not built. The build checks that the version +of dtc is new enough. It also makes sure that pylibfdt is present, if needed +(see `scripts_dtc` in the Makefile). + +Note that the :doc:`tools` are always built with the included version of libfdt +so it is not possible to build U-Boot tools with a system libfdt, at present. + Other build targets ~~~~~~~~~~~~~~~~~~~ diff --git a/dts/Kconfig b/dts/Kconfig index fc4130545a..90c7a1c5f4 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -5,9 +5,6 @@ config SUPPORT_OF_CONTROL bool -config DTC - bool - config PYLIBFDT bool @@ -42,7 +39,6 @@ menu "Device Tree Control" config OF_CONTROL bool "Run-time configuration via Device Tree" - select DTC select OF_LIBFDT if !OF_PLATDATA select OF_REAL if !OF_PLATDATA help diff --git a/scripts/Makefile b/scripts/Makefile index e7b353f77f..cfe9fef804 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -10,4 +10,3 @@ always := $(hostprogs-y) # Let clean descend into subdirs subdir- += basic kconfig -subdir-$(CONFIG_DTC) += dtc diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index bd4e818e92..bfb514e179 100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh @@ -10,11 +10,16 @@ dtc="$*" if [ ${#dtc} -eq 0 ]; then - echo "Error: No dtc command specified." + echo "Error: No dtc command specified" printf "Usage:\n\t$0 \n" exit 1 fi +if ! which $dtc >/dev/null ; then + echo "Error: Cannot find dtc: $dtc" + exit 1 +fi + MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) From bba76a17bd11b5700c2aeb4e7178ac8ac016849c Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Fri, 1 Oct 2021 13:37:57 +0200 Subject: [PATCH 213/228] drivers/gpio: add support for MAX7320 i2c i/o expander This commit adds support for the MAX7320 (and clones) gpio expander. Signed-off-by: Hannes Schmelzer --- .../gpio/gpio-max7320.txt | 36 ++++++ drivers/gpio/Kconfig | 8 ++ drivers/gpio/Makefile | 1 + drivers/gpio/max7320_gpio.c | 113 ++++++++++++++++++ 4 files changed, 158 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/gpio-max7320.txt create mode 100644 drivers/gpio/max7320_gpio.c diff --git a/doc/device-tree-bindings/gpio/gpio-max7320.txt b/doc/device-tree-bindings/gpio/gpio-max7320.txt new file mode 100644 index 0000000000..87b703bb69 --- /dev/null +++ b/doc/device-tree-bindings/gpio/gpio-max7320.txt @@ -0,0 +1,36 @@ +* MAX7320 I/O expanders + +The original maxim 7320 i/o expander offers 8 bit push/pull outputs. +There exists some clones which offers 16 bit. + +Required Properties: + + - compatible: should be one of the following. + - "maxim,max7320" + + - reg: I2C slave address. + + - gpio-controller: Marks the device node as a gpio controller. + - #gpio-cells: Should be 2. The first cell is the GPIO number and the second + cell specifies GPIO flags, as defined in . Only the + GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. + +Optional Properties: + + - ngpios: tell the driver how many gpios the device offers. + if the property is omitted, 8bit (original maxim) is assumed. + +Please refer to gpio.txt in this directory for details of the common GPIO +bindings used by client devices. + +Example: MAX7320 I/O expander node + + ledgpio: max7320@5d { + status = "okay"; + compatible = "maxim,max7320"; + reg = <0x5d>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <16>; + }; + diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f0439e2417..40abc33772 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -183,6 +183,14 @@ config LPC32XX_GPIO help Support for the LPC32XX GPIO driver. +config MAX7320_GPIO + bool "MAX7320 I2C GPIO Expander driver" + depends on DM_GPIO && DM_I2C + help + Support for MAX7320 I2C 8/16-bit GPIO expander. + original maxim device has 8 push/pull outputs, + some clones offers 16bit. + config MCP230XX_GPIO bool "MCP230XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a9dc546a20..3c851b38c7 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -68,3 +68,4 @@ obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o obj-$(CONFIG_NX_GPIO) += nx_gpio.o obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o +obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o diff --git a/drivers/gpio/max7320_gpio.c b/drivers/gpio/max7320_gpio.c new file mode 100644 index 0000000000..647aed907b --- /dev/null +++ b/drivers/gpio/max7320_gpio.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * max7320 I2C GPIO EXPANDER DRIVER + * + * Copyright (C) 2021 Hannes Schmelzer + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ + +#include +#include +#include +#include +#include + +struct max7320_chip { + u32 outreg; +}; + +static int max7320_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + struct max7320_chip *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct dm_i2c_chip *chip = dev_get_parent_plat(dev); + + int ret; + + if (value) + plat->outreg |= BIT(offset); + else + plat->outreg &= ~BIT(offset); + + ret = dm_i2c_write(dev, + plat->outreg & 0xff, + (uint8_t *)&plat->outreg + 1, + uc_priv->gpio_count > 8 ? 1 : 0); + if (ret) + printf("%s i2c write failed to addr %x\n", __func__, + chip->chip_addr); + + return ret; +} + +static int max7320_get_value(struct udevice *dev, unsigned int offset) +{ + struct max7320_chip *plat = dev_get_plat(dev); + + return (plat->outreg >> offset) & 0x1; +} + +static int max7320_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + return max7320_direction_output(dev, offset, value); +} + +static int max7320_get_function(struct udevice *dev, unsigned int offset) +{ + return GPIOF_OUTPUT; +} + +static int max7320_ofdata_plat(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 8); + if (uc_priv->gpio_count > 16) { + printf("%s: max7320 doesn't support more than 16 gpios!", + __func__); + return -EINVAL; + } + + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), + "gpio-bank-name", NULL); + if (!uc_priv->bank_name) + uc_priv->bank_name = fdt_get_name(gd->fdt_blob, + dev_of_offset(dev), NULL); + + return 0; +} + +static int max7320_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + debug("%s GPIO controller with %d gpios probed\n", + uc_priv->bank_name, uc_priv->gpio_count); + + return 0; +} + +static const struct dm_gpio_ops max7320_gpio_ops = { + .direction_output = max7320_direction_output, + .set_value = max7320_set_value, + .get_value = max7320_get_value, + .get_function = max7320_get_function, +}; + +static const struct udevice_id max7320_gpio_ids[] = { + { .compatible = "maxim,max7320" }, + { } +}; + +U_BOOT_DRIVER(gpio_max7320) = { + .name = "gpio_max7320", + .id = UCLASS_GPIO, + .ops = &max7320_gpio_ops, + .of_match = max7320_gpio_ids, + .of_to_plat = max7320_ofdata_plat, + .probe = max7320_gpio_probe, + .plat_auto = sizeof(struct max7320_chip), +}; From 1860bdca6a0198c23227588a817bd3b65754bf00 Mon Sep 17 00:00:00 2001 From: Amjad Ouled-Ameur Date: Mon, 11 Oct 2021 14:27:38 +0200 Subject: [PATCH 214/228] configs: am335x_evm: enable CONFIG_CLK_TI_CTRL This enables the clock controller driver support on TI's SoCs. This will fix this GPIO issue at boot time: request_and_set_gpio: Unable to request GPIO_PR1_MII_CTRL request_and_set_gpio: Unable to request GPIO_MUX_MII_CTRL request_and_set_gpio: Unable to request GPIO_FET_SWITCH_CTRL request_and_set_gpio: Unable to request GPIO_PHY_RESET This issue comes from the fact that the clock controller is not probed. Enable the TI's clock controller driver support to solve this. Signed-off-by: Amjad Ouled-Ameur --- configs/am335x_evm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 0f938e7de3..4dc5d0fe34 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -48,6 +48,7 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y +CONFIG_CLK_TI_CTRL=y CONFIG_DFU_TFTP=y CONFIG_DFU_MMC=y CONFIG_DFU_NAND=y From 4f03a4c7662e79634bc133a2975cc239486237da Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 11 Oct 2021 11:11:41 -0400 Subject: [PATCH 215/228] tools: Stop re-defining -std= when building tools While we intentionally set -std=gnu11 for building host tools, and have for quite some time, we never dropped -std=gnu99 from tools/Makefile. This resulted in passing -std=gnu11 ... -std=gnu99 when building, and gnu99 would win. This in turn would result now in warnings such as: tools/mkeficapsule.c:25:15: warning: redefinition of typedef 'u32' is a C11 feature [-Wtypedef-redefinition] typedef __u32 u32; ^ Signed-off-by: Tom Rini --- Makefile | 2 -- tools/Makefile | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 32d29b87db..6f2474baeb 100644 --- a/Makefile +++ b/Makefile @@ -299,9 +299,7 @@ KBUILD_HOSTLDLIBS := $(HOST_LFS_LIBS) $(HOSTLDLIBS) # have older compilers as their default, so we make it explicit for # these that our host tools are GNU11 (i.e. C11 w/ GNU extensions). CSTD_FLAG := -std=gnu11 -ifeq ($(HOSTOS),linux) KBUILD_HOSTCFLAGS += $(CSTD_FLAG) -endif ifeq ($(HOSTOS),cygwin) KBUILD_HOSTCFLAGS += -ansi diff --git a/tools/Makefile b/tools/Makefile index 999fd46531..b45219e2c3 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -295,8 +295,7 @@ HOST_EXTRACFLAGS += -include $(srctree)/include/compiler.h \ -I$(srctree)/tools \ -DUSE_HOSTCC \ -D__KERNEL_STRICT_NAMES \ - -D_GNU_SOURCE \ - -std=gnu99 + -D_GNU_SOURCE __build: $(LOGO-y) From b20b16a794b073807ef8d6840772a92788b3e226 Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Tue, 12 Oct 2021 13:43:16 +0100 Subject: [PATCH 216/228] arm: total_compute: increase DRAM to 8GB The extra 6GB start at 0x8080000000. Signed-off-by: Usama Arif --- board/armltd/total_compute/total_compute.c | 3 +++ include/configs/total_compute.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index b7eaab0851..b7772f79a3 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -59,6 +59,9 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + return 0; } diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index bbeedaf841..933a145f99 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -30,6 +30,9 @@ #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_2 0x8080000000 +#define PHYS_SDRAM_2_SIZE 0x180000000 + #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 #define CONFIG_EXTRA_ENV_SETTINGS \ From 17864406a4aa3286a8e9db6f577105e3e647c65f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 12 Oct 2021 19:40:29 -0500 Subject: [PATCH 217/228] clk: fixed_rate: add dummy disable() function commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function") implemented .enable, so fixed rate clocks can be used where drivers might call clk_enable(). Implement the .disable op for the same reason; some drivers, e.g. USB PHYs, may attempt to disable clocks at runtime. Signed-off-by: Samuel Holland --- drivers/clk/clk_fixed_rate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index e0dc4ab85f..c5a2a42c92 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -26,6 +26,7 @@ static int dummy_enable(struct clk *clk) const struct clk_ops clk_fixed_rate_ops = { .get_rate = clk_fixed_rate_get_rate, .enable = dummy_enable, + .disable = dummy_enable, }; void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, From a0cfe137157243d9cfcc928e0939b3d65274b554 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 11 Sep 2021 22:31:23 +0800 Subject: [PATCH 218/228] board: sifive: Fix a potential build warning in board_fdt_blob_setup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 47d73ba4f4a4 ("board: sifive: overwrite board_fdt_blob_setup in u-boot proper") added a board-specific implementation of board_fdt_blob_setup() which takes a pointer as the return value, but it does not return anything if CONFIG_OF_SEPARATE is not enabled. This will cause a build warning seen when testing booting S-mode U-Boot directly from QEMU, per the instructions in [1]: board/sifive/unleashed/unleashed.c: In function ‘board_fdt_blob_setup’: board/sifive/unleashed/unleashed.c:125:1: warning: control reaches end of non-void function [-Wreturn-type] Return &_end as the default case. [1] https://qemu.readthedocs.io/en/latest/system/riscv/sifive_u.html#running-u-boot Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- board/sifive/unleashed/unleashed.c | 4 ++-- board/sifive/unmatched/unmatched.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index 8cd514df30..33baeda986 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -119,9 +119,9 @@ void *board_fdt_blob_setup(void) if (IS_ENABLED(CONFIG_OF_SEPARATE)) { if (gd->arch.firmware_fdt_addr) return (ulong *)gd->arch.firmware_fdt_addr; - else - return (ulong *)&_end; } + + return (ulong *)&_end; } int board_init(void) diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index d90b252bae..8773b660fa 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -16,9 +16,9 @@ void *board_fdt_blob_setup(void) if (IS_ENABLED(CONFIG_OF_SEPARATE)) { if (gd->arch.firmware_fdt_addr) return (ulong *)gd->arch.firmware_fdt_addr; - else - return (ulong *)&_end; } + + return (ulong *)&_end; } int board_init(void) From 2fb91a2ea74e87d5e26e95f602c9f8e3951a35cf Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:08 +0800 Subject: [PATCH 219/228] cache: sifive: Fix -Wint-to-pointer-cast warning The following warning is seen in cache-sifive-ccache.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Fix by casting it with uintptr_t. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- drivers/cache/cache-sifive-ccache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c index 76c0ab26ae..c8766f6242 100644 --- a/drivers/cache/cache-sifive-ccache.c +++ b/drivers/cache/cache-sifive-ccache.c @@ -38,7 +38,7 @@ static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info) { struct sifive_ccache *priv = dev_get_priv(dev); - info->base = (phys_addr_t)priv->base; + info->base = (uintptr_t)priv->base; return 0; } From 2edb02ead760630a6495d4e583e2364d10cb850a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:09 +0800 Subject: [PATCH 220/228] clk: sifive: Fix -Wint-to-pointer-cast warning dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and pd->va is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-prci.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/sifive/sifive-prci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index cd1acb9442..52ae268e0c 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -653,9 +653,9 @@ static int sifive_prci_probe(struct udevice *dev) struct prci_clk_desc *data = (struct prci_clk_desc *)dev_get_driver_data(dev); - pd->va = (void *)dev_read_addr(dev); - if (IS_ERR(pd->va)) - return PTR_ERR(pd->va); + pd->va = dev_read_addr_ptr(dev); + if (!pd->va) + return -EINVAL; err = clk_get_by_index(dev, 0, &pd->parent_hfclk); if (err) From d710c7e84187088cb157ab4131ca50a1236a931a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:10 +0800 Subject: [PATCH 221/228] gpio: sifive: Fix -Wint-to-pointer-cast warning dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and plat->base is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-gpio.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- drivers/gpio/sifive-gpio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/sifive-gpio.c b/drivers/gpio/sifive-gpio.c index abd1f629b9..151f484e8f 100644 --- a/drivers/gpio/sifive-gpio.c +++ b/drivers/gpio/sifive-gpio.c @@ -157,13 +157,11 @@ static const struct dm_gpio_ops sifive_gpio_ops = { static int sifive_gpio_of_to_plat(struct udevice *dev) { struct sifive_gpio_plat *plat = dev_get_plat(dev); - fdt_addr_t addr; - addr = dev_read_addr(dev); - if (addr == FDT_ADDR_T_NONE) + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) return -EINVAL; - plat->base = (void *)addr; return 0; } From 7e22c85918e68e6df50d01d08585f88fbbaf3456 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:11 +0800 Subject: [PATCH 222/228] i2c: ocores: Fix -Wint-to-pointer-cast warning The following warning is seen in ocores_i2c.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- drivers/i2c/ocores_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index f129ec3818..3b19ba78fa 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -516,7 +516,7 @@ static int ocores_i2c_probe(struct udevice *dev) u32 clock_frequency_khz; int ret; - bus->base = (void __iomem *)devfdt_get_addr(dev); + bus->base = dev_read_addr_ptr(dev); if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) { /* no 'reg-shift', check for deprecated 'regstep' */ From fb9bec8e8a7378d921478d5fbcc941e0fa80c01e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:12 +0800 Subject: [PATCH 223/228] dm: core: Add a new API devfdt_get_addr_index_ptr() At present there is only devfdt_get_addr_ptr() which only returns the first pair in the 'reg' property. Add a new API devfdt_get_addr_index_ptr() to return the indexed pointer. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- drivers/core/fdtaddr.c | 11 ++++++++--- include/dm/fdtaddr.h | 12 ++++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 6dfda20772..c3a50a2b0c 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -93,6 +93,13 @@ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) #endif } +void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index) +{ + fdt_addr_t addr = devfdt_get_addr_index(dev, index); + + return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr; +} + fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size) { @@ -155,9 +162,7 @@ fdt_addr_t devfdt_get_addr(const struct udevice *dev) void *devfdt_get_addr_ptr(const struct udevice *dev) { - fdt_addr_t addr = devfdt_get_addr_index(dev, 0); - - return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr; + return devfdt_get_addr_index_ptr(dev, 0); } void *devfdt_remap_addr_index(const struct udevice *dev, int index) diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h index a4fda581a7..d2c1994291 100644 --- a/include/dm/fdtaddr.h +++ b/include/dm/fdtaddr.h @@ -92,6 +92,18 @@ void *devfdt_map_physmem(const struct udevice *dev, unsigned long size); */ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index); +/** + * devfdt_get_addr_index_ptr() - Return indexed pointer to the address of the + * reg property of a device + * + * @dev: Pointer to a device + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * + * @return Pointer to addr, or NULL if there is no such property + */ +void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index); + /** * devfdt_get_addr_size_index() - Get the indexed reg property of a device * From bdce903106397add4283b713132e24972a6ac0ee Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:13 +0800 Subject: [PATCH 224/228] dm: Provide dev_read_addr_index_ptr() wrapper Like dev_read_addr_ptr(), provide a wrapper for the indexed version. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Simon Glass --- include/dm/read.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/dm/read.h b/include/dm/read.h index 5bf3405614..890bf3d847 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -180,6 +180,18 @@ int dev_read_size(const struct udevice *dev, const char *propname); */ fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index); +/** + * dev_read_addr_index_ptr() - Get the indexed reg property of a device + * as a pointer + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of pairs + * and @index is used to select which one is required + * + * @return pointer or NULL if not found + */ +void *dev_read_addr_index_ptr(const struct udevice *dev, int index); + /** * dev_read_addr_size_index() - Get the indexed reg property of a device * @@ -805,6 +817,12 @@ static inline fdt_addr_t dev_read_addr_index(const struct udevice *dev, return devfdt_get_addr_index(dev, index); } +static inline void *dev_read_addr_index_ptr(const struct udevice *dev, + int index) +{ + return devfdt_get_addr_index_ptr(dev, index); +} + static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size) From b422ed05f7035c5a6da527ab859bc008cb38ef14 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:14 +0800 Subject: [PATCH 225/228] net: macb: Fix -Wint-to-pointer-cast warnings The following warning is seen in macb.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_index_ptr(), or cast with uintptr_t. Signed-off-by: Bin Meng Reviewed-by: Ramon Fried --- drivers/net/macb.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 8151104acf..8c6461e717 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -574,14 +574,9 @@ static int macb_phy_find(struct macb_device *macb, const char *name) #ifdef CONFIG_DM_ETH static int macb_sifive_clk_init(struct udevice *dev, ulong rate) { - fdt_addr_t addr; void *gemgxl_regs; - addr = dev_read_addr_index(dev, 1); - if (addr == FDT_ADDR_T_NONE) - return -ENODEV; - - gemgxl_regs = (void __iomem *)addr; + gemgxl_regs = dev_read_addr_index_ptr(dev, 1); if (!gemgxl_regs) return -ENODEV; @@ -1383,7 +1378,7 @@ static int macb_eth_probe(struct udevice *dev) macb->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", -1); - macb->regs = (void *)pdata->iobase; + macb->regs = (void *)(uintptr_t)pdata->iobase; macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678); @@ -1444,7 +1439,7 @@ static int macb_eth_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); - pdata->iobase = (phys_addr_t)dev_remap_addr(dev); + pdata->iobase = (uintptr_t)dev_remap_addr(dev); if (!pdata->iobase) return -EINVAL; From d36c94279dd4fceab928cf60947ad876284de86a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:15 +0800 Subject: [PATCH 226/228] ram: sifive: Fix -Wint-to-pointer-cast warnings The following warning is seen in sifive_ddr.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_index_ptr(). Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- drivers/ram/sifive/sifive_ddr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c index ba18466033..4bd69a62be 100644 --- a/drivers/ram/sifive/sifive_ddr.c +++ b/drivers/ram/sifive/sifive_ddr.c @@ -313,7 +313,7 @@ static int sifive_ddr_setup(struct udevice *dev) sifive_ddr_phy_fixup(denali_phy); /* check size */ - priv->info.size = get_ram_size((long *)priv->info.base, + priv->info.size = get_ram_size((long *)(uintptr_t)priv->info.base, ddr_size); debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size); @@ -369,9 +369,9 @@ static int sifive_ddr_probe(struct udevice *dev) return ret; } - priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0); - priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1); - priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2); + priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index_ptr(dev, 0); + priv->phy = (struct sifive_ddrphy *)dev_read_addr_index_ptr(dev, 1); + priv->physical_filter_ctrl = (u32 *)dev_read_addr_index_ptr(dev, 2); return sifive_ddr_setup(dev); #endif From b18c4ae82f266d81281d63ac58945d92ed67afde Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 12 Sep 2021 11:15:16 +0800 Subject: [PATCH 227/228] board: sifive: Fix -Wint-to-pointer-cast warning The following warning is seen in unleashed.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Cast with uintptr_t. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- board/sifive/unleashed/unleashed.c | 2 +- board/sifive/unmatched/unmatched.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index 33baeda986..e7d2332d8c 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -118,7 +118,7 @@ void *board_fdt_blob_setup(void) { if (IS_ENABLED(CONFIG_OF_SEPARATE)) { if (gd->arch.firmware_fdt_addr) - return (ulong *)gd->arch.firmware_fdt_addr; + return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; } return (ulong *)&_end; diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index 8773b660fa..93c452c57f 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -15,7 +15,7 @@ void *board_fdt_blob_setup(void) { if (IS_ENABLED(CONFIG_OF_SEPARATE)) { if (gd->arch.firmware_fdt_addr) - return (ulong *)gd->arch.firmware_fdt_addr; + return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr; } return (ulong *)&_end; From ddf4972834fdf33f0a3360ff4a68fde333995113 Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Mon, 18 Oct 2021 11:50:05 +0800 Subject: [PATCH 228/228] riscv: Avoid io read/write cause wrong result io read/write may cause wrong result because they may read/write data from/to register instead of memory. Add 'volatile' to avoid it. Signed-off-by: Nick Hu Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Bin Meng --- arch/riscv/include/asm/io.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index acf5a96449..3540773c4f 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -44,15 +44,15 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) * read/writes. We define __arch_*[bl] here, and leave __arch_*w * to the architecture specific code. */ -#define __arch_getb(a) (*(unsigned char *)(a)) -#define __arch_getw(a) (*(unsigned short *)(a)) -#define __arch_getl(a) (*(unsigned int *)(a)) -#define __arch_getq(a) (*(unsigned long long *)(a)) +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) +#define __arch_getq(a) (*(volatile unsigned long long *)(a)) -#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) -#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) -#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) -#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v)) +#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) +#define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v)) #define __raw_writeb(v, a) __arch_putb(v, a) #define __raw_writew(v, a) __arch_putw(v, a)