Das U-Boot: Universal Boot Loader
This commit is contained in:
wdenk
85
include/asm-ppc/u-boot.h
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85
include/asm-ppc/u-boot.h
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@@ -0,0 +1,85 @@
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/*
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* (C) Copyright 2000 - 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __U_BOOT_H__
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#define __U_BOOT_H__
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/*
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* Board information passed to Linux kernel from U-Boot
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*
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* include/asm-ppc/u-boot.h
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*/
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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typedef struct bd_info {
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unsigned long bi_memstart; /* start of DRAM memory */
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unsigned long bi_memsize; /* size of DRAM memory in bytes */
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unsigned long bi_flashstart; /* start of FLASH memory */
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unsigned long bi_flashsize; /* size of FLASH memory */
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unsigned long bi_flashoffset; /* reserved area for startup monitor */
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unsigned long bi_sramstart; /* start of SRAM memory */
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unsigned long bi_sramsize; /* size of SRAM memory */
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#if defined(CONFIG_8xx) || defined(CONFIG_8260)
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unsigned long bi_immr_base; /* base of IMMR register */
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#endif
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unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
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unsigned long bi_ip_addr; /* IP Address */
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unsigned char bi_enetaddr[6]; /* Ethernet adress */
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unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
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unsigned long bi_intfreq; /* Internal Freq, in MHz */
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unsigned long bi_busfreq; /* Bus Freq, in MHz */
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#if defined(CONFIG_8260)
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unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
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unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
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unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
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unsigned long bi_vco; /* VCO Out from PLL, in MHz */
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#endif
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unsigned long bi_baudrate; /* Console Baudrate */
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#if defined(CONFIG_405GP) || \
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defined(CONFIG_405CR) || \
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defined(CONFIG_440) || \
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defined(CONFIG_405)
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unsigned char bi_s_version[4]; /* Version of this structure */
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unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
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unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
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unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
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unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
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unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
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#endif
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#if defined(CONFIG_HYMOD)
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hymod_conf_t bi_hymod_conf; /* hymod configuration information */
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#endif
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#if defined(CONFIG_EVB64260) || defined(CONFIG_PN62)
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/* second onboard ethernet port */
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unsigned char bi_enet1addr[6];
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#endif
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#if defined(CONFIG_EVB64260)
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/* third onboard ethernet port */
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unsigned char bi_enet2addr[6];
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#endif
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#if defined(CONFIG_NX823)
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unsigned char bi_sernum[8];
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#endif
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} bd_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __U_BOOT_H__ */
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470
include/configs/FADS823.h
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470
include/configs/FADS823.h
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@@ -0,0 +1,470 @@
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/*
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T FADS board. Copied from the MBX stuff.
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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/*
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* 1999-nov-26: The FADS is using the following physical memorymap:
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*
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* ff020000 -> ff02ffff : pcmcia io remapping
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* ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
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* ff000000 -> ff00ffff : IMAP internal in the cpu
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* e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
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* fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
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* 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
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*/
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#define CFG_PCMCIA_IO_ADDR 0xff020000
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#define CFG_PCMCIA_IO_SIZE 0x10000
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#define CFG_PCMCIA_MEM_ADDR 0xe0000000
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#define CFG_PCMCIA_MEM_SIZE 0x10000
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#define CFG_IMMR 0xFF000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x02800000
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#define BCSR_ADDR ((uint) 0xff010000)
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#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
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#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
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#define CONFIG_VIDEO 1 /* To enable video controller support */
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#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*Now included by CFG_CMD_PCMCIA */
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/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
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/* Video related */
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#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
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#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
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#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
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#define CONFIG_VIDEO_SIZE (2*1024*1024)
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/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
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/* Wireless 56Khz 4PPM keyboard on SMCx */
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/*#define CONFIG_WL_4PPM_KEYBOARD 1 */
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#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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#define CONFIG_MPC823 1
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#define CONFIG_MPC823FADS 1
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#define CONFIG_FADS 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200
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/* Set the CPU speed to 50Mhz on the FADS */
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#if 0
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 5000000 /* 5 MHz in */
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#else
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 5000000 /* 5 MHz in */
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#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
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#endif
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 1
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#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
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#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
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#define CONFIG_BOOTARGS ""
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#define CONFIG_BOOTCOMMAND \
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"bootp ;" \
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"setenv bootargs console=tty0 console=ttyS0 " \
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"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \
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"bootm"
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#else
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#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT ":>" /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
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#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
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*/
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#if 0
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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||||
/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
|
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer *
|
||||
* interrupt status bit - leave PLL multiplication factor unchanged !
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||||
*/
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
|
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* Set clock output, timebase and RTC source and divider,
|
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* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_DER 0
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||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller
|
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* differently. Normally, you write the option register
|
||||
* first, and then enable the chip select by writing the
|
||||
* base register. For CS0, you must write the base register
|
||||
* first, followed by the option register.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
/* the other CS:s are determined by looking at parameters in BCSRx */
|
||||
|
||||
#define BCSR_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
|
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||
|
||||
/* BCSRx - Board Control and Status Registers */
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
|
||||
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
|
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
#define CFG_MAMR 0x13a01114
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/* values according to the manual */
|
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00))
|
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
|
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
|
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description
|
||||
* of the following structures
|
||||
*/
|
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000)
|
||||
#define BCSR0_IP ((uint)0x40000000)
|
||||
#define BCSR0_BDIS ((uint)0x10000000)
|
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000)
|
||||
#define BCSR0_ISB_MASK ((uint)0x01800000)
|
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000)
|
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000)
|
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000)
|
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000)
|
||||
#define BCSR1_DRAM_EN ((uint)0x40000000)
|
||||
#define BCSR1_ETHEN ((uint)0x20000000)
|
||||
#define BCSR1_IRDEN ((uint)0x10000000)
|
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
|
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
|
||||
#define BCSR1_BCSR_EN ((uint)0x02000000)
|
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000)
|
||||
#define BCSR1_PCCEN ((uint)0x00800000)
|
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000)
|
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
|
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
|
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000)
|
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000)
|
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000)
|
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
|
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
|
||||
#define BCSR2_DRAM_PD_SHIFT (23)
|
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
|
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
|
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800)
|
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
|
||||
#define BCSR3_BREVNR0 ((ushort)0x0080)
|
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
|
||||
#define BCSR3_BREVN1 ((ushort)0x0008)
|
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003)
|
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000)
|
||||
#define BCSR4_TFPLDL ((uint)0x40000000)
|
||||
#define BCSR4_TPSQEL ((uint)0x20000000)
|
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_USB_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860SAR
|
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC860SAR */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETH_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_USB_SPEED ((uint)0x04000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHCFG0 ((uint)0x04000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VCCO ((uint)0x02000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHFDE ((uint)0x02000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHCFG1 ((uint)0x00400000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETHRST ((uint)0x00200000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_MODEM_EN ((uint)0x00100000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC850
|
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
||||
#endif /* CONFIG_MPC850 */
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ
|
||||
|
||||
#ifdef CONFIG_MPC860T
|
||||
|
||||
/* Interrupt level assignments.
|
||||
*/
|
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
|
||||
|
||||
#endif /* CONFIG_MPC860T */
|
||||
|
||||
/* We don't use the 8259.
|
||||
*/
|
||||
#define NR_8259_INTS 0
|
||||
|
||||
/* Machine type
|
||||
*/
|
||||
#define _MACH_8xx (_MACH_fads)
|
||||
|
||||
/*
|
||||
* MPC8xx CPM Options
|
||||
*/
|
||||
#define CONFIG_SCC_ENET 1
|
||||
#define CONFIG_SCC2_ENET 1
|
||||
#undef CONFIG_FEC_ENET
|
||||
#undef CONFIG_CPM_IIC
|
||||
#undef CONFIG_UCODE_PATCH
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
|
||||
/* PCMCIA configuration */
|
||||
|
||||
#define PCMCIA_MAX_SLOTS 1
|
||||
|
||||
#ifdef CONFIG_MPC860
|
||||
#define PCMCIA_SLOT_A 1
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
717
include/configs/GEN860T.h
Normal file
717
include/configs/GEN860T.h
Normal file
@@ -0,0 +1,717 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Keith Outwater, keith_outwater@mvis.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config_GEN860T.h - board specific configuration options
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_GEN860T_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_MPC860
|
||||
#define CONFIG_GEN860T
|
||||
|
||||
/*
|
||||
* Identify the board
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING " GEN860T"
|
||||
|
||||
/*
|
||||
* Don't depend on the RTC clock to determine clock frequency -
|
||||
* the 860's internal rtc uses a 32.768 KHz clock which is
|
||||
* generated by the DS1337 - and the DS1337 clock can be turned off.
|
||||
*/
|
||||
#define CONFIG_8xx_GCLK_FREQ 66600000
|
||||
|
||||
/*
|
||||
* The RS-232 console port is on SMC1
|
||||
*/
|
||||
#define CONFIG_8xx_CONS_SMC1
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
/*
|
||||
* Set allowable console baud rates
|
||||
*/
|
||||
#define CFG_BAUDRATE_TABLE { 9600, \
|
||||
19200, \
|
||||
38400, \
|
||||
57600, \
|
||||
115200, \
|
||||
}
|
||||
|
||||
/*
|
||||
* Print console information
|
||||
*/
|
||||
#undef CFG_CONSOLE_INFO_QUIET
|
||||
|
||||
/*
|
||||
* Set the autoboot delay in seconds. A delay of -1 disables autoboot
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
/*
|
||||
* Pass the clock frequency to the Linux kernel in units of MHz
|
||||
*/
|
||||
#define CONFIG_CLOCKS_IN_MHZ
|
||||
|
||||
#define CONFIG_PREBOOT \
|
||||
"echo;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm"
|
||||
|
||||
/*
|
||||
* Turn off echo for serial download by default. Allow baud rate to be changed
|
||||
* for downloads
|
||||
*/
|
||||
#undef CONFIG_LOADS_ECHO
|
||||
#define CFG_LOADS_BAUD_CHANGE
|
||||
|
||||
/*
|
||||
* Set default load address for tftp network downloads
|
||||
*/
|
||||
#define CFG_TFTP_LOADADDR 0x01000000
|
||||
|
||||
/*
|
||||
* Turn off the watchdog timer
|
||||
*/
|
||||
#undef CONFIG_WATCHDOG
|
||||
|
||||
/*
|
||||
* Do not reboot if a panic occurs
|
||||
*/
|
||||
#define CONFIG_PANIC_HANG
|
||||
|
||||
/*
|
||||
* Enable the status LED
|
||||
*/
|
||||
#define CONFIG_STATUS_LED
|
||||
|
||||
/*
|
||||
* Reset address. We pick an address such that when an instruction
|
||||
* is executed at that address, a machine check exception occurs
|
||||
*/
|
||||
#define CFG_RESET_ADDRESS ((ulong) -1)
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
|
||||
CONFIG_BOOTP_BOOTFILESIZE \
|
||||
)
|
||||
|
||||
/*
|
||||
* The GEN860T network interface uses the on-chip 10/100 FEC with
|
||||
* an Intel LXT971A PHY connected to the 860T's MII. The PHY's
|
||||
* MII address is hardwired on the board to zero.
|
||||
*/
|
||||
#define CONFIG_FEC_ENET
|
||||
#define CFG_DISCOVER_PHY
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
|
||||
/*
|
||||
* Set default IP stuff just to get bootstrap entries into the
|
||||
* environment so that we can autoscript the full default environment.
|
||||
*/
|
||||
#define CONFIG_ETHADDR 9a:52:63:15:85:25
|
||||
#define CONFIG_SERVERIP 10.0.4.200
|
||||
#define CONFIG_IPADDR 10.0.4.111
|
||||
|
||||
/*
|
||||
* This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
|
||||
* the MPC860T I2C interface.
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
|
||||
#define CFG_ENV_EEPROM_SIZE (32 * 1024)
|
||||
|
||||
#undef CONFIG_HARD_I2C
|
||||
#define CONFIG_SOFT_I2C
|
||||
|
||||
/*
|
||||
* Configure software I2C support (taken from IP860 BSP).
|
||||
* The I2C bus is connected to the GEN860T's 'dedicated' I2C
|
||||
* pins, i.e. PB26 and PB27
|
||||
*/
|
||||
#define PB_SCL 0x00000020 /* PB 26 */
|
||||
#define PB_SDA 0x00000010 /* PB 27 */
|
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
|
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
|
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
|
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
|
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA
|
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
|
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
|
||||
#define CFG_I2C_SLAVE 0xFE /* I2C slave address */
|
||||
|
||||
/*
|
||||
* Allow environment overwrites by anyone
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* The MPC860's internal RTC is horribly broken in rev D masks. Three
|
||||
* internal MPC860T circuit nodes were inadvertently left floating; this
|
||||
* causes KAPWR current in power down mode to be three orders of magnitude
|
||||
* higher than specified in the datasheet (from 10 uA to 10 mA). No
|
||||
* reasonable battery can keep that kind RTC running during powerdown for any
|
||||
* length of time, so we use an external RTC on the I2C bus instead.
|
||||
*/
|
||||
#undef CONFIG_RTC_MPC8xx
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CFG_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* Allow partial commands to be matched to uniqueness.
|
||||
*/
|
||||
#define CFG_MATCH_PARTIAL_CMD
|
||||
|
||||
/*
|
||||
* List of available monitor commands. Use the system default list
|
||||
* plus add some of the "non-standard" commands back in.
|
||||
* See ./cmd_confdefs.h
|
||||
*/
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_IMMAP | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_FPGA | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_BEDBUG \
|
||||
)
|
||||
|
||||
/*
|
||||
* There is no IDE/PCMCIA hardware support on the board.
|
||||
*/
|
||||
#undef CONFIG_IDE_PCMCIA
|
||||
#undef CONFIG_IDE_LED
|
||||
#undef CONFIG_IDE_RESET
|
||||
|
||||
/*
|
||||
* Enable the call to misc_init_r() for miscellaneous platform
|
||||
* dependent initialization.
|
||||
*/
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/*
|
||||
* Enable call to last_stage_init() so we can twiddle some LEDS :)
|
||||
*/
|
||||
#define CONFIG_LAST_STAGE_INIT
|
||||
|
||||
/*
|
||||
* Virtex2 FPGA configuration support
|
||||
*/
|
||||
#define CONFIG_FPGA_COUNT 1
|
||||
#define CONFIG_FPGA CFG_XILINX_VIRTEX2
|
||||
#define CFG_FPGA_PROG_FEEDBACK
|
||||
|
||||
|
||||
/************************************************************************
|
||||
* This must be included AFTER the definition of any CONFIG_COMMANDS
|
||||
*/
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Verbose help from command monitor.
|
||||
*/
|
||||
#define CFG_LONGHELP
|
||||
#define CFG_PROMPT "gen860t> "
|
||||
|
||||
/*
|
||||
* Use the "hush" command parser
|
||||
*/
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* Set buffer size for console I/O
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024
|
||||
#else
|
||||
#define CFG_CBSIZE 256
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Print buffer size
|
||||
*/
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
|
||||
|
||||
/*
|
||||
* Maximum number of arguments that a command can accept
|
||||
*/
|
||||
#define CFG_MAXARGS 16
|
||||
|
||||
/*
|
||||
* Boot argument buffer size
|
||||
*/
|
||||
#define CFG_BARGSIZE CFG_CBSIZE
|
||||
|
||||
/*
|
||||
* Default memory test range
|
||||
*/
|
||||
#define CFG_MEMTEST_START 0x0100000
|
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
|
||||
|
||||
/*
|
||||
* Select the more full-featured memory test
|
||||
*/
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
/*
|
||||
* Default load address
|
||||
*/
|
||||
#define CFG_LOAD_ADDR 0x01000000
|
||||
|
||||
/*
|
||||
* Set decrementer frequency (1 ms ticks)
|
||||
*/
|
||||
#define CFG_HZ 1000
|
||||
|
||||
/*
|
||||
* Device memory map (after SDRAM remap to 0x0):
|
||||
*
|
||||
* CS Device Base Addr Size
|
||||
* ----------------------------------------------------
|
||||
* CS0* Flash 0x40000000 64 M
|
||||
* CS1* SDRAM 0x00000000 16 M
|
||||
* CS2* Disk-On-Chip 0x50000000 32 K
|
||||
* CS3* FPGA 0x60000000 64 M
|
||||
* CS4* SelectMap 0x70000000 32 K
|
||||
* CS5* Mil-Std 1553 I/F 0x80000000 32 K
|
||||
* CS6* Unused
|
||||
* CS7* Unused
|
||||
* IMMR 860T Registers 0xfff00000
|
||||
*/
|
||||
|
||||
/*
|
||||
* Base addresses and block sizes
|
||||
*/
|
||||
#define CFG_IMMR 0xFF000000
|
||||
|
||||
#define SDRAM_BASE 0x00000000
|
||||
#define SDRAM_SIZE (64 * 1024 * 1024)
|
||||
|
||||
#define FLASH_BASE 0x40000000
|
||||
#define FLASH_SIZE (16 * 1024 * 1024)
|
||||
|
||||
#define DOC_BASE 0x50000000
|
||||
#define DOC_SIZE (32 * 1024)
|
||||
|
||||
#define FPGA_BASE 0x60000000
|
||||
#define FPGA_SIZE (64 * 1024 * 1024)
|
||||
|
||||
#define SELECTMAP_BASE 0x70000000
|
||||
#define SELECTMAP_SIZE (32 * 1024)
|
||||
|
||||
#define M1553_BASE 0x80000000
|
||||
#define M1553_SIZE (64 * 1024)
|
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE SDRAM_BASE
|
||||
|
||||
/*
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_BASE FLASH_BASE
|
||||
#define CFG_FLASH_SIZE FLASH_SIZE
|
||||
#define CFG_FLASH_SECT_SIZE (128 * 1024)
|
||||
#define CFG_MAX_FLASH_BANKS 1
|
||||
#define CFG_MAX_FLASH_SECT 128
|
||||
|
||||
/*
|
||||
* The timeout values are for an entire chip and are in milliseconds.
|
||||
* Yes I know that the write timeout is huge. Accroding to the
|
||||
* datasheet a single byte takes 630 uS (round to 1 ms) max at worst
|
||||
* case VCC and temp after 100K programming cycles. It works out
|
||||
* to 280 minutes (might as well be forever).
|
||||
*/
|
||||
#define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
|
||||
#define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
|
||||
|
||||
/*
|
||||
* Allow direct writes to FLASH from tftp transfers (** dangerous **)
|
||||
*/
|
||||
#define CFG_DIRECT_FLASH_TFTP
|
||||
|
||||
/*
|
||||
* Reserve memory for U-Boot.
|
||||
*/
|
||||
#define CFG_MAX_U_BOOT_SECT 3
|
||||
|
||||
#if defined(DEBUG)
|
||||
#define CFG_MONITOR_LEN (512 * 1024)
|
||||
#else
|
||||
#define CFG_MONITOR_LEN (256 * 1024)
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
|
||||
/*
|
||||
* Select environment placement. NOTE that u-boot.lds must
|
||||
* be edited if this is changed!
|
||||
*/
|
||||
#undef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_IS_IN_EEPROM
|
||||
|
||||
#if defined(CFG_ENV_IS_IN_EEPROM)
|
||||
#define CFG_ENV_SIZE (2 * 1024)
|
||||
#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
|
||||
#else
|
||||
#define CFG_ENV_SIZE (4 * 1024)
|
||||
#define CFG_ENV_OFFSET (CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Reserve memory for malloc()
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (128 * 1024)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control UM 11-9
|
||||
* -----------------------------------------------------------------------
|
||||
* SYPCR can only be written once after reset!
|
||||
*
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR ( SYPCR_SWTC | \
|
||||
SYPCR_BMT | \
|
||||
SYPCR_BME | \
|
||||
SYPCR_SWF | \
|
||||
SYPCR_SWE | \
|
||||
SYPCR_SWRI | \
|
||||
SYPCR_SWP \
|
||||
)
|
||||
#else
|
||||
#define CFG_SYPCR ( SYPCR_SWTC | \
|
||||
SYPCR_BMT | \
|
||||
SYPCR_BME | \
|
||||
SYPCR_SWF | \
|
||||
SYPCR_SWP \
|
||||
)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration UM 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* Set debug pin mux, enable SPKROUT and GPLB5*.
|
||||
*/
|
||||
#define CFG_SIUMCR ( SIUMCR_DBGC11 | \
|
||||
SIUMCR_DBPC11 | \
|
||||
SIUMCR_MLRC11 | \
|
||||
SIUMCR_GB5E \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control UM 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freeze enabled
|
||||
*/
|
||||
#define CFG_TBSCR ( TBSCR_REFA | \
|
||||
TBSCR_REFB | \
|
||||
TBSCR_TBF \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register UM 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RTCSC ( RTCSC_SEC | \
|
||||
RTCSC_ALR | \
|
||||
RTCSC_RTF | \
|
||||
RTCSC_RTE \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control UM 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR ( PISCR_PS | \
|
||||
PISCR_PITF \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit. Set MF for 1:2:1 mode.
|
||||
*/
|
||||
#define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
|
||||
PLPRCR_SPLSS | \
|
||||
PLPRCR_TEXPS | \
|
||||
PLPRCR_TMIST \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register UM 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
|
||||
#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
|
||||
SCCR_COM00 | /* full strength CLKOUT */ \
|
||||
SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
|
||||
SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
|
||||
SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 \
|
||||
)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DER - Debug Enable Register UM 37-46
|
||||
*-----------------------------------------------------------------------
|
||||
* Mask all events that can cause entry into debug mode
|
||||
*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Initialize Memory Controller:
|
||||
*
|
||||
* BR0 and OR0 (FLASH memory)
|
||||
*/
|
||||
#define FLASH_BASE0_PRELIM FLASH_BASE
|
||||
|
||||
/*
|
||||
* Flash address mask
|
||||
*/
|
||||
#define CFG_PRELIM_OR_AM 0xfe000000
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
* 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
|
||||
*/
|
||||
#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
|
||||
OR_ACS_DIV2 | \
|
||||
OR_BI | \
|
||||
OR_SCY_2_CLK | \
|
||||
OR_TRLX | \
|
||||
OR_EHTR \
|
||||
)
|
||||
|
||||
#define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
|
||||
CFG_OR_TIMING_FLASH \
|
||||
)
|
||||
|
||||
#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
|
||||
BR_MS_GPCM | \
|
||||
BR_PS_8 | \
|
||||
BR_V \
|
||||
)
|
||||
|
||||
/*
|
||||
* SDRAM configuration
|
||||
*/
|
||||
#define CFG_OR1_AM 0xfc000000
|
||||
#define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
|
||||
OR_CSNT_SAM \
|
||||
)
|
||||
|
||||
#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
|
||||
BR_MS_UPMA | \
|
||||
BR_PS_32 | \
|
||||
BR_V \
|
||||
)
|
||||
|
||||
/*
|
||||
* Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
|
||||
* of 256 MBit SDRAM
|
||||
*/
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
|
||||
|
||||
/*
|
||||
* Periodic timer for refresh @ 33 MHz system clock
|
||||
*/
|
||||
#define CFG_MAMR_PTA 64
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
|
||||
MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | \
|
||||
MAMR_DSA_1_CYCL | \
|
||||
MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | \
|
||||
MAMR_WLFA_1X | \
|
||||
MAMR_TLFA_4X \
|
||||
)
|
||||
|
||||
/*
|
||||
* CS2* configuration for Disk On Chip:
|
||||
* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
|
||||
* no burst.
|
||||
*/
|
||||
#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
|
||||
OR_CSNT_SAM | \
|
||||
OR_ACS_DIV2 | \
|
||||
OR_BI | \
|
||||
OR_SCY_2_CLK | \
|
||||
OR_TRLX | \
|
||||
OR_EHTR \
|
||||
)
|
||||
|
||||
#define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_GPCM | \
|
||||
BR_V \
|
||||
)
|
||||
|
||||
/*
|
||||
* CS3* configuration for FPGA:
|
||||
* 33 MHz bus with SCY=15, no burst.
|
||||
* The FPGA uses TA and TEA to terminate bus cycles, but we
|
||||
* clear SETA and set the cycle length to a large number so that
|
||||
* the cycle will still complete even if there is a configuration
|
||||
* error that prevents TA from asserting on FPGA accesss.
|
||||
*/
|
||||
#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
|
||||
OR_SCY_15_CLK | \
|
||||
OR_BI \
|
||||
)
|
||||
|
||||
#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
|
||||
BR_PS_32 | \
|
||||
BR_MS_GPCM | \
|
||||
BR_V \
|
||||
)
|
||||
/*
|
||||
* CS4* configuration for FPGA SelectMap configuration interface.
|
||||
* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
|
||||
* of GCLK1_50
|
||||
*/
|
||||
#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
|
||||
OR_G5LS | \
|
||||
OR_BI \
|
||||
)
|
||||
|
||||
#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_UPMB | \
|
||||
BR_V \
|
||||
)
|
||||
|
||||
/*
|
||||
* CS5* configuration for Mil-Std 1553 databus interface.
|
||||
* 33 MHz bus, GPCM, no burst.
|
||||
* The 1553 interface uses TA and TEA to terminate bus cycles,
|
||||
* but we clear SETA and set the cycle length to a large number so that
|
||||
* the cycle will still complete even if there is a configuration
|
||||
* error that prevents TA from asserting on FPGA accesss.
|
||||
*/
|
||||
#define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
|
||||
OR_SCY_15_CLK | \
|
||||
OR_EHTR | \
|
||||
OR_TRLX | \
|
||||
OR_CSNT_SAM | \
|
||||
OR_BI \
|
||||
)
|
||||
|
||||
#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
|
||||
BR_PS_16 | \
|
||||
BR_MS_GPCM | \
|
||||
BR_V \
|
||||
)
|
||||
|
||||
/*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*
|
||||
* Disk On Chip (millenium) configuration
|
||||
*/
|
||||
#define CFG_MAX_DOC_DEVICE 1
|
||||
#undef CFG_DOC_SUPPORT_2000
|
||||
#define CFG_DOC_SUPPORT_MILLENNIUM
|
||||
#undef CFG_DOC_PASSIVE_PROBE
|
||||
|
||||
/*
|
||||
* FEC interrupt assignment
|
||||
*/
|
||||
#define FEC_INTERRUPT SIU_LEVEL1
|
||||
|
||||
/*
|
||||
* Sanity checks
|
||||
*/
|
||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
|
||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_GEN860T_H */
|
||||
|
||||
/* vim: set ts=4 tw=78 ai shiftwidth=4: */
|
||||
348
include/configs/NETVIA.h
Normal file
348
include/configs/NETVIA.h
Normal file
@@ -0,0 +1,348 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
|
||||
* U-Boot port on NetVia board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
|
||||
#define CONFIG_NETVIA 1 /* ...on a NetVia board */
|
||||
#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
|
||||
|
||||
#ifdef CONFIG_NETVIA_PLL_CLOCK
|
||||
/* XXX make sure that you calculate these two correctly */
|
||||
#define CFG_GCLK_MF 1350
|
||||
#define CONFIG_8xx_GCLK_FREQ 44236800
|
||||
#else
|
||||
#define CFG_GCLK_MF 1
|
||||
#define CONFIG_8xx_GCLK_FREQ 50000000
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"tftpboot; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#undef CONFIG_MAC_PARTITION
|
||||
#undef CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP )
|
||||
|
||||
#define CONFIG_BOARD_PRE_INIT
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFF000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0x40000000
|
||||
#if defined(DEBUG)
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#endif
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x10000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#ifndef CONFIG_CAN_DRIVER
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
|
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
*/
|
||||
|
||||
#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
/*#define CFG_DER 0x2002000F*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
|
||||
|
||||
/*
|
||||
* BR1/2 and OR1/2 (4MByte Flash Bank x 2)
|
||||
*
|
||||
*/
|
||||
#define FLASH0_SIZE 0x00400000 /* 4MByte */
|
||||
#define FLASH0_BASE 0xF0000000
|
||||
|
||||
#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH0_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
|
||||
#define CFG_BR1_PRELIM ((FLASH0_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
|
||||
|
||||
#define FLASH1_SIZE 0x00400000
|
||||
#define FLASH1_BASE 0xF0400000
|
||||
|
||||
#define CFG_OR2_PRELIM ((0xFFFFFFFFLU & ~(FLASH1_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
|
||||
#define CFG_BR2_PRELIM ((FLASH1_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
|
||||
|
||||
/*
|
||||
* BR3 and OR3 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
|
||||
|
||||
#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
|
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
|
||||
|
||||
/*
|
||||
* BR6 (External register)
|
||||
* 16 bit port size - leds are at high 8 bits
|
||||
*/
|
||||
#define EXTREG_BASE 0x30000000 /* external register */
|
||||
#define EXTREG_SIZE 0x00010000 /* max 64K */
|
||||
|
||||
#define CFG_OR6_PRELIM ((0xFFFFFFFFLU & ~(EXTREG_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX)
|
||||
#define CFG_BR6_PRELIM ((EXTREG_BASE & BR_BA_MSK) | BR_PS_32 | BR_V)
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CFG_MAMR_PTA 208
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/* Ethernet at SCC2 */
|
||||
#define CONFIG_SCC2_ENET
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
439
include/configs/RPXClassic.h
Normal file
439
include/configs/RPXClassic.h
Normal file
@@ -0,0 +1,439 @@
|
||||
/*
|
||||
* (C) Copyright 2000, 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-Boot port on RPXlite board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define RPXClassic_50MHz
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC860 1
|
||||
#define CONFIG_RPXCLASSIC 1
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
|
||||
|
||||
|
||||
/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
|
||||
#undef CONFIG_FEC_ENET
|
||||
#ifdef CONFIG_FEC_ENET
|
||||
#define CFG_DISCOVER_PHY 1
|
||||
#endif /* CONFIG_FEC_ENET */
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK 1
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"tftpboot; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NONSTD | CFG_CMD_ELF)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_RESET_ADDRESS 0x80000000
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFA200000
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* I2C Configuration
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_I2C 1
|
||||
#define CFG_I2C_SPEED 50000
|
||||
#define CFG_I2C_SLAVE 0x34
|
||||
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00000010)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
|
||||
#define I2C_READ ((iop->pdat & 0x00000010) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
|
||||
else iop->pdat &= ~0x00000010
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
|
||||
else iop->pdat &= ~0x00000020
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
|
||||
# define CFG_I2C_SPEED 50000
|
||||
# define CFG_I2C_SLAVE 0x34
|
||||
# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
|
||||
# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFF000000
|
||||
|
||||
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
|
||||
#endif
|
||||
#define CFG_MONITOR_BASE 0xFF000000
|
||||
/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#if 0
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
#else
|
||||
#define CFG_ENV_IS_IN_NVRAM 1
|
||||
#define CFG_ENV_ADDR 0xfa000100
|
||||
#define CFG_ENV_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWP)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_MLRC10)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
/* up to 50 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF00
|
||||
/* up to 50 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
/* #define CFG_DER 0x2002000F */
|
||||
/* #define CFG_DER 0 */
|
||||
#define CFG_DER 0x0082000F
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0 and OR0 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
|
||||
#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
|
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
|
||||
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000E00
|
||||
|
||||
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
|
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/* RPXLITE mem setting */
|
||||
#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
|
||||
#define CFG_OR3_PRELIM 0xff7f8970
|
||||
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
|
||||
#define CFG_OR4_PRELIM 0xFFF80970
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CFG_MAMR_PTA 58
|
||||
|
||||
/*
|
||||
* Refresh clock Prescalar
|
||||
*/
|
||||
#define CFG_MPTPR MPTPR_PTP_DIV8
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 10 column SDRAM */
|
||||
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
|
||||
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
|
||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||||
/* Configuration variable added by yooth. */
|
||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||||
|
||||
/*
|
||||
* BCSRx
|
||||
*
|
||||
* Board Status and Control Registers
|
||||
*
|
||||
*/
|
||||
|
||||
#define BCSR0 0xFA400000
|
||||
#define BCSR1 0xFA400001
|
||||
#define BCSR2 0xFA400002
|
||||
#define BCSR3 0xFA400003
|
||||
|
||||
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
|
||||
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
|
||||
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
|
||||
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
|
||||
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
|
||||
#define BCSR0_COLTEST 0x20
|
||||
#define BCSR0_ETHLPBK 0x40
|
||||
#define BCSR0_ETHEN 0x80
|
||||
|
||||
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
|
||||
#define BCSR1_PCVCTL6 0x02
|
||||
#define BCSR1_PCVCTL5 0x04
|
||||
#define BCSR1_PCVCTL4 0x08
|
||||
#define BCSR1_IPB5SEL 0x10
|
||||
|
||||
#define BCSR2_MIIRST 0x80
|
||||
#define BCSR2_MIIPWRDWN 0x40
|
||||
#define BCSR2_MIICTL 0x08
|
||||
|
||||
#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
|
||||
#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
|
||||
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
|
||||
#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
|
||||
#define BCSR3_D27 0x10 /* Dip Switch settings */
|
||||
#define BCSR3_D26 0x20
|
||||
#define BCSR3_D25 0x40
|
||||
#define BCSR3_D24 0x80
|
||||
|
||||
|
||||
/*
|
||||
* Environment setting
|
||||
*/
|
||||
|
||||
/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
|
||||
/* #define CONFIG_IPADDR 10.10.106.1 */
|
||||
/* #define CONFIG_SERVERIP 10.10.104.11 */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
392
include/configs/RPXlite.h
Normal file
392
include/configs/RPXlite.h
Normal file
@@ -0,0 +1,392 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-Boot port on RPXlite board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define RPXLite_50MHz
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#undef CONFIG_MPC860
|
||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
|
||||
#define CONFIG_RPXLITE 1
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFA200000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFFC00000
|
||||
/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
|
||||
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
|
||||
#endif
|
||||
#define CFG_MONITOR_BASE 0xFFF00000
|
||||
/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_MLRC10)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
/* up to 50 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF00
|
||||
/* up to 50 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_COM11 | SCCR_TBS)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
/*#define CFG_DER 0x2002000F*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0 and OR0 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
|
||||
#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
|
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
|
||||
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000E00
|
||||
|
||||
#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
|
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/* RPXLITE mem setting */
|
||||
#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
|
||||
#define CFG_OR3_PRELIM 0xFFFF8910
|
||||
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
|
||||
#define CFG_OR4_PRELIM 0xFFFE0970
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CFG_MAMR_PTA 58
|
||||
|
||||
/*
|
||||
* Refresh clock Prescalar
|
||||
*/
|
||||
#define CFG_MPTPR MPTPR_PTP_DIV8
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 10 column SDRAM */
|
||||
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
|
||||
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
|
||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||||
/* Configuration variable added by yooth. */
|
||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||||
|
||||
/*
|
||||
* BCSRx
|
||||
*
|
||||
* Board Status and Control Registers
|
||||
*
|
||||
*/
|
||||
|
||||
#define BCSR0 0xFA400000
|
||||
#define BCSR1 0xFA400001
|
||||
#define BCSR2 0xFA400002
|
||||
#define BCSR3 0xFA400003
|
||||
|
||||
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
|
||||
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
|
||||
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
|
||||
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
|
||||
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
|
||||
#define BCSR0_COLTEST 0x20
|
||||
#define BCSR0_ETHLPBK 0x40
|
||||
#define BCSR0_ETHEN 0x80
|
||||
|
||||
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
|
||||
#define BCSR1_PCVCTL6 0x02
|
||||
#define BCSR1_PCVCTL5 0x04
|
||||
#define BCSR1_PCVCTL4 0x08
|
||||
#define BCSR1_IPB5SEL 0x10
|
||||
|
||||
#define BCSR2_ENPA5HDR 0x08 /* USB Control */
|
||||
#define BCSR2_ENUSBCLK 0x10
|
||||
#define BCSR2_USBPWREN 0x20
|
||||
#define BCSR2_USBSPD 0x40
|
||||
#define BCSR2_USBSUSP 0x80
|
||||
|
||||
#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
|
||||
#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
|
||||
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
|
||||
#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
|
||||
#define BCSR3_D27 0x10 /* Dip Switch settings */
|
||||
#define BCSR3_D26 0x20
|
||||
#define BCSR3_D25 0x40
|
||||
#define BCSR3_D24 0x80
|
||||
|
||||
|
||||
/*
|
||||
* Environment setting
|
||||
*/
|
||||
|
||||
#define CONFIG_ETHADDR 00:10:EC:00:1D:0B
|
||||
#define CONFIG_IPADDR 192.168.1.65
|
||||
#define CONFIG_SERVERIP 192.168.1.27
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
505
include/configs/RPXsuper.h
Normal file
505
include/configs/RPXsuper.h
Normal file
@@ -0,0 +1,505 @@
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* These settings must match the way _your_ board is set up
|
||||
*
|
||||
*****************************************************************************/
|
||||
/* for the AY-Revision which does not use the HRCW */
|
||||
#define CFG_DEFAULT_IMMR 0x00010000
|
||||
|
||||
/* What is the oscillator's (UX2) frequency in Hz? */
|
||||
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
|
||||
|
||||
/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
|
||||
* only the 3 least significant bits are important.
|
||||
*/
|
||||
#define CFG_SBC_S2 0x04
|
||||
|
||||
/* What should MODCK_H be? It is dependent on the oscillator
|
||||
* frequency, MODCK[1-3], and desired CPM and core frequencies.
|
||||
* Some example values (all frequencies are in MHz):
|
||||
*
|
||||
* MODCK_H MODCK[1-3] Osc CPM Core
|
||||
* 0x2 0x2 33 133 133
|
||||
* 0x2 0x4 33 133 200
|
||||
* 0x5 0x5 66 133 133
|
||||
* 0x5 0x7 66 133 200
|
||||
*/
|
||||
#define CFG_SBC_MODCK_H 0x06
|
||||
|
||||
#define CFG_SBC_BOOT_LOW 1 /* only for HRCW */
|
||||
#undef CFG_SBC_BOOT_LOW
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
|
||||
* The main FLASH is whichever is connected to *CS0. U-Boot expects
|
||||
* this to be the SIMM.
|
||||
*/
|
||||
#define CFG_FLASH0_BASE 0x80000000
|
||||
#define CFG_FLASH0_SIZE 16
|
||||
|
||||
/* What should the base address of the secondary FLASH be and how big
|
||||
* is it (in Mbytes)? The secondary FLASH is whichever is connected
|
||||
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
|
||||
* want it enabled, don't define these constants.
|
||||
*/
|
||||
#define CFG_FLASH1_BASE 0
|
||||
#define CFG_FLASH1_SIZE 0
|
||||
#undef CFG_FLASH1_BASE
|
||||
#undef CFG_FLASH1_SIZE
|
||||
|
||||
/* What should be the base address of SDRAM DIMM and how big is
|
||||
* it (in Mbytes)?
|
||||
*/
|
||||
#define CFG_SDRAM0_BASE 0x00000000
|
||||
#define CFG_SDRAM0_SIZE 64
|
||||
|
||||
/* What should be the base address of SDRAM DIMM and how big is
|
||||
* it (in Mbytes)?
|
||||
*/
|
||||
#define CFG_SDRAM1_BASE 0x04000000
|
||||
#define CFG_SDRAM1_SIZE 32
|
||||
|
||||
/* What should be the base address of the LEDs and switch S0?
|
||||
* If you don't want them enabled, don't define this.
|
||||
*/
|
||||
#define CFG_LED_BASE 0x00000000
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere.
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on neither */
|
||||
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
||||
* from CONFIG_COMMANDS to remove support for networking.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
|
||||
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
|
||||
|
||||
#if ( CONFIG_ETHER_INDEX == 3 )
|
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK15
|
||||
* - Tx-CLK is CLK16
|
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||
* - Enable Half Duplex in FSMR
|
||||
*/
|
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
|
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
|
||||
# define CFG_CPMFCR_RAMTYPE 0
|
||||
/*#define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
|
||||
# define CFG_FCC_PSMR 0
|
||||
|
||||
#else /* CONFIG_ETHER_INDEX */
|
||||
# error "on RPX Super ethernet must be FCC3"
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
|
||||
/* Define this to reserve an entire FLASH sector (256 KB) for
|
||||
* environment variables. Otherwise, the environment will be
|
||||
* put in the same sector as U-Boot, and changing variables
|
||||
* will erase U-Boot temporarily
|
||||
*/
|
||||
#define CFG_ENV_IN_OWN_SECT
|
||||
|
||||
/* Define to allow the user to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* What should the console's baud rate be? */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Ethernet MAC address */
|
||||
#define CONFIG_ETHADDR 08:00:22:50:70:63
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.99
|
||||
#define CONFIG_SERVERIP 192.168.1.3
|
||||
|
||||
/* Set to a positive value to delay for running BOOTCOMMAND */
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
|
||||
/* undef this to save memory */
|
||||
#define CFG_LONGHELP
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CFG_PROMPT "=> "
|
||||
|
||||
/* What U-Boot subsytems do you want enabled? */
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_IMMAP | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_ECHO | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_REGINFO & \
|
||||
~CFG_CMD_KGDB )
|
||||
|
||||
/* Where do the internal registers live? */
|
||||
#define CFG_IMMR 0xF0000000
|
||||
|
||||
/* Where do the on board registers (CS4) live? */
|
||||
#define CFG_REGS_BASE 0xFA000000
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* You should not have to modify any of the following settings
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
|
||||
#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
|
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
|
||||
|
||||
#define CFG_MAXARGS 8 /* max number of command args */
|
||||
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x04000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE
|
||||
#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*/
|
||||
#if defined(CFG_SBC_BOOT_LOW)
|
||||
# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
|
||||
#else
|
||||
# define CFG_SBC_HRCW_BOOT_FLAGS (0)
|
||||
#endif /* defined(CFG_SBC_BOOT_LOW) */
|
||||
|
||||
/* get the HRCW ISB field from CFG_IMMR */
|
||||
#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
|
||||
((CFG_IMMR & 0x01000000) >> 7) |\
|
||||
((CFG_IMMR & 0x00100000) >> 4) )
|
||||
|
||||
#define CFG_HRCW_MASTER (HRCW_BPS11 |\
|
||||
HRCW_DPPC11 |\
|
||||
CFG_SBC_HRCW_IMMR |\
|
||||
HRCW_MMR00 |\
|
||||
HRCW_LBPC11 |\
|
||||
HRCW_APPC10 |\
|
||||
HRCW_CS10PC00 |\
|
||||
(CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
|
||||
CFG_SBC_HRCW_BOOT_FLAGS)
|
||||
|
||||
/* no slaves */
|
||||
#define CFG_HRCW_SLAVE1 0
|
||||
#define CFG_HRCW_SLAVE2 0
|
||||
#define CFG_HRCW_SLAVE3 0
|
||||
#define CFG_HRCW_SLAVE4 0
|
||||
#define CFG_HRCW_SLAVE5 0
|
||||
#define CFG_HRCW_SLAVE6 0
|
||||
#define CFG_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
* Note also that the logic that sets CFG_RAMBOOT is platform dependent.
|
||||
*/
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH0_BASE + 0x00F00000)
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
# define CFG_ENV_IS_IN_FLASH 1
|
||||
|
||||
# ifdef CFG_ENV_IN_OWN_SECT
|
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
|
||||
# define CFG_ENV_SECT_SIZE 0x40000
|
||||
# else
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
|
||||
# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
|
||||
# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
|
||||
# endif /* CFG_ENV_IN_OWN_SECT */
|
||||
#else
|
||||
# define CFG_ENV_IS_IN_NVRAM 1
|
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
# define CFG_ENV_SIZE 0x200
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CFG_HID0_INIT (/*HID0_ICE |*/\
|
||||
/*HID0_DCE |*/\
|
||||
HID0_ICFI |\
|
||||
HID0_DCI |\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE)
|
||||
|
||||
#define CFG_HID0_FINAL (/*HID0_ICE |*/\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE |\
|
||||
HID0_EMCP)
|
||||
#define CFG_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RMR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_BCR (BCR_EBM |\
|
||||
BCR_PLDP |\
|
||||
BCR_EAV |\
|
||||
BCR_NPQM0)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
|
||||
SIUMCR_APPC10 |\
|
||||
SIUMCR_CS10PC01)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#define CFG_SYPCR (SYPCR_SWTC |\
|
||||
SYPCR_BMT |\
|
||||
SYPCR_PBME |\
|
||||
SYPCR_LBME |\
|
||||
SYPCR_SWRI |\
|
||||
SYPCR_SWP)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC |\
|
||||
TMCNTSC_ALR |\
|
||||
TMCNTSC_TCF |\
|
||||
TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS |\
|
||||
PISCR_PTF |\
|
||||
PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_SCCR (SCCR_DFBRG01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RCCR 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
|
||||
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
|
||||
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
|
||||
* 3 unused
|
||||
* 4 60x GPCM 8 bit Board Regs, LEDs, switches
|
||||
* 5 unused
|
||||
* 6 unused
|
||||
* 7 unused
|
||||
* 8 PCMCIA
|
||||
* 9 unused
|
||||
* 10 unused
|
||||
* 11 unused
|
||||
*/
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*
|
||||
*/
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_DECC_NONE |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_6_CLK |\
|
||||
ORxG_EHTR)
|
||||
|
||||
/* Bank 1 - SDRAM
|
||||
*
|
||||
*/
|
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A8 |\
|
||||
ORxS_NUMR_12 |\
|
||||
ORxS_IBID)
|
||||
|
||||
#define CFG_PSDMR 0x014DA412
|
||||
#define CFG_PSRT 0x79
|
||||
|
||||
|
||||
/* Bank 2 - SDRAM
|
||||
*
|
||||
*/
|
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_L |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CFG_LSDMR 0x0169A512
|
||||
#define CFG_LSRT 0x79
|
||||
|
||||
#define CFG_MPTPR (0x0800 & MPTPR_PTP_MSK)
|
||||
|
||||
/* Bank 4 - On board registers
|
||||
*
|
||||
*/
|
||||
#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_TRLX)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
|
||||
689
include/configs/ep8260.h
Normal file
689
include/configs/ep8260.h
Normal file
@@ -0,0 +1,689 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
|
||||
*
|
||||
* This file is based on similar values for other boards found in other
|
||||
* U-Boot config files, and some that I found in the EP8260 manual.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*
|
||||
* Note: my board is a "SBC 8260 H, V.1.1"
|
||||
* - 64M 60x Bus SDRAM
|
||||
* - 32M Local Bus SDRAM
|
||||
* - 16M Flash (4 x AM29DL323DB90WDI)
|
||||
* - 128k NVRAM with RTC
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* What is the oscillator's (UX2) frequency in Hz? */
|
||||
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
|
||||
*-----------------------------------------------------------------------
|
||||
* What should MODCK_H be? It is dependent on the oscillator
|
||||
* frequency, MODCK[1-3], and desired CPM and core frequencies.
|
||||
* Here are some example values (all frequencies are in MHz):
|
||||
*
|
||||
* MODCK_H MODCK[1-3] Osc CPM Core
|
||||
* ------- ---------- --- --- ----
|
||||
* 0x2 0x2 33 133 133
|
||||
* 0x2 0x3 33 133 166
|
||||
* 0x2 0x4 33 133 200
|
||||
* 0x2 0x5 33 133 233
|
||||
* 0x2 0x6 33 133 266
|
||||
*
|
||||
* 0x5 0x5 66 133 133
|
||||
* 0x5 0x6 66 133 166
|
||||
* 0x5 0x7 66 133 200 *
|
||||
* 0x6 0x0 66 133 233
|
||||
* 0x6 0x1 66 133 266
|
||||
* 0x6 0x2 66 133 300
|
||||
*/
|
||||
#define CFG_SBC_MODCK_H 0x05
|
||||
|
||||
/* Define this if you want to boot from 0x00000100. If you don't define
|
||||
* this, you will need to program the bootloader to 0xfff00000, and
|
||||
* get the hardware reset config words at 0xfe000000. The simplest
|
||||
* way to do that is to program the bootloader at both addresses.
|
||||
* It is suggested that you just let U-Boot live at 0x00000000.
|
||||
*/
|
||||
/* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW */
|
||||
/* #undef CFG_SBC_BOOT_LOW */
|
||||
|
||||
/* The reset command will not work as expected if the reset address does
|
||||
* not point to the correct address.
|
||||
*/
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
|
||||
* The main FLASH is whichever is connected to *CS0. U-Boot expects
|
||||
* this to be the SIMM.
|
||||
*/
|
||||
#define CFG_FLASH0_BASE 0xFF000000
|
||||
#define CFG_FLASH0_SIZE 16
|
||||
|
||||
/* What should the base address of the secondary FLASH be and how big
|
||||
* is it (in Mbytes)? The secondary FLASH is whichever is connected
|
||||
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
|
||||
* want it enabled, don't define these constants.
|
||||
*/
|
||||
#define CFG_FLASH1_BASE 0
|
||||
#define CFG_FLASH1_SIZE 0
|
||||
#undef CFG_FLASH1_BASE
|
||||
#undef CFG_FLASH1_SIZE
|
||||
|
||||
/* What should be the base address of SDRAM DIMM (60x bus) and how big is
|
||||
* it (in Mbytes)?
|
||||
*/
|
||||
#define CFG_SDRAM0_BASE 0x00000000
|
||||
#define CFG_SDRAM0_SIZE 64
|
||||
|
||||
/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
|
||||
* local bus (8260 local bus is NOT cacheable!)
|
||||
*/
|
||||
/* #define CFG_LSDRAM */
|
||||
#undef CFG_LSDRAM
|
||||
|
||||
#ifdef CFG_LSDRAM
|
||||
/* What should be the base address of SDRAM DIMM (local bus) and how big is
|
||||
* it (in Mbytes)?
|
||||
*/
|
||||
#define CFG_SDRAM1_BASE 0x04000000
|
||||
#define CFG_SDRAM1_SIZE 32
|
||||
#else
|
||||
#define CFG_SDRAM1_BASE 0
|
||||
#define CFG_SDRAM1_SIZE 0
|
||||
#undef CFG_SDRAM1_BASE
|
||||
#undef CFG_SDRAM1_SIZE
|
||||
#endif /* CFG_LSDRAM */
|
||||
|
||||
/* What should be the base address of NVRAM and how big is
|
||||
* it (in Bytes)
|
||||
*/
|
||||
#define CFG_NVRAM_BASE_ADDR 0xFa080000
|
||||
#define CFG_NVRAM_SIZE (128*1024)-16
|
||||
|
||||
/* The RTC is a Dallas DS1556
|
||||
*/
|
||||
#define CONFIG_RTC_DS1556
|
||||
|
||||
/* What should be the base address of the LEDs and switch S0?
|
||||
* If you don't want them enabled, don't define this.
|
||||
*/
|
||||
#define CFG_LED_BASE 0x00000000
|
||||
#undef CFG_LED_BASE
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere.
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on neither */
|
||||
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
||||
* from CONFIG_COMMANDS to remove support for networking.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
|
||||
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
|
||||
|
||||
#if ( CONFIG_ETHER_INDEX == 3 )
|
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK15
|
||||
* - Tx-CLK is CLK16
|
||||
* - RAM for BD/Buffers is on the local Bus (see 28-13)
|
||||
* - Enable Half Duplex in FSMR
|
||||
*/
|
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
|
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
|
||||
|
||||
/*
|
||||
* - RAM for BD/Buffers is on the local Bus (see 28-13)
|
||||
*/
|
||||
#ifdef CFG_LSDRAM
|
||||
#define CFG_CPMFCR_RAMTYPE 3
|
||||
#else /* CFG_LSDRAM */
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#endif /* CFG_LSDRAM */
|
||||
|
||||
/* - Enable Half Duplex in FSMR */
|
||||
/* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
|
||||
# define CFG_FCC_PSMR 0
|
||||
|
||||
#else /* CONFIG_ETHER_INDEX */
|
||||
# error "on EP8260 ethernet must be FCC3"
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
/*
|
||||
* select i2c support configuration
|
||||
*
|
||||
* Supported configurations are {none, software, hardware} drivers.
|
||||
* If the software driver is chosen, there are some additional
|
||||
* configuration items that the driver uses to drive the port pins.
|
||||
*/
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
/* #define CONFIG_RTC_DS174x */
|
||||
|
||||
/* Define this to reserve an entire FLASH sector (256 KB) for
|
||||
* environment variables. Otherwise, the environment will be
|
||||
* put in the same sector as U-Boot, and changing variables
|
||||
* will erase U-Boot temporarily
|
||||
*/
|
||||
#define CFG_ENV_IN_OWN_SECT
|
||||
|
||||
/* Define to allow the user to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* What should the console's baud rate be? */
|
||||
/* #define CONFIG_BAUDRATE 57600 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Ethernet MAC address */
|
||||
#define CONFIG_ETHADDR 00:10:EC:00:30:8C
|
||||
|
||||
#define CONFIG_IPADDR 192.168.254.130
|
||||
#define CONFIG_SERVERIP 192.168.254.49
|
||||
|
||||
/* Set to a positive value to delay for running BOOTCOMMAND */
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
|
||||
/* undef this to save memory */
|
||||
#define CFG_LONGHELP
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CFG_PROMPT "=> "
|
||||
|
||||
/* Define this variable to enable the "hush" shell (from
|
||||
Busybox) as command line interpreter, thus enabling
|
||||
powerful command line syntax like
|
||||
if...then...else...fi conditionals or `&&' and '||'
|
||||
constructs ("shell scripts").
|
||||
If undefined, you get the old, much simpler behaviour
|
||||
with a somewhat smapper memory footprint.
|
||||
*/
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* What U-Boot subsytems do you want enabled? */
|
||||
/*
|
||||
*/
|
||||
#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
|
||||
~CFG_CMD_BSP & \
|
||||
~CFG_CMD_DCR & \
|
||||
~CFG_CMD_DHCP & \
|
||||
~CFG_CMD_DOC & \
|
||||
~CFG_CMD_EEPROM & \
|
||||
~CFG_CMD_FDC & \
|
||||
~CFG_CMD_HWFLOW & \
|
||||
~CFG_CMD_IDE & \
|
||||
~CFG_CMD_JFFS2 & \
|
||||
~CFG_CMD_KGDB & \
|
||||
~CFG_CMD_MII & \
|
||||
~CFG_CMD_PCI & \
|
||||
~CFG_CMD_PCMCIA & \
|
||||
~CFG_CMD_SCSI & \
|
||||
~CFG_CMD_USB & \
|
||||
~CFG_CMD_VFD & \
|
||||
~CFG_CMD_DTT )
|
||||
|
||||
/* Where do the internal registers live? */
|
||||
#define CFG_IMMR 0xF0000000
|
||||
#define CFG_DEFAULT_IMMR 0x00010000
|
||||
|
||||
/* Where do the on board registers (CS4) live? */
|
||||
#define CFG_REGS_BASE 0xFA000000
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* You should not have to modify any of the following settings
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
|
||||
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
|
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
|
||||
|
||||
#define CFG_MAXARGS 8 /* max number of command args */
|
||||
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#ifdef CFG_LSDRAM
|
||||
#define CFG_MEMTEST_START 0x04000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
|
||||
#else
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
|
||||
#endif /* CFG_LSDRAM */
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */
|
||||
#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE
|
||||
#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*/
|
||||
|
||||
#if defined(CFG_SBC_BOOT_LOW)
|
||||
# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
|
||||
#else
|
||||
# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
|
||||
#endif /* defined(CFG_SBC_BOOT_LOW) */
|
||||
|
||||
/* get the HRCW ISB field from CFG_IMMR */
|
||||
/*
|
||||
#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
|
||||
((CFG_IMMR & 0x01000000) >> 7) |\
|
||||
((CFG_IMMR & 0x00100000) >> 4) )
|
||||
|
||||
#define CFG_HRCW_MASTER (HRCW_EBM |\
|
||||
HRCW_L2CPC01 |\
|
||||
CFG_SBC_HRCW_IMMR |\
|
||||
HRCW_APPC10 |\
|
||||
HRCW_CS10PC01 |\
|
||||
HRCW_MODCK_H0101 |\
|
||||
CFG_SBC_HRCW_BOOT_FLAGS)
|
||||
*/
|
||||
#define CFG_HRCW_MASTER 0x10400245
|
||||
|
||||
/* no slaves */
|
||||
#define CFG_HRCW_SLAVE1 0
|
||||
#define CFG_HRCW_SLAVE2 0
|
||||
#define CFG_HRCW_SLAVE3 0
|
||||
#define CFG_HRCW_SLAVE4 0
|
||||
#define CFG_HRCW_SLAVE5 0
|
||||
#define CFG_HRCW_SLAVE6 0
|
||||
#define CFG_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
* Note also that the logic that sets CFG_RAMBOOT is platform dependent.
|
||||
*/
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
# define CFG_ENV_IS_IN_FLASH 1
|
||||
|
||||
# ifdef CFG_ENV_IN_OWN_SECT
|
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
|
||||
# define CFG_ENV_SECT_SIZE 0x40000
|
||||
# else
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
|
||||
# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
|
||||
# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
|
||||
# endif /* CFG_ENV_IN_OWN_SECT */
|
||||
#else
|
||||
# define CFG_ENV_IS_IN_NVRAM 1
|
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
# define CFG_ENV_SIZE 0x200
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CFG_HID0_INIT (HID0_ICE |\
|
||||
HID0_DCE |\
|
||||
HID0_ICFI |\
|
||||
HID0_DCI |\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE)
|
||||
#ifdef CFG_LSDRAM
|
||||
/* 8260 local bus is NOT cacheable */
|
||||
#define CFG_HID0_FINAL (/*HID0_ICE |*/\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE |\
|
||||
HID0_EMCP)
|
||||
#else /* !CFG_LSDRAM */
|
||||
#define CFG_HID0_FINAL (HID0_ICE |\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE |\
|
||||
HID0_EMCP)
|
||||
#endif /* CFG_LSDRAM */
|
||||
|
||||
#define CFG_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RMR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/*#define CFG_BCR (BCR_EBM |\
|
||||
BCR_PLDP |\
|
||||
BCR_EAV |\
|
||||
BCR_NPQM1)
|
||||
*/
|
||||
#define CFG_BCR 0x80C08000
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
|
||||
SIUMCR_APPC10 |\
|
||||
SIUMCR_CS10PC01)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#ifdef CFG_LSDRAM
|
||||
#define CFG_SYPCR (SYPCR_SWTC |\
|
||||
SYPCR_BMT |\
|
||||
SYPCR_PBME |\
|
||||
SYPCR_LBME |\
|
||||
SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC |\
|
||||
SYPCR_BMT |\
|
||||
SYPCR_PBME |\
|
||||
SYPCR_SWP)
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC |\
|
||||
TMCNTSC_ALR |\
|
||||
TMCNTSC_TCF |\
|
||||
TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
/*#define CFG_PISCR (PISCR_PS |\
|
||||
PISCR_PTF |\
|
||||
PISCR_PTE)*/
|
||||
#define CFG_PISCR 0
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_SCCR (SCCR_DFBRG01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RCCR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* MPTPR - Memory Refresh Timer Prescale Register 10-32
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_MPTPR (0x0A00 & MPTPR_PTP_MSK)
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
|
||||
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
|
||||
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
|
||||
* 3 unused
|
||||
* 4 60x GPCM 8 bit Board Regs, NVRTC
|
||||
* 5 unused
|
||||
* 6 unused
|
||||
* 7 unused
|
||||
* 8 PCMCIA
|
||||
* 9 unused
|
||||
* 10 unused
|
||||
* 11 unused
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BRx - Base Register
|
||||
* Ref: Section 10.3.1 on page 10-14
|
||||
* ORx - Option Register
|
||||
* Ref: Section 10.3.2 on page 10-18
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*
|
||||
*/
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_DECC_NONE |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_6_CLK |\
|
||||
ORxG_EHTR)
|
||||
|
||||
/* Bank 1 - SDRAM
|
||||
* PSDRAM
|
||||
*/
|
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A6 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CFG_PSDMR 0xC34E2462
|
||||
#define CFG_PSRT 0x64
|
||||
|
||||
|
||||
#ifdef CFG_LSDRAM
|
||||
/* Bank 2 - SDRAM
|
||||
* LSDRAM
|
||||
*/
|
||||
|
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_L |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CFG_LSDMR 0x416A2562
|
||||
#define CFG_LSRT 0x64
|
||||
#else
|
||||
#define CFG_LSRT 0x0
|
||||
#endif /* CFG_LSDRAM */
|
||||
|
||||
/* Bank 4 - On board registers
|
||||
* NVRTC and BCSR
|
||||
*/
|
||||
#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
/*
|
||||
#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_10_CLK |\
|
||||
ORxG_TRLX)
|
||||
*/
|
||||
#define CFG_OR4_PRELIM 0xfff00854
|
||||
|
||||
/* Bank 8 - On board registers
|
||||
* PCMCIA (currently not working!)
|
||||
*/
|
||||
#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_16 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR8_PRELIM (ORxG_AM_MSK |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SETA |\
|
||||
ORxG_SCY_10_CLK)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
35
include/hush.h
Normal file
35
include/hush.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _HUSH_H_
|
||||
#define _HUSH_H_
|
||||
|
||||
#define FLAG_EXIT_FROM_LOOP 1
|
||||
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
|
||||
#define FLAG_REPARSING (1 << 2) /* >=2nd pass */
|
||||
|
||||
extern int u_boot_hush_start(void);
|
||||
extern int parse_string_outer(char *, int);
|
||||
extern int parse_file_outer(void);
|
||||
|
||||
#endif
|
||||
147
include/image.h
Normal file
147
include/image.h
Normal file
@@ -0,0 +1,147 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IMAGE_H__
|
||||
#define __IMAGE_H__
|
||||
|
||||
/*
|
||||
* Operating System Codes
|
||||
*/
|
||||
#define IH_OS_INVALID 0 /* Invalid OS */
|
||||
#define IH_OS_OPENBSD 1 /* OpenBSD */
|
||||
#define IH_OS_NETBSD 2 /* NetBSD */
|
||||
#define IH_OS_FREEBSD 3 /* FreeBSD */
|
||||
#define IH_OS_4_4BSD 4 /* 4.4BSD */
|
||||
#define IH_OS_LINUX 5 /* Linux */
|
||||
#define IH_OS_SVR4 6 /* SVR4 */
|
||||
#define IH_OS_ESIX 7 /* Esix */
|
||||
#define IH_OS_SOLARIS 8 /* Solaris */
|
||||
#define IH_OS_IRIX 9 /* Irix */
|
||||
#define IH_OS_SCO 10 /* SCO */
|
||||
#define IH_OS_DELL 11 /* Dell */
|
||||
#define IH_OS_NCR 12 /* NCR */
|
||||
#define IH_OS_LYNXOS 13 /* LynxOS */
|
||||
#define IH_OS_VXWORKS 14 /* VxWorks */
|
||||
#define IH_OS_PSOS 15 /* pSOS */
|
||||
#define IH_OS_QNX 16 /* QNX */
|
||||
#define IH_OS_U_BOOT 17 /* Firmware */
|
||||
|
||||
/*
|
||||
* CPU Architecture Codes (supported by Linux)
|
||||
*/
|
||||
#define IH_CPU_INVALID 0 /* Invalid CPU */
|
||||
#define IH_CPU_ALPHA 1 /* Alpha */
|
||||
#define IH_CPU_ARM 2 /* ARM */
|
||||
#define IH_CPU_I386 3 /* Intel x86 */
|
||||
#define IH_CPU_IA64 4 /* IA64 */
|
||||
#define IH_CPU_MIPS 5 /* MIPS */
|
||||
#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */
|
||||
#define IH_CPU_PPC 7 /* PowerPC */
|
||||
#define IH_CPU_S390 8 /* IBM S390 */
|
||||
#define IH_CPU_SH 9 /* SuperH */
|
||||
#define IH_CPU_SPARC 10 /* Sparc */
|
||||
#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
|
||||
|
||||
/*
|
||||
* Image Types
|
||||
*
|
||||
* "Standalone Programs" are directly runnable in the environment
|
||||
* provided by U-Boot; it is expected that (if they behave
|
||||
* well) you can continue to work in U-Boot after return from
|
||||
* the Standalone Program.
|
||||
* "OS Kernel Images" are usually images of some Embedded OS which
|
||||
* will take over control completely. Usually these programs
|
||||
* will install their own set of exception handlers, device
|
||||
* drivers, set up the MMU, etc. - this means, that you cannot
|
||||
* expect to re-enter U-Boot except by resetting the CPU.
|
||||
* "RAMDisk Images" are more or less just data blocks, and their
|
||||
* parameters (address, size) are passed to an OS kernel that is
|
||||
* being started.
|
||||
* "Multi-File Images" contain several images, typically an OS
|
||||
* (Linux) kernel image and one or more data images like
|
||||
* RAMDisks. This construct is useful for instance when you want
|
||||
* to boot over the network using BOOTP etc., where the boot
|
||||
* server provides just a single image file, but you want to get
|
||||
* for instance an OS kernel and a RAMDisk image.
|
||||
*
|
||||
* "Multi-File Images" start with a list of image sizes, each
|
||||
* image size (in bytes) specified by an "uint32_t" in network
|
||||
* byte order. This list is terminated by an "(uint32_t)0".
|
||||
* Immediately after the terminating 0 follow the images, one by
|
||||
* one, all aligned on "uint32_t" boundaries (size rounded up to
|
||||
* a multiple of 4 bytes).
|
||||
*
|
||||
* "Firmware Images" are binary images containing firmware (like
|
||||
* U-Boot or FPGA images) which usually will be programmed to
|
||||
* flash memory.
|
||||
*
|
||||
* "Script files" are command sequences that will be executed by
|
||||
* U-Boot's command interpreter; this feature is especially
|
||||
* useful when you configure U-Boot to use a real shell (hush)
|
||||
* as command interpreter.
|
||||
*/
|
||||
|
||||
#define IH_TYPE_INVALID 0 /* Invalid Image */
|
||||
#define IH_TYPE_STANDALONE 1 /* Standalone Program */
|
||||
#define IH_TYPE_KERNEL 2 /* OS Kernel Image */
|
||||
#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */
|
||||
#define IH_TYPE_MULTI 4 /* Multi-File Image */
|
||||
#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
|
||||
#define IH_TYPE_SCRIPT 6 /* Script file */
|
||||
|
||||
/*
|
||||
* Compression Types
|
||||
*/
|
||||
#define IH_COMP_NONE 0 /* No Compression Used */
|
||||
#define IH_COMP_GZIP 1 /* gzip Compression Used */
|
||||
#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
|
||||
|
||||
#define IH_MAGIC 0x27051956 /* Image Magic Number */
|
||||
#define IH_NMLEN 32 /* Image Name Length */
|
||||
|
||||
#ifdef __CYGWIN__
|
||||
typedef unsigned long uint32_t;
|
||||
typedef unsigned char uint8_t;
|
||||
#endif /* __CYGWIN__ */
|
||||
|
||||
/*
|
||||
* all data in network byte order (aka natural aka bigendian)
|
||||
*/
|
||||
|
||||
typedef struct image_header {
|
||||
uint32_t ih_magic; /* Image Header Magic Number */
|
||||
uint32_t ih_hcrc; /* Image Header CRC Checksum */
|
||||
uint32_t ih_time; /* Image Creation Timestamp */
|
||||
uint32_t ih_size; /* Image Data Size */
|
||||
uint32_t ih_load; /* Data Load Address */
|
||||
uint32_t ih_ep; /* Entry Point Address */
|
||||
uint32_t ih_dcrc; /* Image Data CRC Checksum */
|
||||
uint8_t ih_os; /* Operating System */
|
||||
uint8_t ih_arch; /* CPU architecture */
|
||||
uint8_t ih_type; /* Image Type */
|
||||
uint8_t ih_comp; /* Compression Type */
|
||||
uint8_t ih_name[IH_NMLEN]; /* Image Name */
|
||||
} image_header_t;
|
||||
|
||||
|
||||
#endif /* __IMAGE_H__ */
|
||||
949
include/malloc.h
Normal file
949
include/malloc.h
Normal file
@@ -0,0 +1,949 @@
|
||||
/*
|
||||
A version of malloc/free/realloc written by Doug Lea and released to the
|
||||
public domain. Send questions/comments/complaints/performance data
|
||||
to dl@cs.oswego.edu
|
||||
|
||||
* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee)
|
||||
|
||||
Note: There may be an updated version of this malloc obtainable at
|
||||
ftp://g.oswego.edu/pub/misc/malloc.c
|
||||
Check before installing!
|
||||
|
||||
* Why use this malloc?
|
||||
|
||||
This is not the fastest, most space-conserving, most portable, or
|
||||
most tunable malloc ever written. However it is among the fastest
|
||||
while also being among the most space-conserving, portable and tunable.
|
||||
Consistent balance across these factors results in a good general-purpose
|
||||
allocator. For a high-level description, see
|
||||
http://g.oswego.edu/dl/html/malloc.html
|
||||
|
||||
* Synopsis of public routines
|
||||
|
||||
(Much fuller descriptions are contained in the program documentation below.)
|
||||
|
||||
malloc(size_t n);
|
||||
Return a pointer to a newly allocated chunk of at least n bytes, or null
|
||||
if no space is available.
|
||||
free(Void_t* p);
|
||||
Release the chunk of memory pointed to by p, or no effect if p is null.
|
||||
realloc(Void_t* p, size_t n);
|
||||
Return a pointer to a chunk of size n that contains the same data
|
||||
as does chunk p up to the minimum of (n, p's size) bytes, or null
|
||||
if no space is available. The returned pointer may or may not be
|
||||
the same as p. If p is null, equivalent to malloc. Unless the
|
||||
#define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
|
||||
size argument of zero (re)allocates a minimum-sized chunk.
|
||||
memalign(size_t alignment, size_t n);
|
||||
Return a pointer to a newly allocated chunk of n bytes, aligned
|
||||
in accord with the alignment argument, which must be a power of
|
||||
two.
|
||||
valloc(size_t n);
|
||||
Equivalent to memalign(pagesize, n), where pagesize is the page
|
||||
size of the system (or as near to this as can be figured out from
|
||||
all the includes/defines below.)
|
||||
pvalloc(size_t n);
|
||||
Equivalent to valloc(minimum-page-that-holds(n)), that is,
|
||||
round up n to nearest pagesize.
|
||||
calloc(size_t unit, size_t quantity);
|
||||
Returns a pointer to quantity * unit bytes, with all locations
|
||||
set to zero.
|
||||
cfree(Void_t* p);
|
||||
Equivalent to free(p).
|
||||
malloc_trim(size_t pad);
|
||||
Release all but pad bytes of freed top-most memory back
|
||||
to the system. Return 1 if successful, else 0.
|
||||
malloc_usable_size(Void_t* p);
|
||||
Report the number usable allocated bytes associated with allocated
|
||||
chunk p. This may or may not report more bytes than were requested,
|
||||
due to alignment and minimum size constraints.
|
||||
malloc_stats();
|
||||
Prints brief summary statistics on stderr.
|
||||
mallinfo()
|
||||
Returns (by copy) a struct containing various summary statistics.
|
||||
mallopt(int parameter_number, int parameter_value)
|
||||
Changes one of the tunable parameters described below. Returns
|
||||
1 if successful in changing the parameter, else 0.
|
||||
|
||||
* Vital statistics:
|
||||
|
||||
Alignment: 8-byte
|
||||
8 byte alignment is currently hardwired into the design. This
|
||||
seems to suffice for all current machines and C compilers.
|
||||
|
||||
Assumed pointer representation: 4 or 8 bytes
|
||||
Code for 8-byte pointers is untested by me but has worked
|
||||
reliably by Wolfram Gloger, who contributed most of the
|
||||
changes supporting this.
|
||||
|
||||
Assumed size_t representation: 4 or 8 bytes
|
||||
Note that size_t is allowed to be 4 bytes even if pointers are 8.
|
||||
|
||||
Minimum overhead per allocated chunk: 4 or 8 bytes
|
||||
Each malloced chunk has a hidden overhead of 4 bytes holding size
|
||||
and status information.
|
||||
|
||||
Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead)
|
||||
8-byte ptrs: 24/32 bytes (including, 4/8 overhead)
|
||||
|
||||
When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
|
||||
ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
|
||||
needed; 4 (8) for a trailing size field
|
||||
and 8 (16) bytes for free list pointers. Thus, the minimum
|
||||
allocatable size is 16/24/32 bytes.
|
||||
|
||||
Even a request for zero bytes (i.e., malloc(0)) returns a
|
||||
pointer to something of the minimum allocatable size.
|
||||
|
||||
Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes
|
||||
8-byte size_t: 2^63 - 16 bytes
|
||||
|
||||
It is assumed that (possibly signed) size_t bit values suffice to
|
||||
represent chunk sizes. `Possibly signed' is due to the fact
|
||||
that `size_t' may be defined on a system as either a signed or
|
||||
an unsigned type. To be conservative, values that would appear
|
||||
as negative numbers are avoided.
|
||||
Requests for sizes with a negative sign bit when the request
|
||||
size is treaded as a long will return null.
|
||||
|
||||
Maximum overhead wastage per allocated chunk: normally 15 bytes
|
||||
|
||||
Alignnment demands, plus the minimum allocatable size restriction
|
||||
make the normal worst-case wastage 15 bytes (i.e., up to 15
|
||||
more bytes will be allocated than were requested in malloc), with
|
||||
two exceptions:
|
||||
1. Because requests for zero bytes allocate non-zero space,
|
||||
the worst case wastage for a request of zero bytes is 24 bytes.
|
||||
2. For requests >= mmap_threshold that are serviced via
|
||||
mmap(), the worst case wastage is 8 bytes plus the remainder
|
||||
from a system page (the minimal mmap unit); typically 4096 bytes.
|
||||
|
||||
* Limitations
|
||||
|
||||
Here are some features that are NOT currently supported
|
||||
|
||||
* No user-definable hooks for callbacks and the like.
|
||||
* No automated mechanism for fully checking that all accesses
|
||||
to malloced memory stay within their bounds.
|
||||
* No support for compaction.
|
||||
|
||||
* Synopsis of compile-time options:
|
||||
|
||||
People have reported using previous versions of this malloc on all
|
||||
versions of Unix, sometimes by tweaking some of the defines
|
||||
below. It has been tested most extensively on Solaris and
|
||||
Linux. It is also reported to work on WIN32 platforms.
|
||||
People have also reported adapting this malloc for use in
|
||||
stand-alone embedded systems.
|
||||
|
||||
The implementation is in straight, hand-tuned ANSI C. Among other
|
||||
consequences, it uses a lot of macros. Because of this, to be at
|
||||
all usable, this code should be compiled using an optimizing compiler
|
||||
(for example gcc -O2) that can simplify expressions and control
|
||||
paths.
|
||||
|
||||
__STD_C (default: derived from C compiler defines)
|
||||
Nonzero if using ANSI-standard C compiler, a C++ compiler, or
|
||||
a C compiler sufficiently close to ANSI to get away with it.
|
||||
DEBUG (default: NOT defined)
|
||||
Define to enable debugging. Adds fairly extensive assertion-based
|
||||
checking to help track down memory errors, but noticeably slows down
|
||||
execution.
|
||||
REALLOC_ZERO_BYTES_FREES (default: NOT defined)
|
||||
Define this if you think that realloc(p, 0) should be equivalent
|
||||
to free(p). Otherwise, since malloc returns a unique pointer for
|
||||
malloc(0), so does realloc(p, 0).
|
||||
HAVE_MEMCPY (default: defined)
|
||||
Define if you are not otherwise using ANSI STD C, but still
|
||||
have memcpy and memset in your C library and want to use them.
|
||||
Otherwise, simple internal versions are supplied.
|
||||
USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
|
||||
Define as 1 if you want the C library versions of memset and
|
||||
memcpy called in realloc and calloc (otherwise macro versions are used).
|
||||
At least on some platforms, the simple macro versions usually
|
||||
outperform libc versions.
|
||||
HAVE_MMAP (default: defined as 1)
|
||||
Define to non-zero to optionally make malloc() use mmap() to
|
||||
allocate very large blocks.
|
||||
HAVE_MREMAP (default: defined as 0 unless Linux libc set)
|
||||
Define to non-zero to optionally make realloc() use mremap() to
|
||||
reallocate very large blocks.
|
||||
malloc_getpagesize (default: derived from system #includes)
|
||||
Either a constant or routine call returning the system page size.
|
||||
HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
|
||||
Optionally define if you are on a system with a /usr/include/malloc.h
|
||||
that declares struct mallinfo. It is not at all necessary to
|
||||
define this even if you do, but will ensure consistency.
|
||||
INTERNAL_SIZE_T (default: size_t)
|
||||
Define to a 32-bit type (probably `unsigned int') if you are on a
|
||||
64-bit machine, yet do not want or need to allow malloc requests of
|
||||
greater than 2^31 to be handled. This saves space, especially for
|
||||
very small chunks.
|
||||
INTERNAL_LINUX_C_LIB (default: NOT defined)
|
||||
Defined only when compiled as part of Linux libc.
|
||||
Also note that there is some odd internal name-mangling via defines
|
||||
(for example, internally, `malloc' is named `mALLOc') needed
|
||||
when compiling in this case. These look funny but don't otherwise
|
||||
affect anything.
|
||||
WIN32 (default: undefined)
|
||||
Define this on MS win (95, nt) platforms to compile in sbrk emulation.
|
||||
LACKS_UNISTD_H (default: undefined if not WIN32)
|
||||
Define this if your system does not have a <unistd.h>.
|
||||
LACKS_SYS_PARAM_H (default: undefined if not WIN32)
|
||||
Define this if your system does not have a <sys/param.h>.
|
||||
MORECORE (default: sbrk)
|
||||
The name of the routine to call to obtain more memory from the system.
|
||||
MORECORE_FAILURE (default: -1)
|
||||
The value returned upon failure of MORECORE.
|
||||
MORECORE_CLEARS (default 1)
|
||||
True (1) if the routine mapped to MORECORE zeroes out memory (which
|
||||
holds for sbrk).
|
||||
DEFAULT_TRIM_THRESHOLD
|
||||
DEFAULT_TOP_PAD
|
||||
DEFAULT_MMAP_THRESHOLD
|
||||
DEFAULT_MMAP_MAX
|
||||
Default values of tunable parameters (described in detail below)
|
||||
controlling interaction with host system routines (sbrk, mmap, etc).
|
||||
These values may also be changed dynamically via mallopt(). The
|
||||
preset defaults are those that give best performance for typical
|
||||
programs/systems.
|
||||
USE_DL_PREFIX (default: undefined)
|
||||
Prefix all public routines with the string 'dl'. Useful to
|
||||
quickly avoid procedure declaration conflicts and linker symbol
|
||||
conflicts with existing memory allocation routines.
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/* Preliminaries */
|
||||
|
||||
#ifndef __STD_C
|
||||
#ifdef __STDC__
|
||||
#define __STD_C 1
|
||||
#else
|
||||
#if __cplusplus
|
||||
#define __STD_C 1
|
||||
#else
|
||||
#define __STD_C 0
|
||||
#endif /*__cplusplus*/
|
||||
#endif /*__STDC__*/
|
||||
#endif /*__STD_C*/
|
||||
|
||||
#ifndef Void_t
|
||||
#if (__STD_C || defined(WIN32))
|
||||
#define Void_t void
|
||||
#else
|
||||
#define Void_t char
|
||||
#endif
|
||||
#endif /*Void_t*/
|
||||
|
||||
#if __STD_C
|
||||
#include <linux/stddef.h> /* for size_t */
|
||||
#else
|
||||
#include <sys/types.h>
|
||||
#endif /* __STD_C */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if 0 /* not for U-Boot */
|
||||
#include <stdio.h> /* needed for malloc_stats */
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Compile-time options
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
Debugging:
|
||||
|
||||
Because freed chunks may be overwritten with link fields, this
|
||||
malloc will often die when freed memory is overwritten by user
|
||||
programs. This can be very effective (albeit in an annoying way)
|
||||
in helping track down dangling pointers.
|
||||
|
||||
If you compile with -DDEBUG, a number of assertion checks are
|
||||
enabled that will catch more memory errors. You probably won't be
|
||||
able to make much sense of the actual assertion errors, but they
|
||||
should help you locate incorrectly overwritten memory. The
|
||||
checking is fairly extensive, and will slow down execution
|
||||
noticeably. Calling malloc_stats or mallinfo with DEBUG set will
|
||||
attempt to check every non-mmapped allocated and free chunk in the
|
||||
course of computing the summmaries. (By nature, mmapped regions
|
||||
cannot be checked very much automatically.)
|
||||
|
||||
Setting DEBUG may also be helpful if you are trying to modify
|
||||
this code. The assertions in the check routines spell out in more
|
||||
detail the assumptions and invariants underlying the algorithms.
|
||||
|
||||
*/
|
||||
|
||||
#ifdef DEBUG
|
||||
/* #include <assert.h> */
|
||||
#define assert(x) ((void)0)
|
||||
#else
|
||||
#define assert(x) ((void)0)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
INTERNAL_SIZE_T is the word-size used for internal bookkeeping
|
||||
of chunk sizes. On a 64-bit machine, you can reduce malloc
|
||||
overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
|
||||
at the expense of not being able to handle requests greater than
|
||||
2^31. This limitation is hardly ever a concern; you are encouraged
|
||||
to set this. However, the default version is the same as size_t.
|
||||
*/
|
||||
|
||||
#ifndef INTERNAL_SIZE_T
|
||||
#define INTERNAL_SIZE_T size_t
|
||||
#endif
|
||||
|
||||
/*
|
||||
REALLOC_ZERO_BYTES_FREES should be set if a call to
|
||||
realloc with zero bytes should be the same as a call to free.
|
||||
Some people think it should. Otherwise, since this malloc
|
||||
returns a unique pointer for malloc(0), so does realloc(p, 0).
|
||||
*/
|
||||
|
||||
|
||||
/* #define REALLOC_ZERO_BYTES_FREES */
|
||||
|
||||
|
||||
/*
|
||||
WIN32 causes an emulation of sbrk to be compiled in
|
||||
mmap-based options are not currently supported in WIN32.
|
||||
*/
|
||||
|
||||
/* #define WIN32 */
|
||||
#ifdef WIN32
|
||||
#define MORECORE wsbrk
|
||||
#define HAVE_MMAP 0
|
||||
|
||||
#define LACKS_UNISTD_H
|
||||
#define LACKS_SYS_PARAM_H
|
||||
|
||||
/*
|
||||
Include 'windows.h' to get the necessary declarations for the
|
||||
Microsoft Visual C++ data structures and routines used in the 'sbrk'
|
||||
emulation.
|
||||
|
||||
Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
|
||||
Visual C++ header files are included.
|
||||
*/
|
||||
#define WIN32_LEAN_AND_MEAN
|
||||
#include <windows.h>
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
HAVE_MEMCPY should be defined if you are not otherwise using
|
||||
ANSI STD C, but still have memcpy and memset in your C library
|
||||
and want to use them in calloc and realloc. Otherwise simple
|
||||
macro versions are defined here.
|
||||
|
||||
USE_MEMCPY should be defined as 1 if you actually want to
|
||||
have memset and memcpy called. People report that the macro
|
||||
versions are often enough faster than libc versions on many
|
||||
systems that it is better to use them.
|
||||
|
||||
*/
|
||||
|
||||
#define HAVE_MEMCPY
|
||||
|
||||
#ifndef USE_MEMCPY
|
||||
#ifdef HAVE_MEMCPY
|
||||
#define USE_MEMCPY 1
|
||||
#else
|
||||
#define USE_MEMCPY 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (__STD_C || defined(HAVE_MEMCPY))
|
||||
|
||||
#if __STD_C
|
||||
void* memset(void*, int, size_t);
|
||||
void* memcpy(void*, const void*, size_t);
|
||||
#else
|
||||
#ifdef WIN32
|
||||
// On Win32 platforms, 'memset()' and 'memcpy()' are already declared in
|
||||
// 'windows.h'
|
||||
#else
|
||||
Void_t* memset();
|
||||
Void_t* memcpy();
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if USE_MEMCPY
|
||||
|
||||
/* The following macros are only invoked with (2n+1)-multiples of
|
||||
INTERNAL_SIZE_T units, with a positive integer n. This is exploited
|
||||
for fast inline execution when n is small. */
|
||||
|
||||
#define MALLOC_ZERO(charp, nbytes) \
|
||||
do { \
|
||||
INTERNAL_SIZE_T mzsz = (nbytes); \
|
||||
if(mzsz <= 9*sizeof(mzsz)) { \
|
||||
INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \
|
||||
if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \
|
||||
*mz++ = 0; \
|
||||
if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \
|
||||
*mz++ = 0; \
|
||||
if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \
|
||||
*mz++ = 0; }}} \
|
||||
*mz++ = 0; \
|
||||
*mz++ = 0; \
|
||||
*mz = 0; \
|
||||
} else memset((charp), 0, mzsz); \
|
||||
} while(0)
|
||||
|
||||
#define MALLOC_COPY(dest,src,nbytes) \
|
||||
do { \
|
||||
INTERNAL_SIZE_T mcsz = (nbytes); \
|
||||
if(mcsz <= 9*sizeof(mcsz)) { \
|
||||
INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \
|
||||
INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \
|
||||
if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
|
||||
*mcdst++ = *mcsrc++; \
|
||||
if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
|
||||
*mcdst++ = *mcsrc++; \
|
||||
if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
|
||||
*mcdst++ = *mcsrc++; }}} \
|
||||
*mcdst++ = *mcsrc++; \
|
||||
*mcdst++ = *mcsrc++; \
|
||||
*mcdst = *mcsrc ; \
|
||||
} else memcpy(dest, src, mcsz); \
|
||||
} while(0)
|
||||
|
||||
#else /* !USE_MEMCPY */
|
||||
|
||||
/* Use Duff's device for good zeroing/copying performance. */
|
||||
|
||||
#define MALLOC_ZERO(charp, nbytes) \
|
||||
do { \
|
||||
INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \
|
||||
long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \
|
||||
if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \
|
||||
switch (mctmp) { \
|
||||
case 0: for(;;) { *mzp++ = 0; \
|
||||
case 7: *mzp++ = 0; \
|
||||
case 6: *mzp++ = 0; \
|
||||
case 5: *mzp++ = 0; \
|
||||
case 4: *mzp++ = 0; \
|
||||
case 3: *mzp++ = 0; \
|
||||
case 2: *mzp++ = 0; \
|
||||
case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define MALLOC_COPY(dest,src,nbytes) \
|
||||
do { \
|
||||
INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \
|
||||
INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \
|
||||
long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \
|
||||
if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \
|
||||
switch (mctmp) { \
|
||||
case 0: for(;;) { *mcdst++ = *mcsrc++; \
|
||||
case 7: *mcdst++ = *mcsrc++; \
|
||||
case 6: *mcdst++ = *mcsrc++; \
|
||||
case 5: *mcdst++ = *mcsrc++; \
|
||||
case 4: *mcdst++ = *mcsrc++; \
|
||||
case 3: *mcdst++ = *mcsrc++; \
|
||||
case 2: *mcdst++ = *mcsrc++; \
|
||||
case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
Define HAVE_MMAP to optionally make malloc() use mmap() to
|
||||
allocate very large blocks. These will be returned to the
|
||||
operating system immediately after a free().
|
||||
*/
|
||||
|
||||
/***
|
||||
#ifndef HAVE_MMAP
|
||||
#define HAVE_MMAP 1
|
||||
#endif
|
||||
***/
|
||||
#undef HAVE_MMAP /* Not available for U-Boot */
|
||||
|
||||
/*
|
||||
Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
|
||||
large blocks. This is currently only possible on Linux with
|
||||
kernel versions newer than 1.3.77.
|
||||
*/
|
||||
|
||||
/***
|
||||
#ifndef HAVE_MREMAP
|
||||
#ifdef INTERNAL_LINUX_C_LIB
|
||||
#define HAVE_MREMAP 1
|
||||
#else
|
||||
#define HAVE_MREMAP 0
|
||||
#endif
|
||||
#endif
|
||||
***/
|
||||
#undef HAVE_MREMAP /* Not available for U-Boot */
|
||||
|
||||
#if HAVE_MMAP
|
||||
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
|
||||
#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
|
||||
#define MAP_ANONYMOUS MAP_ANON
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_MMAP */
|
||||
|
||||
/*
|
||||
Access to system page size. To the extent possible, this malloc
|
||||
manages memory from the system in page-size units.
|
||||
|
||||
The following mechanics for getpagesize were adapted from
|
||||
bsd/gnu getpagesize.h
|
||||
*/
|
||||
|
||||
#define LACKS_UNISTD_H /* Shortcut for U-Boot */
|
||||
#define malloc_getpagesize 4096
|
||||
|
||||
#ifndef LACKS_UNISTD_H
|
||||
# include <unistd.h>
|
||||
#endif
|
||||
|
||||
#ifndef malloc_getpagesize
|
||||
# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */
|
||||
# ifndef _SC_PAGE_SIZE
|
||||
# define _SC_PAGE_SIZE _SC_PAGESIZE
|
||||
# endif
|
||||
# endif
|
||||
# ifdef _SC_PAGE_SIZE
|
||||
# define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
|
||||
# else
|
||||
# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
|
||||
extern size_t getpagesize();
|
||||
# define malloc_getpagesize getpagesize()
|
||||
# else
|
||||
# ifdef WIN32
|
||||
# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
|
||||
# else
|
||||
# ifndef LACKS_SYS_PARAM_H
|
||||
# include <sys/param.h>
|
||||
# endif
|
||||
# ifdef EXEC_PAGESIZE
|
||||
# define malloc_getpagesize EXEC_PAGESIZE
|
||||
# else
|
||||
# ifdef NBPG
|
||||
# ifndef CLSIZE
|
||||
# define malloc_getpagesize NBPG
|
||||
# else
|
||||
# define malloc_getpagesize (NBPG * CLSIZE)
|
||||
# endif
|
||||
# else
|
||||
# ifdef NBPC
|
||||
# define malloc_getpagesize NBPC
|
||||
# else
|
||||
# ifdef PAGESIZE
|
||||
# define malloc_getpagesize PAGESIZE
|
||||
# else
|
||||
# define malloc_getpagesize (4096) /* just guess */
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
This version of malloc supports the standard SVID/XPG mallinfo
|
||||
routine that returns a struct containing the same kind of
|
||||
information you can get from malloc_stats. It should work on
|
||||
any SVID/XPG compliant system that has a /usr/include/malloc.h
|
||||
defining struct mallinfo. (If you'd like to install such a thing
|
||||
yourself, cut out the preliminary declarations as described above
|
||||
and below and save them in a malloc.h file. But there's no
|
||||
compelling reason to bother to do this.)
|
||||
|
||||
The main declaration needed is the mallinfo struct that is returned
|
||||
(by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a
|
||||
bunch of fields, most of which are not even meaningful in this
|
||||
version of malloc. Some of these fields are are instead filled by
|
||||
mallinfo() with other numbers that might possibly be of interest.
|
||||
|
||||
HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
|
||||
/usr/include/malloc.h file that includes a declaration of struct
|
||||
mallinfo. If so, it is included; else an SVID2/XPG2 compliant
|
||||
version is declared below. These must be precisely the same for
|
||||
mallinfo() to work.
|
||||
|
||||
*/
|
||||
|
||||
/* #define HAVE_USR_INCLUDE_MALLOC_H */
|
||||
|
||||
#if HAVE_USR_INCLUDE_MALLOC_H
|
||||
#include "/usr/include/malloc.h"
|
||||
#else
|
||||
|
||||
/* SVID2/XPG mallinfo structure */
|
||||
|
||||
struct mallinfo {
|
||||
int arena; /* total space allocated from system */
|
||||
int ordblks; /* number of non-inuse chunks */
|
||||
int smblks; /* unused -- always zero */
|
||||
int hblks; /* number of mmapped regions */
|
||||
int hblkhd; /* total space in mmapped regions */
|
||||
int usmblks; /* unused -- always zero */
|
||||
int fsmblks; /* unused -- always zero */
|
||||
int uordblks; /* total allocated space */
|
||||
int fordblks; /* total non-inuse space */
|
||||
int keepcost; /* top-most, releasable (via malloc_trim) space */
|
||||
};
|
||||
|
||||
/* SVID2/XPG mallopt options */
|
||||
|
||||
#define M_MXFAST 1 /* UNUSED in this malloc */
|
||||
#define M_NLBLKS 2 /* UNUSED in this malloc */
|
||||
#define M_GRAIN 3 /* UNUSED in this malloc */
|
||||
#define M_KEEP 4 /* UNUSED in this malloc */
|
||||
|
||||
#endif
|
||||
|
||||
/* mallopt options that actually do something */
|
||||
|
||||
#define M_TRIM_THRESHOLD -1
|
||||
#define M_TOP_PAD -2
|
||||
#define M_MMAP_THRESHOLD -3
|
||||
#define M_MMAP_MAX -4
|
||||
|
||||
|
||||
|
||||
#ifndef DEFAULT_TRIM_THRESHOLD
|
||||
#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
|
||||
#endif
|
||||
|
||||
/*
|
||||
M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
|
||||
to keep before releasing via malloc_trim in free().
|
||||
|
||||
Automatic trimming is mainly useful in long-lived programs.
|
||||
Because trimming via sbrk can be slow on some systems, and can
|
||||
sometimes be wasteful (in cases where programs immediately
|
||||
afterward allocate more large chunks) the value should be high
|
||||
enough so that your overall system performance would improve by
|
||||
releasing.
|
||||
|
||||
The trim threshold and the mmap control parameters (see below)
|
||||
can be traded off with one another. Trimming and mmapping are
|
||||
two different ways of releasing unused memory back to the
|
||||
system. Between these two, it is often possible to keep
|
||||
system-level demands of a long-lived program down to a bare
|
||||
minimum. For example, in one test suite of sessions measuring
|
||||
the XF86 X server on Linux, using a trim threshold of 128K and a
|
||||
mmap threshold of 192K led to near-minimal long term resource
|
||||
consumption.
|
||||
|
||||
If you are using this malloc in a long-lived program, it should
|
||||
pay to experiment with these values. As a rough guide, you
|
||||
might set to a value close to the average size of a process
|
||||
(program) running on your system. Releasing this much memory
|
||||
would allow such a process to run in memory. Generally, it's
|
||||
worth it to tune for trimming rather tham memory mapping when a
|
||||
program undergoes phases where several large chunks are
|
||||
allocated and released in ways that can reuse each other's
|
||||
storage, perhaps mixed with phases where there are no such
|
||||
chunks at all. And in well-behaved long-lived programs,
|
||||
controlling release of large blocks via trimming versus mapping
|
||||
is usually faster.
|
||||
|
||||
However, in most programs, these parameters serve mainly as
|
||||
protection against the system-level effects of carrying around
|
||||
massive amounts of unneeded memory. Since frequent calls to
|
||||
sbrk, mmap, and munmap otherwise degrade performance, the default
|
||||
parameters are set to relatively high values that serve only as
|
||||
safeguards.
|
||||
|
||||
The default trim value is high enough to cause trimming only in
|
||||
fairly extreme (by current memory consumption standards) cases.
|
||||
It must be greater than page size to have any useful effect. To
|
||||
disable trimming completely, you can set to (unsigned long)(-1);
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#ifndef DEFAULT_TOP_PAD
|
||||
#define DEFAULT_TOP_PAD (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
M_TOP_PAD is the amount of extra `padding' space to allocate or
|
||||
retain whenever sbrk is called. It is used in two ways internally:
|
||||
|
||||
* When sbrk is called to extend the top of the arena to satisfy
|
||||
a new malloc request, this much padding is added to the sbrk
|
||||
request.
|
||||
|
||||
* When malloc_trim is called automatically from free(),
|
||||
it is used as the `pad' argument.
|
||||
|
||||
In both cases, the actual amount of padding is rounded
|
||||
so that the end of the arena is always a system page boundary.
|
||||
|
||||
The main reason for using padding is to avoid calling sbrk so
|
||||
often. Having even a small pad greatly reduces the likelihood
|
||||
that nearly every malloc request during program start-up (or
|
||||
after trimming) will invoke sbrk, which needlessly wastes
|
||||
time.
|
||||
|
||||
Automatic rounding-up to page-size units is normally sufficient
|
||||
to avoid measurable overhead, so the default is 0. However, in
|
||||
systems where sbrk is relatively slow, it can pay to increase
|
||||
this value, at the expense of carrying around more memory than
|
||||
the program needs.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#ifndef DEFAULT_MMAP_THRESHOLD
|
||||
#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
M_MMAP_THRESHOLD is the request size threshold for using mmap()
|
||||
to service a request. Requests of at least this size that cannot
|
||||
be allocated using already-existing space will be serviced via mmap.
|
||||
(If enough normal freed space already exists it is used instead.)
|
||||
|
||||
Using mmap segregates relatively large chunks of memory so that
|
||||
they can be individually obtained and released from the host
|
||||
system. A request serviced through mmap is never reused by any
|
||||
other request (at least not directly; the system may just so
|
||||
happen to remap successive requests to the same locations).
|
||||
|
||||
Segregating space in this way has the benefit that mmapped space
|
||||
can ALWAYS be individually released back to the system, which
|
||||
helps keep the system level memory demands of a long-lived
|
||||
program low. Mapped memory can never become `locked' between
|
||||
other chunks, as can happen with normally allocated chunks, which
|
||||
menas that even trimming via malloc_trim would not release them.
|
||||
|
||||
However, it has the disadvantages that:
|
||||
|
||||
1. The space cannot be reclaimed, consolidated, and then
|
||||
used to service later requests, as happens with normal chunks.
|
||||
2. It can lead to more wastage because of mmap page alignment
|
||||
requirements
|
||||
3. It causes malloc performance to be more dependent on host
|
||||
system memory management support routines which may vary in
|
||||
implementation quality and may impose arbitrary
|
||||
limitations. Generally, servicing a request via normal
|
||||
malloc steps is faster than going through a system's mmap.
|
||||
|
||||
All together, these considerations should lead you to use mmap
|
||||
only for relatively large requests.
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef DEFAULT_MMAP_MAX
|
||||
#if HAVE_MMAP
|
||||
#define DEFAULT_MMAP_MAX (64)
|
||||
#else
|
||||
#define DEFAULT_MMAP_MAX (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
M_MMAP_MAX is the maximum number of requests to simultaneously
|
||||
service using mmap. This parameter exists because:
|
||||
|
||||
1. Some systems have a limited number of internal tables for
|
||||
use by mmap.
|
||||
2. In most systems, overreliance on mmap can degrade overall
|
||||
performance.
|
||||
3. If a program allocates many large regions, it is probably
|
||||
better off using normal sbrk-based allocation routines that
|
||||
can reclaim and reallocate normal heap memory. Using a
|
||||
small value allows transition into this mode after the
|
||||
first few allocations.
|
||||
|
||||
Setting to 0 disables all use of mmap. If HAVE_MMAP is not set,
|
||||
the default value is 0, and attempts to set it to non-zero values
|
||||
in mallopt will fail.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
USE_DL_PREFIX will prefix all public routines with the string 'dl'.
|
||||
Useful to quickly avoid procedure declaration conflicts and linker
|
||||
symbol conflicts with existing memory allocation routines.
|
||||
|
||||
*/
|
||||
|
||||
/* #define USE_DL_PREFIX */
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
Special defines for linux libc
|
||||
|
||||
Except when compiled using these special defines for Linux libc
|
||||
using weak aliases, this malloc is NOT designed to work in
|
||||
multithreaded applications. No semaphores or other concurrency
|
||||
control are provided to ensure that multiple malloc or free calls
|
||||
don't run at the same time, which could be disasterous. A single
|
||||
semaphore could be used across malloc, realloc, and free (which is
|
||||
essentially the effect of the linux weak alias approach). It would
|
||||
be hard to obtain finer granularity.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
#ifdef INTERNAL_LINUX_C_LIB
|
||||
|
||||
#if __STD_C
|
||||
|
||||
Void_t * __default_morecore_init (ptrdiff_t);
|
||||
Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
|
||||
|
||||
#else
|
||||
|
||||
Void_t * __default_morecore_init ();
|
||||
Void_t *(*__morecore)() = __default_morecore_init;
|
||||
|
||||
#endif
|
||||
|
||||
#define MORECORE (*__morecore)
|
||||
#define MORECORE_FAILURE 0
|
||||
#define MORECORE_CLEARS 1
|
||||
|
||||
#else /* INTERNAL_LINUX_C_LIB */
|
||||
|
||||
#if __STD_C
|
||||
extern Void_t* sbrk(ptrdiff_t);
|
||||
#else
|
||||
extern Void_t* sbrk();
|
||||
#endif
|
||||
|
||||
#ifndef MORECORE
|
||||
#define MORECORE sbrk
|
||||
#endif
|
||||
|
||||
#ifndef MORECORE_FAILURE
|
||||
#define MORECORE_FAILURE -1
|
||||
#endif
|
||||
|
||||
#ifndef MORECORE_CLEARS
|
||||
#define MORECORE_CLEARS 1
|
||||
#endif
|
||||
|
||||
#endif /* INTERNAL_LINUX_C_LIB */
|
||||
|
||||
#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
|
||||
|
||||
#define cALLOc __libc_calloc
|
||||
#define fREe __libc_free
|
||||
#define mALLOc __libc_malloc
|
||||
#define mEMALIGn __libc_memalign
|
||||
#define rEALLOc __libc_realloc
|
||||
#define vALLOc __libc_valloc
|
||||
#define pvALLOc __libc_pvalloc
|
||||
#define mALLINFo __libc_mallinfo
|
||||
#define mALLOPt __libc_mallopt
|
||||
|
||||
#pragma weak calloc = __libc_calloc
|
||||
#pragma weak free = __libc_free
|
||||
#pragma weak cfree = __libc_free
|
||||
#pragma weak malloc = __libc_malloc
|
||||
#pragma weak memalign = __libc_memalign
|
||||
#pragma weak realloc = __libc_realloc
|
||||
#pragma weak valloc = __libc_valloc
|
||||
#pragma weak pvalloc = __libc_pvalloc
|
||||
#pragma weak mallinfo = __libc_mallinfo
|
||||
#pragma weak mallopt = __libc_mallopt
|
||||
|
||||
#else
|
||||
|
||||
#ifdef USE_DL_PREFIX
|
||||
#define cALLOc dlcalloc
|
||||
#define fREe dlfree
|
||||
#define mALLOc dlmalloc
|
||||
#define mEMALIGn dlmemalign
|
||||
#define rEALLOc dlrealloc
|
||||
#define vALLOc dlvalloc
|
||||
#define pvALLOc dlpvalloc
|
||||
#define mALLINFo dlmallinfo
|
||||
#define mALLOPt dlmallopt
|
||||
#else /* USE_DL_PREFIX */
|
||||
#define cALLOc calloc
|
||||
#define fREe free
|
||||
#define mALLOc malloc
|
||||
#define mEMALIGn memalign
|
||||
#define rEALLOc realloc
|
||||
#define vALLOc valloc
|
||||
#define pvALLOc pvalloc
|
||||
#define mALLINFo mallinfo
|
||||
#define mALLOPt mallopt
|
||||
#endif /* USE_DL_PREFIX */
|
||||
|
||||
#endif
|
||||
|
||||
/* Public routines */
|
||||
|
||||
#if __STD_C
|
||||
|
||||
Void_t* mALLOc(size_t);
|
||||
void fREe(Void_t*);
|
||||
Void_t* rEALLOc(Void_t*, size_t);
|
||||
Void_t* mEMALIGn(size_t, size_t);
|
||||
Void_t* vALLOc(size_t);
|
||||
Void_t* pvALLOc(size_t);
|
||||
Void_t* cALLOc(size_t, size_t);
|
||||
void cfree(Void_t*);
|
||||
int malloc_trim(size_t);
|
||||
size_t malloc_usable_size(Void_t*);
|
||||
void malloc_stats(void);
|
||||
int mALLOPt(int, int);
|
||||
struct mallinfo mALLINFo(void);
|
||||
#else
|
||||
Void_t* mALLOc();
|
||||
void fREe();
|
||||
Void_t* rEALLOc();
|
||||
Void_t* mEMALIGn();
|
||||
Void_t* vALLOc();
|
||||
Void_t* pvALLOc();
|
||||
Void_t* cALLOc();
|
||||
void cfree();
|
||||
int malloc_trim();
|
||||
size_t malloc_usable_size();
|
||||
void malloc_stats();
|
||||
int mALLOPt();
|
||||
struct mallinfo mALLINFo();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}; /* end of extern "C" */
|
||||
#endif
|
||||
29
include/version.h
Normal file
29
include/version.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __VERSION_H__
|
||||
#define __VERSION_H__
|
||||
|
||||
#define U_BOOT_VERSION "U-Boot 0.1.0"
|
||||
|
||||
#endif /* __VERSION_H__ */
|
||||
Reference in New Issue
Block a user