Update ALPR code (NAND support working now)
Patch by Stefan Roese, 07 Oct 2006
This commit is contained in:
Stefan Roese
@@ -31,8 +31,9 @@
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#define CONFIG_440GX 1 /* Specifc GX support */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_BOARD_RESET 1 /* call board_reset() */
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#undef CFG_DRAM_TEST /* Disable-takes long time! */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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@@ -80,45 +81,29 @@
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#if 0 /* test-only */
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/*-----------------------------------------------------------------------
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* NVRAM/RTC
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*
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* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
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* The DS1743 code assumes this condition (i.e. -- it assumes the base
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* address for the RTC registers is:
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*
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* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
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*
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*----------------------------------------------------------------------*/
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#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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@@ -177,7 +162,7 @@
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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@@ -216,24 +201,10 @@
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#if 0 /* test-only */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SNTP )
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#else
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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@@ -250,7 +221,6 @@
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CFG_CMD_FPGA | \
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CFG_CMD_NAND | \
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CFG_CMD_REGINFO)
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#endif
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@@ -279,15 +249,12 @@
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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@@ -321,7 +288,6 @@
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ist das mit den multiple Device in PS
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Mode erklaert ...*/
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/* FPGA program pin configuration */
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#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
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#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */
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@@ -336,14 +302,12 @@
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/*
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* NAND-FLASH stuff
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*/
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#define CFG_MAX_NAND_DEVICE 2
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#define NAND_MAX_CHIPS 2
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#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */
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#if 0
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#define CONFIG_MTD_DEBUG
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#define CONFIG_MTD_DEBUG_VERBOSE 4
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#endif
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#define CFG_MAX_NAND_DEVICE 4
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#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
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#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
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#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \
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CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
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#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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@@ -353,14 +317,9 @@
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/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x92015480
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#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
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/* Memory Bank 1 (NAND-FLASH) initialization */
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/*#define CFG_EBC_PB1AP 0x108f4380 */ /* TODO */
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/*#define CFG_EBC_PB1AP 0x7f854380 */ /* TODO */
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/*#define CFG_EBC_PB1AP 0x108553c0 */
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/*#define CFG_EBC_PB1AP 0x108053c0 */
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#define CFG_EBC_PB1AP 0x10810180
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/*#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 1 (NAND-FLASH) initialization */
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#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */
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#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
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/*
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