From 6c353674bd5219b1129e29d16484eb540e0d3925 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Mon, 7 May 2018 17:42:55 +0800 Subject: [PATCH 1/3] spi: cadence_qspi: Change to use devfdt_get_addr_index() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change to use devfdt_get_addr_index() function to get fdt address. Original code has compilation warning below: drivers/spi/cadence_qspi.c: In function ‘cadence_spi_ofdata_to_platdata’: drivers/spi/cadence_qspi.c:297:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] plat->regbase = (void *)data[0]; ^ drivers/spi/cadence_qspi.c:298:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] plat->ahbbase = (void *)data[2]; ^ Signed-off-by: Ley Foon Tan Acked-by: Marek Vasut Reviewed-by: Jagan Teki --- drivers/spi/cadence_qspi.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index b88837c0eb..91742ba5f1 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -283,18 +283,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); int subnode; - u32 data[4]; - int ret; - /* 2 base addresses are needed, lets get them from the DT */ - ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); - if (ret) { - printf("Error: Can't get base addresses (ret=%d)!\n", ret); - return -ENODEV; - } - - plat->regbase = (void *)data[0]; - plat->ahbbase = (void *)data[2]; + plat->regbase = (void *)devfdt_get_addr_index(bus, 0); + plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs"); plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128); plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4); From 8ff4130debcc09594b550209c44abf6c7e3ee595 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 24 May 2018 21:58:40 +0200 Subject: [PATCH 2/3] sf: Set current flash bank to 0 in clean_bar() The clean_bar() function resets the SPI NOR BAR register to 0, but does not set the flash->curr_bar to 0 , therefore those two can get out of sync, which could ultimatelly result in corrupted flash content. The simplest test case is this: => mw 0x10000000 0x1234abcd 0x4000 => sf probe => sf erase 0x1000000 0x10000 => sf write 0x10000000 0x1000000 0x10000 => sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000 That is, erase a sector above the 16 MiB boundary and write it with random pre-configured data. What will actually happen without this patch is the sector will be erased, but the data will be written to BAR 0 offset 0x0 in the flash. This is because the erase command will call write_bar()+clean_bar(), which will leave flash->bank_curr = 1 while the hardware BAR registers will be set to 0 through clean_bar(). The subsequent write will also trigger write_bar()+clean_bar(), but write_bar checks if the target bank == flash->bank_curr and if so, does NOT reconfigure the BAR in the SPI NOR. Since flash->bank_curr is still 1 and out of sync with the HW, the condition matches, BAR programming is skipped and write ends up at address 0x0, thus corrupting flash content. Signed-off-by: Marek Vasut Cc: Tom Rini Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi_flash.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 0ed2317554..c159124259 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -128,6 +128,7 @@ static int clean_bar(struct spi_flash *flash) if (flash->bank_curr == 0) return 0; cmd = flash->bank_write_cmd; + flash->bank_curr = 0; return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); } From b1f2b72e39465f2d4582bb4d8c426489ee94e2d9 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 2 Jun 2018 14:06:17 +0100 Subject: [PATCH 3/3] sf: Add support for gd25q32b gigadevice flash This flash IC is used in some chromebook models manufactured by Bitland. Signed-off-by: Carlo Caione Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi_flash_ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 5d146e36c6..c45d2e80be 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -63,6 +63,7 @@ const struct spi_flash_info spi_flash_ids[] = { #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, + {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */