eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ppc4xx: Replace 4xx lowercase SPR references

Browse Source 
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
2009-07-22 17:27:56 +02:00
committed by Stefan Roese
parent 87c0b72908
commit 58ea142fb2
15 changed files with 177 additions and 278 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/esd/pmc440/pmc440.c
View File

@@ -142,7 +142,7 @@ int board_early_init_f(void)
reg |= CPR0_ICFG_RLI_MASK;
mtcpr(clk_icfg, reg);
mtspr(dbcr0, 0x20000000); /* do chip reset */
mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
}
/*

2
board/mpl/mip405/mip405.c
View File

@@ -688,7 +688,7 @@ int misc_init_r (void)
start=get_timer(0);
/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
mtspr(ccr0, (mfspr(ccr0) & ~0x80));
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
}

2
board/mpl/pip405/pip405.c
View File

@@ -669,7 +669,7 @@ int misc_init_r (void)
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
mtspr(ccr0, (mfspr(ccr0) & ~0x80));
mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
return (0);
}

8
board/netstal/hcu5/hcu5.c
View File

@@ -89,8 +89,8 @@ int board_early_init_f(void)
/*
* Initiate system reset in debug control register DBCR
*/
dbcr = mfspr(dbcr0);
mtspr(dbcr0, dbcr | CHIP_RESET);
dbcr = mfspr(SPRN_DBCR0);
mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
}
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
#endif
@@ -307,14 +307,14 @@ int misc_init_r(void)
/* We cannot easily enable trace before, as there are other
* routines messing around with sdr0_pfc1. And I do not need it.
*/
if (mfspr(dbcr0) & 0x80000000) {
if (mfspr(SPRN_DBCR0) & 0x80000000) {
/* External debugger alive
* enable trace facilty for Lauterbach
* CCR0[DTB]=0 Enable broadcast of trace information
* SDR0_PFC0[TRE] Trace signals are enabled instead of
* GPIO49-63
*/
mtspr(ccr0, mfspr(ccr0) &~ (CCR0_DTB));
mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
}
return 0;

4
board/netstal/hcu5/sdram.c
View File

@@ -144,7 +144,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
u32 *magicPtr;
u32 magic;
if ((mfspr(dbcr0) & 0x80000000) == 0) {
if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
/* only if no external debugger is alive!
* Check whether vxWorks is using EDR logging, if yes zero
* also PostMortem and user reserved memory
@@ -182,7 +182,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
mtspr(mcsr, mfspr(mcsr));
mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);

2
board/netstal/mcu25/mcu25.c
View File

@@ -77,7 +77,7 @@ int board_early_init_f (void)
out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR );
out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);
out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);
mtspr(ccr0, 0x00700000);
mtspr(SPRN_CCR0, 0x00700000);
return 0;
}