armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Priyanka Jain
committed by
Prabhakar Kushwaha
Prabhakar Kushwaha
parent
2e53759dc6
commit
58c3e62040
214
include/configs/lx2160a_common.h
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214
include/configs/lx2160a_common.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __LX2_COMMON_H
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#define __LX2_COMMON_H
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#include <asm/arch/stream_id_lsch3.h>
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#include <asm/arch/config.h>
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#include <asm/arch/soc.h>
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_GICV3
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#define CONFIG_FSL_TZPC_BP147
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#define CONFIG_FSL_MEMAC
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/* DDR */
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
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#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
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#define CONFIG_DDR_SPD
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS3 0x53
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#define SPD_EEPROM_ADDRESS4 0x54
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#define SPD_EEPROM_ADDRESS5 0x55
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#define SPD_EEPROM_ADDRESS6 0x56
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
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#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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/* SMP Definitinos */
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#define CPU_RELEASE_ADDR secondary_boot_func
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/* Generic Timer Definitions */
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/*
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* This is not an accurate number. It is used in start.S. The frequency
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* will be udpated later when get_bus_freq(0) is available.
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*/
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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/* Serial Port */
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#define CONFIG_PL01X_SERIAL
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#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
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#define CONFIG_SYS_SERIAL0 0x21c0000
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#define CONFIG_SYS_SERIAL1 0x21d0000
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#define CONFIG_SYS_SERIAL2 0x21e0000
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#define CONFIG_SYS_SERIAL3 0x21f0000
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/*below might needs to be removed*/
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#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1, \
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(void *)CONFIG_SYS_SERIAL2, \
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(void *)CONFIG_SYS_SERIAL3 }
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* MC firmware */
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#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
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#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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/* Define phy_reset function to boot the MC based on mcinitcmd.
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* This happens late enough to properly fixup u-boot env MAC addresses.
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*/
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#define CONFIG_RESET_PHY_R
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/*
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* Carve out a DDR region which will not be used by u-boot/Linux
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*
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* It will be used by MC and Debug Server. The MC region must be
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* 512MB aligned, so the min size to hide is 512MB.
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*/
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#ifdef CONFIG_FSL_MC_ENET
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#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
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#endif
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x8
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/* RTC */
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#define RTC
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* Qixis */
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#define CONFIG_FSL_QIXIS
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#define CONFIG_QIXIS_I2C_ACCESS
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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/* PCI */
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#ifdef CONFIG_PCI
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#define CONFIG_SYS_PCI_64BIT
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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/* SATA */
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#ifdef CONFIG_SCSI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
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#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#endif
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/* USB */
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#ifdef CONFIG_USB
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#define CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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/* FlexSPI */
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#ifdef CONFIG_NXP_FSPI
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#define NXP_FSPI_FLASH_SIZE SZ_64M
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#define NXP_FSPI_FLASH_NUM 1
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#endif
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(void);
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unsigned long get_board_ddr_clk(void);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_OFFSET 0x500000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_ENV_OFFSET)
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* Initial environment variables */
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#define XSPI_NOR_BOOTCOMMAND "fsl_mc apply dpl 0x20d00000;" \
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"sf probe 0:0;" \
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"sf read 0xa0000000 0x1000000 0x3000000;" \
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"bootm 0xa0000000"
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#define SD_BOOTCOMMAND "mmc read 0xa0000000 0x6800 0xA0;" \
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"fsl_mc apply dpl 0xa0000000;" \
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"mmc read 0xb0000000 0x8000 0x1d000;" \
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"bootm 0xb0000000"
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#define XSPI_MC_INIT_CMD \
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"fsl_mc start mc 0x20a00000 0x20e00000\0"
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#define SD_MC_INIT_CMD \
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"mmc read 0x80000000 0x5000 0x800;" \
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"mmc read 0x80100000 0x7000 0x800;" \
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"fsl_mc start mc 0x80000000 0x80100000\0"
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#endif /* __LX2_COMMON_H */
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102
include/configs/lx2160ardb.h
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include/configs/lx2160ardb.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __LX2_RDB_H
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#define __LX2_RDB_H
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#include "lx2160a_common.h"
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/* Qixis */
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#define QIXIS_XMAP_MASK 0x07
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#define QIXIS_XMAP_SHIFT 5
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#define QIXIS_RST_CTL_RESET_EN 0x30
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x20
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#define QIXIS_LBMAP_QSPI 0x00
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#define QIXIS_RCW_SRC_QSPI 0xff
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SD
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#define QIXIS_RCW_SRC_SD 0x08
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#define NON_EXTENDED_DUTCFG
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/* VID */
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#define I2C_MUX_CH_VOL_MONITOR 0xA
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/* Voltage monitor on channel 2*/
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#define I2C_VOL_MONITOR_ADDR 0x63
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#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
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#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
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#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
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#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
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#define CONFIG_VID
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/* The lowest and highest voltage allowed*/
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#define VDD_MV_MIN 775
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#define VDD_MV_MAX 855
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/* PM Bus commands code for LTC3882*/
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#define PMBUS_CMD_PAGE 0x0
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#define PMBUS_CMD_READ_VOUT 0x8B
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#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
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#define PMBUS_CMD_VOUT_COMMAND 0x21
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#define PWM_CHANNEL0 0x0
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#define CONFIG_VOL_MONITOR_LTC3882_SET
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#define CONFIG_VOL_MONITOR_LTC3882_READ
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/* RTC */
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#define CONFIG_SYS_RTC_BUS_NUM 4
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/* MAC/PHY configuration */
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#if defined(CONFIG_FSL_MC_ENET)
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#define CONFIG_MII
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#define CONFIG_ETHPRIME "DPMAC1@xgmii"
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#define AQR107_PHY_ADDR1 0x04
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#define AQR107_PHY_ADDR2 0x05
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#define CORTINA_NO_FW_UPLOAD
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#define CORTINA_PHY_ADDR1 0x0
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#define INPHI_PHY_ADDR1 0x0
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#define RGMII_PHY_ADDR1 0x01
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#define RGMII_PHY_ADDR2 0x02
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#endif
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"scriptaddr=0x80800000\0" \
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"kernel_addr_r=0x81000000\0" \
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"pxefile_addr_r=0x81000000\0" \
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"fdt_addr_r=0x88000000\0" \
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"ramdisk_addr_r=0x89000000\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x21000000\0" \
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"lx2160ardb_vdd_mv=800\0" \
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"mcmemsize=0x40000000\0"
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#include <asm/fsl_secure_boot.h>
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#endif /* __LX2_RDB_H */
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