Merge branch '2021-07-06-platform-updates'

- mpc8379erdb DM_USB, DM_PCI and DM_ETH support. - Drop PCI support from the integrator family of boards - Add synquacer support - Assorted lpc32xx updates and improvements - snapdragon (and related) fixes, Broadcom iproc update
2021-07-06 18:10:10 -04:00
parent b5f9d2f3aa 725cf89512
commit 5617efd2c8
72 changed files with 4320 additions and 742 deletions
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -30,11 +30,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
 					 - GENERATED_GBL_DATA_SIZE)

-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART		5   /* UART5 */
-
 /*
 * DMA
 */
@@ -46,7 +41,6 @@
 * I2C
 */
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_LPC32XX
 #define CONFIG_SYS_I2C_SPEED		100000

 /*
--- a/include/configs/ea-lpc3250devkitv2.h
+++ b/include/configs/ea-lpc3250devkitv2.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Embedded Artists LPC3250 DevKit v2
+ * Copyright (C) 2021  Trevor Woerner <twoerner@gmail.com>
+ */
+
+#ifndef __CONFIG_EA_LPC3250DEVKITV2_H__
+#define __CONFIG_EA_LPC3250DEVKITV2_H__
+
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * SoC and board defines
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */
+
+/*
+ * RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+
+/*
+ * cmd
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80100000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SoC-specific config
+ */
+#include <asm/arch/config.h>
+
+#endif
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Timers for fasp(TIMCLK) */
+#define CONFIG_SYS_HZ			1000		/* 1 msec */
+#define CONFIG_SYS_TIMERBASE		0x31080000	/* AP Timer 1 (ARM-SP804) */
+
+/*
+ * SDRAM (for initialize)
+ */
+#define CONFIG_SYS_SDRAM_BASE		(0x80000000)	/* Start address of DDR3 */
+#define PHYS_SDRAM_SIZE			(0x7c000000)	/* Default size (2GB - Secure memory) */
+
+#define CONFIG_VERY_BIG_RAM				/* SynQuacer supports up to 64GB */
+#define CONFIG_MAX_MEM_MAPPED		PHYS_SDRAM_SIZE
+
+#define SQ_DRAMINFO_BASE		(0x2e00ffc0)	/* DRAM info from TF-A */
+
+/*
+ * Boot info
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(0xe0000000)	/* stack of init proccess */
+#define CONFIG_SYS_MALLOC_LEN		(0x01000000)	/* 16Mbyte size of malloc() */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE /* default kernel load address */
+
+/*
+ * Hardware drivers support
+ */
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/* Serial (pl011)       */
+#define UART_CLK			(62500000)
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		UART_CLK
+#define CONFIG_PL01x_PORTS		{(void *)(0x2a400000)}
+
+#define CONFIG_ENV_OVERWRITE		/* ethaddr can be reprogrammed */
+
+/* Support MTD */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + (512 * 1024))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		128
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
+/* #define CONFIG_SYS_PCI_64BIT		1 */
+
+#define DEFAULT_DFU_ALT_INFO "dfu_alt_info="				\
+			"mtd nor1=u-boot.bin raw 200000 100000;"	\
+			"fip.bin raw 180000 78000;"			\
+			"optee.bin raw 500000 100000\0"
+
+/* Distro boot settings */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICE_USB(func)	func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICE_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICE_MMC(func)	func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICE_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_NVME
+#define BOOT_TARGET_DEVICE_NVME(func)	func(NVME, nvme, 0)
+#else
+#define BOOT_TARGET_DEVICE_NVME(func)
+#endif
+
+#ifdef CONFIG_CMD_SCSI
+#define BOOT_TARGET_DEVICE_SCSI(func)	func(SCSI, scsi, 0) func(SCSI, scsi, 1)
+#else
+#define BOOT_TARGET_DEVICE_SCSI(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func)	\
+	BOOT_TARGET_DEVICE_USB(func)	\
+	BOOT_TARGET_DEVICE_MMC(func)	\
+	BOOT_TARGET_DEVICE_SCSI(func)	\
+	BOOT_TARGET_DEVICE_NVME(func)	\
+
+#include <config_distro_bootcmd.h>
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"fdt_addr_r=0x9fe00000\0"		\
+	"kernel_addr_r=0x90000000\0"		\
+	"ramdisk_addr_r=0xa0000000\0"		\
+	"scriptaddr=0x88000000\0"		\
+	"pxefile_addr_r=0x88100000\0"		\
+	DEFAULT_DFU_ALT_INFO			\
+	BOOTENV
+
+#endif /* __CONFIG_H */
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -35,11 +35,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_512K \
 					 - GENERATED_GBL_DATA_SIZE)

-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART		5   /* UART5 - NS16550 */
-
 /*
 * Ethernet Driver
 */
@@ -52,7 +47,6 @@
 * I2C driver
 */

-#define CONFIG_SYS_I2C_LPC32XX
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SPEED 350000

--- a/include/dt-bindings/clock/lpc32xx-clock.h
+++ b/include/dt-bindings/clock/lpc32xx-clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
+#define __DT_BINDINGS_LPC32XX_CLOCK_H
+
+/* LPC32XX System Control Block clocks */
+#define LPC32XX_CLK_RTC		1
+#define LPC32XX_CLK_DMA		2
+#define LPC32XX_CLK_MLC		3
+#define LPC32XX_CLK_SLC		4
+#define LPC32XX_CLK_LCD		5
+#define LPC32XX_CLK_MAC		6
+#define LPC32XX_CLK_SD		7
+#define LPC32XX_CLK_DDRAM	8
+#define LPC32XX_CLK_SSP0	9
+#define LPC32XX_CLK_SSP1	10
+#define LPC32XX_CLK_UART3	11
+#define LPC32XX_CLK_UART4	12
+#define LPC32XX_CLK_UART5	13
+#define LPC32XX_CLK_UART6	14
+#define LPC32XX_CLK_IRDA	15
+#define LPC32XX_CLK_I2C1	16
+#define LPC32XX_CLK_I2C2	17
+#define LPC32XX_CLK_TIMER0	18
+#define LPC32XX_CLK_TIMER1	19
+#define LPC32XX_CLK_TIMER2	20
+#define LPC32XX_CLK_TIMER3	21
+#define LPC32XX_CLK_TIMER4	22
+#define LPC32XX_CLK_TIMER5	23
+#define LPC32XX_CLK_WDOG	24
+#define LPC32XX_CLK_I2S0	25
+#define LPC32XX_CLK_I2S1	26
+#define LPC32XX_CLK_SPI1	27
+#define LPC32XX_CLK_SPI2	28
+#define LPC32XX_CLK_MCPWM	29
+#define LPC32XX_CLK_HSTIMER	30
+#define LPC32XX_CLK_KEY		31
+#define LPC32XX_CLK_PWM1	32
+#define LPC32XX_CLK_PWM2	33
+#define LPC32XX_CLK_ADC		34
+#define LPC32XX_CLK_HCLK_PLL	35
+#define LPC32XX_CLK_PERIPH	36
+
+/* LPC32XX USB clocks */
+#define LPC32XX_USB_CLK_I2C	1
+#define LPC32XX_USB_CLK_DEVICE	2
+#define LPC32XX_USB_CLK_HOST	3
+
+#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */