Cleanup of the monahans cpu and delta board port.
This commit is contained in:
Markus Klotzbuecher
committed by
Markus Klotzbcher
Markus Klotzbcher
parent
e443c944cf
commit
552fc624f2
@@ -821,21 +821,21 @@ typedef void (*ExcpHndlr) (void) ;
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#define RTAR __REG(0x40900004) /* RTC Alarm Register */
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#define RTSR __REG(0x40900008) /* RTC Status Register */
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#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
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#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
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#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
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#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
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#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
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#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
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#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
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#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
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#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
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#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
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#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
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#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
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#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
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#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
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#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
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#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
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#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
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#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
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#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
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#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
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#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
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#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
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#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
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#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
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#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
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#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
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#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
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#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
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#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
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#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
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#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
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#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
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@@ -921,9 +921,10 @@ typedef void (*ExcpHndlr) (void) ;
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#ifdef CONFIG_CPU_MONAHANS
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#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
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/* Missing: 32 Interrupt priority registers */
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/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
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* merged if GPIO Stuff is same too. */
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/* Missing: 32 Interrupt priority registers
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* These are the same as beneath for PXA27x: maybe can be merged if
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* GPIO Stuff is same too.
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*/
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
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#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
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#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
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@@ -983,24 +984,24 @@ typedef void (*ExcpHndlr) (void) ;
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#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
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#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
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#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
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#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
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#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
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#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
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#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
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#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
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#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
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#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
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#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
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#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
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#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
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#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
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#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
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#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
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#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
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#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
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#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
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#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
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#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
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#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
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#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
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#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
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#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
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#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
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#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
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@@ -1488,8 +1489,8 @@ typedef void (*ExcpHndlr) (void) ;
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#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
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#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
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#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
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#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
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#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
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#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
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/*
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* Power Manager
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@@ -1709,10 +1710,10 @@ typedef void (*ExcpHndlr) (void) ;
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#define ACCR_13MEND2 (1 << 21)
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#define ACCR_PCCE (1 << 11)
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#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
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#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
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#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
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#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
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#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
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#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
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#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
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#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
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#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
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#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
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#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
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@@ -1720,27 +1721,27 @@ typedef void (*ExcpHndlr) (void) ;
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#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
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#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
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#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
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#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
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#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
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#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
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#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
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#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
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#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
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#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
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#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
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#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
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#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
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#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
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#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
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#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
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#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
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#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
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#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
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#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
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#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
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#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
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#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
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#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
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#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
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#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
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#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
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#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
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#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
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#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
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#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
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#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
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#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
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#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
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#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
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#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
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#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
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#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
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#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
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#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */
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#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
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#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
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@@ -2382,16 +2383,16 @@ typedef void (*ExcpHndlr) (void) ;
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#define KPAS_SO (0x1 << 31)
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#define KPASMKPx_SO (0x1 << 31)
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#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
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#define PSLR __REG(0x40F00034)
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#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
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#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
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#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
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#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
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#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
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#define OSMR4 __REG(0x40A00080) /* */
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#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
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#define OMCR4 __REG(0x40A000C0) /* */
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#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
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#define PSLR __REG(0x40F00034)
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#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
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#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
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#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
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#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
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#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
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#define OSMR4 __REG(0x40A00080) /* */
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#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
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#define OMCR4 __REG(0x40A000C0) /* */
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#endif /* CONFIG_PXA27X */
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@@ -62,7 +62,7 @@
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1
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#define CONFIG_FFUART 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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@@ -168,8 +168,6 @@
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#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define SECTORSIZE 512
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#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
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/* nand timeout values */
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#define CFG_NAND_PROG_ERASE_TO 3000
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@@ -178,16 +176,15 @@
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#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
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/* NAND Timing Parameters (in ns) */
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#define NAND_TIMING_tCH 10
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#define NAND_TIMING_tCS 0
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#define NAND_TIMING_tCH 10
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#define NAND_TIMING_tCS 0
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#define NAND_TIMING_tWH 20
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#define NAND_TIMING_tWP 40
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#define NAND_TIMING_tWP 40
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#define NAND_TIMING_tRH 20
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#define NAND_TIMING_tRP 40
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#define NAND_TIMING_tRH 20
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#define NAND_TIMING_tRP 40
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#define NAND_TIMING_tR 11123
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/* #define NAND_TIMING_tWHR 110 */
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#define NAND_TIMING_tR 11123
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#define NAND_TIMING_tWHR 100
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#define NAND_TIMING_tAR 10
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@@ -199,87 +196,16 @@
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#define CONFIG_MTD_DEBUG
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#define CONFIG_MTD_DEBUG_VERBOSE 1
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NO_FLASH 1
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#ifndef CGF_NO_FLASH
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/* these are required by the environment code */
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#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */
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#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */
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#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */
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#endif
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#define CFG_NO_FLASH 1
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/*
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* GPIO settings
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*/
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#define CFG_GPSR0_VAL 0x00008000
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#define CFG_GPSR1_VAL 0x00FC0382
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#define CFG_GPSR2_VAL 0x0001FFFF
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#define CFG_GPCR0_VAL 0x00000000
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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#define CFG_GPDR0_VAL 0x0060A800
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#define CFG_GPDR1_VAL 0x00FF0382
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#define CFG_GPDR2_VAL 0x0001C000
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#define CFG_GAFR0_L_VAL 0x98400000
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#define CFG_GAFR0_U_VAL 0x00002950
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#define CFG_GAFR1_L_VAL 0x000A9558
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#define CFG_GAFR1_U_VAL 0x0005AAAA
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#define CFG_GAFR2_L_VAL 0xA0000000
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#define CFG_GAFR2_U_VAL 0x00000002
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#define CFG_PSSR_VAL 0x20
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/*
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* Memory settings
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*/
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#define CFG_MSC0_VAL 0x23F223F2
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#define CFG_MSC1_VAL 0x3FF1A441
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#define CFG_MSC2_VAL 0x7FF97FF1
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#define CFG_MDCNFG_VAL 0x00001AC9
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#define CFG_MDREFR_VAL 0x00018018
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#define CFG_MDMRS_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CFG_MECR_VAL 0x00000000
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#define CFG_MCMEM0_VAL 0x00010504
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#define CFG_MCMEM1_VAL 0x00010504
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#define CFG_MCATT0_VAL 0x00010504
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#define CFG_MCATT1_VAL 0x00010504
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#define CFG_MCIO0_VAL 0x00004715
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#define CFG_MCIO1_VAL 0x00004715
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#define _LED 0x08000010
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#define LED_BLANK 0x08000040
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/*
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* FLASH and environment organization
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*/
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#ifndef CFG_NO_FLASH
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
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/* NOTE: many default partitioning schemes assume the kernel starts at the
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* second sector, not an environment. You have been warned!
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*/
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#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
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#endif /* #ifndef CFG_NO_FLASH */
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/* #define CFG_ENV_IS_NOWHERE */
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#define CFG_ENV_IS_IN_NAND 1
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#define CFG_ENV_OFFSET 0x40000
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#define CFG_ENV_OFFSET_REDUND 0x44000
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