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Merge branch 'master' of git://git.denx.de/u-boot-arm

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* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
  ARM: cache: Move the cp15 CR register read before flushing the cache.
  ARM: introduce arch_early_init_r()
  PXA: Enable CONFIG_PREBOOT on zipitz2
  ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
  No need to define CONFIG_ARCH_CPU_INIT.
  add new board vl_ma2sc
  MTD: SPEAr SMI: Add write support for length < 4 bytes
  i2c: designware_i2c.c: Add support for the "i2c probe" command
  rtc/m41t62: Add support for M41T82 with HT (Halt Update)
  SPL: ARM: spear: Add SPL support for SPEAr600 platform
  Makefile: Add u-boot.spr build target (SPEAr)
  SPL: ARM: spear: Remove some objects from SPL build
  SPL: lib/Makefile: Add crc32.c to SPL build
  SPL: common/Makefile: Add image.c to SPL build
  arm: Don't use printf() in SPL builds
  GPIO: Add SPEAr GPIO driver
  net: Multiple updates/enhancements to designware.c
  cleanup/SPEAr: Define configuration flags more elegantly
  cleanup/SPEAr: Remove unnecessary parenthesis
  SPEAr: Correct SoC ID offset in misc configuration space
  SPEAr: explicitly select clk src for UART
  SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
  SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
  SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
  SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
  SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
  SPEAr: Enable dcache for fast file transfer
  SPEAr: Enable autoneg for ethernet
  SPEAr: Enable udc and usb-console support only for usbtty configuration
  SPEAr: Enable usb device high speed support
  SPEAr: Initialize SNOR in early_board_init_f
  SPEAr: Change the default environment variables
  SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
  SPEAr: Add configuration options for spear3xx and spear6xx boards
  SPEAr: Add basic arch related support for SPEAr SoCs
  SPEAr: Add interface information in initialization
  SPEAr: Add macb driver support for spear310 and spear320
  SPEAr: Configure network support for spear SoCs
  SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
  SPEAr: Eliminate dependency on Xloader table
  SPEAr: Fix ARM relocation support
  st_smi: Fixed page size for Winbond W25Q128FV flash
  st_smi: Change timeout loop implementation
  st_smi: Fix bug in flash_print_info()
  st_smi: Change the flash probing method
  st_smi: Removed no needed dependency on ST_M25Pxx_ID
  st_smi: Fix smi read status
  st_smi: Move status register read before modifying ctrl register
  st_smi: Read status until timeout happens
  st_smi: Enhance the error handling
  st_smi: Change SMI timeout values
  st_smi: Return error in case TFF is not set
  st_smi: Add support for SPEAr SMI driver
  mtd/NAND: Remove obsolete SPEAr specific NAND drivers
  SPEAr: Configure FSMC driver for NAND interface
  mtd/NAND: Add FSMC driver support
  arm/km: remove calls to kw_gpio_* in board_early_init_f
  arm/km: add implementation for read_dip_switch
  arm/km: support the 2 PCIe fpga resets
  arm/km: skip FPGA config when already configured
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: cleanup km_kirkwood boards
  arm/km: enable BOCO2 FPGA download support
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: add kmcoge5un board support
  arm/km: add kmnusa board support
  arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
  cm-t35: fix incorrect NAND_ECC layout selection
  ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
  ARM: OMAP4/5: Move USB pads to essential list.
  ARM: OMAP4/5: Move USB clocks to essential group.
  ARM: OMAP4/5: Move gpmc clocks to essential group.
  ARM: OMAP4+: Move external phy initialisations to arch specific place.
  omap4: Use a smaller M,N couple for IVA DPLL
  da850/omap-l138: Enable auto negotiation in RMII mode
  omap: am33xx: accomodate input clocks other than 24 Mhz
  omap: emif: fix bug in manufacturer code test
  omap: emif: deal with rams that return duplicate mr data on all byte lanes
  OMAP4+: Force DDR in self-refresh after warm reset
  OMAP4+: Handle sdram init after warm reset
  ARM: OMAP3+: Detect reset type
  arm: bugfix: Move vector table before jumping relocated code
  Kirkwood: Add support for Ka-Ro TK71
  arm/km: use spi claim bus to switch between SPI and NAND
  arm/kirkwood: protect the ENV_SPI #defines
  ARM: don't probe PHY address for LaCie boards
  lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
  lacie_kw: fix SDRAM banks number for net2big_v2
  Kirkwood: add lschlv2 and lsxhl board support
  net: add helper to generate random mac address
  net: use common rand()/srand() functions
  lib: add rand() function
  kwboot: boot kirkwood SoCs over a serial link
  kw_spi: add weak functions board_spi_claim/release_bus
  kw_spi: support spi_claim/release_bus functions
  kw_spi: backup and reset the MPP of the chosen CS pin
  kirkwood: fix calls to kirkwood_mpp_conf
  kirkwood: add save functionality kirkwood_mpp_conf function
  km_arm: use filesize for erase in update command
  arm/km: enable mii cmd
  arm/km: remove CONFIG_RESET_PHY_R
  arm/km: change maintainer for mgcoge3un
  arm/km: fix wrong comment in SDRAM config for mgcoge3un
  arm/km: use ARRAY_SIZE macro
  arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
  arm/km: add piggy mac adress offset for mgcoge3un
  arm/km: add board type to boards.cfg
  AT91SAM9*: Change kernel address in dataflash to match u-boot's size
  ATMEL/PIO: Enable new feature of PIO on Atmel device
  ehci-atmel: fix compiler warning
  AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
  Atmel : usb : add EHCI driver for Atmel SoC
  Fix: AT91SAM9263 nor flash usage
  Fix: broken boot message at serial line on AT91SAM9263-EK board
  i.MX6 USDHC: Use the ESDHC clock
  mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
  i.MX28: Add function to adjust memory parameters
  mx28evk: Fix PSWITCH key position
  mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
  mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
  imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
  mx53ard: Remove unused CONFIG_MII_GASKET
  mx6: Avoid writing to read-only bits in imximage.cfg
  m28evk: use same notation to alloc the 128kB stack
  ...

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
2012-07-08 19:26:33 +02:00
parent 8246ff864d d702b0811d
commit 50cd93b250
258 changed files with 11050 additions and 1797 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
include/common.h
View File

@@ -760,6 +760,16 @@ char * strmhz(char *buf, unsigned long hz);
/* lib/crc32.c */
#include <u-boot/crc.h>
/* lib/rand.c */
#if defined(CONFIG_RANDOM_MACADDR) || \
defined(CONFIG_BOOTP_RANDOM_DELAY) || \
defined(CONFIG_CMD_LINK_LOCAL)
#define RAND_MAX -1U
void srand(unsigned int seed);
unsigned int rand(void);
unsigned int rand_r(unsigned int *seedp);
#endif
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
int console_init_r(void); /* After relocation; uses the console stuff */

5
include/configs/at91sam9260ek.h
View File

@@ -187,7 +187,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
@@ -201,7 +201,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
@@ -230,6 +230,7 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool

5
include/configs/at91sam9261ek.h
View File

@@ -189,7 +189,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
@@ -203,7 +203,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
@@ -232,6 +232,7 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool

10
include/configs/at91sam9263ek.h
View File

@@ -33,7 +33,11 @@
*/
#include <asm/hardware.h>
#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SYS_TEXT_BASE 0x21F00000
#else
#define CONFIG_SYS_TEXT_BASE 0x0000000
#endif
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
@@ -147,11 +151,11 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SIZE 0x10000
#define xstr(s) str(s)
#define str(s) #s
@@ -314,7 +318,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) "\

20
include/configs/at91sam9m10g45ek.h
View File

@@ -59,17 +59,6 @@
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
*/
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* Specify the clock enable bit in the PMC_SCER register.
*/
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/* LCD */
#define CONFIG_LCD
#define LCD_BPP LCD_COLOR8
@@ -147,13 +136,10 @@
#define CONFIG_RESET_PHY_R
/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_ATMEL
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */

3
include/configs/at91sam9rlek.h
View File

@@ -155,7 +155,7 @@
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) "\
@@ -182,6 +182,7 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool

5
include/configs/cm_t35.h
View File

@@ -77,7 +77,7 @@
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
@@ -174,7 +174,7 @@
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define GPMC_NAND_ECC_LP_x8_LAYOUT
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
@@ -315,7 +315,6 @@
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET

20
include/configs/enbw_cmc.h
View File

@@ -101,6 +101,14 @@
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
/*
* SPI Configuration
*/
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_CMD_SPI
/*
* Flash & Environment
*/
@@ -225,9 +233,9 @@
"key_magic_2=2\0" \
"key_magic_3=3\0" \
"magic_keys=0123\0" \
"hwconfig=switch:lan=on,pwl=off\0" \
"hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"logversion=2\0" \
@@ -336,6 +344,11 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
/* GPIO */
#define CONFIG_ENBW_CMC_BOARD_TYPE 57
#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
/* FDT support */
#define CONFIG_OF_LIBFDT
@@ -438,7 +451,8 @@
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

29
include/configs/harmony.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010,2011
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
@@ -27,8 +27,12 @@
#include <asm/sizes.h>
#include "tegra2-common.h"
/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra2-harmony
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Harmony) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony"
@@ -44,14 +48,13 @@
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
@@ -61,4 +64,22 @@
/* Environment not stored */
#define CONFIG_ENV_IS_NOWHERE
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

1
include/configs/imx31_phycore.h
View File

@@ -56,7 +56,6 @@
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX31_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE

63
include/configs/km/km_arm.h
View File

@@ -57,6 +57,13 @@
#define CONFIG_CMD_SF
#define CONFIG_SOFT_I2C /* I2C bit-banged */
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 5000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_3
#endif
#include "asm/arch/config.h"
#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */
@@ -81,7 +88,7 @@
"boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
"u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_DEF_ENV_UPDATE \
CONFIG_KM_UPDATE_UBOOT \
""
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
@@ -159,12 +166,12 @@
*/
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII /* to debug mdio phy config */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
/*
* UBI related stuff
@@ -185,6 +192,7 @@ int get_sda(void);
int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN 8
#define KM_KIRKWOOD_SCL_PIN 9
#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
#define KM_KIRKWOOD_ENV_WP 38
#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
@@ -211,6 +219,15 @@ int get_scl(void);
/*
* Environment variables configurations
*/
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */
#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */
#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
#else
#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
#define CONFIG_ENV_EEPROM_IS_ON_I2C
@@ -218,16 +235,20 @@ int get_scl(void);
#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0"
/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/* SPI bus claim MPP configuration */
#define CONFIG_SYS_KW_SPI_MPP 0x0
#define FLASH_GPIO_PIN 0x00010000
#define KM_FLASH_GPIO_PIN 16
#ifndef MTDIDS_DEFAULT
# define MTDIDS_DEFAULT "nand0=orion_nand"
@@ -239,23 +260,32 @@ int get_scl(void);
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
#endif /* MTDPARTS_DEFAULT */
#define CONFIG_KM_DEF_ENV_UPDATE \
#define CONFIG_KM_UPDATE_UBOOT \
"update=" \
"spi on;sf probe 0;sf erase 0 50000;" \
"sf write ${load_addr_r} 0 ${filesize};" \
"spi off\0"
"sf probe 0;sf erase 0 +${filesize};" \
"sf write ${load_addr_r} 0 ${filesize};\0"
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_NEW_ENV \
"newenv=sf probe 0;" \
"sf erase " xstr(CONFIG_ENV_OFFSET) " " \
xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
#else
#define CONFIG_KM_NEW_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
CONFIG_KM_NEW_ENV \
"arch=arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
@@ -284,4 +314,7 @@ int get_scl(void);
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
#define CONFIG_CMD_DIAG
/* we do the whole PCIe FPGA config stuff here */
#define BOARD_LATE_INIT
#endif /* _CONFIG_KM_ARM_H */

145
include/configs/km_kirkwood.h
View File

@@ -6,8 +6,9 @@
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de
* (C) Copyright 2011-2012
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
* Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -36,25 +37,139 @@
#ifndef _CONFIG_KM_KIRKWOOD_H
#define _CONFIG_KM_KIRKWOOD_H
/* KM_KIRKWOOD */
#if defined(CONFIG_KM_KIRKWOOD)
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
#define CONFIG_HOSTNAME km_kirkwood
#define CONFIG_KM_DISABLE_PCIE
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
/* KM_KIRKWOOD_PCI */
#elif defined(CONFIG_KM_KIRKWOOD_PCI)
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
#define CONFIG_HOSTNAME km_kirkwood_pci
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_FPGA_CONFIG
/* KM_NUSA */
#elif defined(CONFIG_KM_NUSA)
#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
#define CONFIG_IDENT_STRING "\nKeymile NUSA"
#define CONFIG_HOSTNAME kmnusa
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG
#define CONFIG_KM_PIGGY4_88E6352
/* KM_MGCOGE3UN */
#elif defined(CONFIG_KM_MGCOGE3UN)
#define CONFIG_IDENT_STRING "\nKeymile COGE3UN"
#define CONFIG_HOSTNAME mgcoge3un
#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_PIGGY4_88E6061
/* KMCOGE5UN */
#elif defined(CONFIG_KM_COGE5UN)
#define CONFIG_IDENT_STRING "\nKeymile COGE5UN"
#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
#define CONFIG_HOSTNAME kmcoge5un
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_PIGGY4_88E6352
/* KM_PORTL2 */
#elif defined(CONFIG_KM_PORTL2)
#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
#define CONFIG_HOSTNAME portl2
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define CONFIG_KM_PIGGY4_88E6061
#else
#error ("Board unsupported")
#endif
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
/*
* Version number information
*/
#ifdef CONFIG_KM_DISABLE_PCI
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
#undef CONFIG_KIRKWOOD_PCIE_INIT
#else
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
#endif
#define CONFIG_HOSTNAME km_kirkwood
#if defined(CONFIG_KM_PIGGY4_88E6352)
/*
* Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
* an Marvell 88E6352 simple switch.
* In this case we have to change the default settings for the etherent mac.
* There is NO ethernet phy. The ARM and Switch are conencted directly over
* RGMII in MAC-MAC mode
* In this case 1GBit full duplex and autoneg off
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_1000 |\
MVGBE_SET_MII_SPEED_TO_100)
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
#endif
#ifdef CONFIG_KM_PIGGY4_88E6061
/*
* Some keymile boards like mgcoge3un have their PIGGY4 connected via
* an Marvell 88E6061 simple switch.
* In this case we have to change the default settings for the
* ethernet phy connected to the kirkwood.
* In this case 100MB full duplex and autoneg off
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
#endif
#ifdef CONFIG_KM_DISABLE_PCI
#undef CONFIG_KIRKWOOD_PCIE_INIT
#endif
/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
#define KM_XLX_PROGRAM_B_PIN 39
#endif /* _CONFIG_KM_KIRKWOOD */

6
include/configs/lacie_kw.h
View File

@@ -66,15 +66,11 @@
/*
* SDRAM configuration
*/
#if defined(CONFIG_NET2BIG_V2)
#define CONFIG_NR_DRAM_BANKS 2
#else
#define CONFIG_NR_DRAM_BANKS 1
#endif
#ifdef CONFIG_INETSPACE_V2
/* Different SDRAM configuration and size for Internet Space v2 */
#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
#endif
/*

182
include/configs/lsxl.h Normal file
View File

@@ -0,0 +1,182 @@
/*
* Copyright (c) 2012 Michael Walle
* Michael Walle <michael@walle.cc>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_LSXL_H
#define _CONFIG_LSXL_H
/*
* Version number information
*/
#if defined(CONFIG_LSCHLV2)
#define CONFIG_IDENT_STRING " LS-CHLv2"
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
#define CONFIG_MACH_TYPE 3006
#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
#elif defined(CONFIG_LSXHL)
#define CONFIG_IDENT_STRING " LS-XHL"
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
#define CONFIG_MACH_TYPE 2663
/* CONFIG_SYS_TCLK is 200000000 by default */
#else
#error "unknown board"
#endif
/*
* General configuration options
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_MISC_INIT_R
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_RANDOM_MACADDR
#define CONFIG_KIRKWOOD_GPIO
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/*
* Enable u-boot API for standalone programs.
*/
#define CONFIG_API
/*
* Commands configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/* ST M25P40 */
#undef CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SPI_FLASH_STMICRO
#undef CONFIG_ENV_SPI_MAX_HZ
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#undef CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SF_DEFAULT_SPEED 25000000
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Environment variables configurations
*/
#ifdef CONFIG_SPI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 8
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x10000 /* 64k */
#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_LOADADDR 0x00800000
#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootsource=hdd\0" \
"hdpart=0:1\0" \
"bootcmd_net=bootp 0x00100000 uImage " \
"&& tftpboot 0x00800000 uInitrd " \
"&& bootm 0x00100000 0x00800000\0" \
"bootcmd_hdd=ide reset " \
"&& ext2load ide ${hdpart} 0x00100000 /uImage " \
"&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \
"&& bootm 0x00100000 0x00800000\0" \
"bootcmd_usb=usb start " \
"&& fatload usb 0:1 0x00100000 /uImage " \
"&& fatload usb 0:1 0x00800000 /uInitrd " \
"&& bootm 0x00100000 0x00800000\0" \
"bootcmd_rescue=run config_nc_dhcp; run nc\0" \
"eraseenv=sf probe 0 " \
"&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \
" +" MK_STR(CONFIG_ENV_SIZE) "\0" \
"config_nc_dhcp=setenv autoload_old ${autoload}; " \
"setenv autoload no " \
"&& bootp " \
"&& setenv ncip ${serverip} " \
"&& setenv autoload ${autoload_old}; " \
"setenv autoload_old\0" \
"standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
"setenv ncip; setenv gatewayip; setenv ethact; " \
"setenv bootfile; setenv dnsip; " \
"setenv bootsource hdd; run ser\0" \
"restore_env=run standard_env; saveenv; reset\0" \
"ser=setenv stdin serial; setenv stdout serial; " \
"setenv stderr serial\0" \
"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */
#define CONFIG_PHY_BASE_ADR 7
#undef CONFIG_RESET_PHY_R
#endif /* CONFIG_CMD_NET */
#ifdef CONFIG_CMD_IDE
#undef CONFIG_IDE_LED
#undef CONFIG_SYS_IDE_MAXBUS
#define CONFIG_SYS_IDE_MAXBUS 1
#undef CONFIG_SYS_IDE_MAXDEVICE
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif
#endif /* _CONFIG_LSXL_H */

11
include/configs/m28evk.h
View File

@@ -17,8 +17,8 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __M28_H__
#define __M28_H__
#ifndef __M28EVK_CONFIG_H__
#define __M28EVK_CONFIG_H__
#include <asm/arch/regs-base.h>
@@ -40,11 +40,8 @@
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_OF_LIBFDT
/*
* SPL
*/
@@ -88,7 +85,7 @@
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
@@ -325,4 +322,4 @@
"fi ; " \
"fi\0"
#endif /* __M28_H__ */
#endif /* __M28EVK_CONFIG_H__ */

6
include/configs/medcom.h
View File

@@ -29,10 +29,8 @@
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M"
#define V_PROMPT "Tegra2 (Medcom) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
@@ -46,7 +44,7 @@
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
@@ -61,4 +59,6 @@
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

86
include/configs/mgcoge3un.h
View File

@@ -1,86 +0,0 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2010-2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
#ifndef _CONFIG_MGCOGE3UN_H
#define _CONFIG_MGCOGE3UN_H
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN"
#define CONFIG_HOSTNAME mgcoge3un
#define CONFIG_MGCOGE3UN
#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/
/* we use a new RAM type on mgcoge3un board */
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
/*
* mgcoge3un has a fixed link to the marvell switch
* with 100MB full duplex and autoneg off, for this
* reason we have to change the default settings
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
/*
* PCIe port not used on mgcoge3un
*/
#undef CONFIG_KIRKWOOD_PCIE_INIT
#endif /* _CONFIG_MGCOGE3UN_H */

9
include/configs/mx28evk.h
View File

@@ -16,8 +16,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __MX28EVK_CONFIG_H__
#define __MX28EVK_CONFIG_H__
#include <asm/arch/regs-base.h>
@@ -34,7 +34,6 @@
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
/*
@@ -54,11 +53,11 @@
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
@@ -250,4 +249,4 @@
"run netargs; " \
"dhcp ${uimage}; bootm\0" \
#endif /* __CONFIG_H */
#endif /* __MX28EVK_CONFIG_H__ */

1
include/configs/mx35pdk.h
View File

@@ -59,7 +59,6 @@
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX35_PORT1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

2
include/configs/mx53ard.h
View File

@@ -52,7 +52,6 @@
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
/* MMC Configs */
#define CONFIG_FSL_ESDHC
@@ -68,7 +67,6 @@
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_MII
#define CONFIG_MII_GASKET
#define CONFIG_DISCOVER_PHY
#define CONFIG_CMD_PING

1
include/configs/mx53evk.h
View File

@@ -55,7 +55,6 @@
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
/* PMIC Configs */
#define CONFIG_PMIC

2
include/configs/mx53loco.h
View File

@@ -41,7 +41,6 @@
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
@@ -92,7 +91,6 @@
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
/* PMIC Controller */
#define CONFIG_PMIC

1
include/configs/mx53smd.h
View File

@@ -52,7 +52,6 @@
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
/* MMC Configs */
#define CONFIG_FSL_ESDHC

1
include/configs/mx6qarm2.h
View File

@@ -37,7 +37,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO

1
include/configs/mx6qsabrelite.h
View File

@@ -40,7 +40,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO

4
include/configs/omap3_beagle.h
View File

@@ -146,6 +146,8 @@
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
@@ -213,7 +215,7 @@
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \

4
include/configs/omap3_evm.h
View File

@@ -42,6 +42,8 @@
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
@@ -134,7 +136,7 @@
* Default environment
* -----------------------------------------------------------------------------
*/
#define CONFIG_BOOTDELAY 10
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \

7
include/configs/omap4_common.h
View File

@@ -120,9 +120,6 @@
/* Flash */
#define CONFIG_SYS_NO_FLASH 1
/* clocks */
#define CONFIG_SYS_CLOCKS_ENABLE_ALL
/* commands to include */
#include <config_cmd_default.h>
@@ -281,9 +278,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_ENABLE_PADS_ALL
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_THUMB_BUILD

4
include/configs/omap5_evm.h
View File

@@ -50,8 +50,6 @@
/* Clock Defines */
#define V_OSCK 19200000 /* Clock output from T2 */
#define V_SCLK V_OSCK
#define CONFIG_SYS_CLOCKS_ENABLE_ALL 1 /* Enable all clocks */
#define CONFIG_SYS_ENABLE_PADS_ALL 1 /* Enable all PADS for now */
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
@@ -261,7 +259,7 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/*
* 64 bytes before this address should be set aside for u-boot.img's

34
include/configs/paz00.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010,2011, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -20,8 +20,12 @@
#include <asm/sizes.h>
#include "tegra2-common.h"
/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra2-paz00
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=512M@0M"
#define V_PROMPT "Tegra2 (Paz00) MOD # "
#define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00"
@@ -31,14 +35,13 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
@@ -46,6 +49,25 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/* Environment not stored */
#define CONFIG_ENV_IS_NOWHERE
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

6
include/configs/plutux.h
View File

@@ -29,10 +29,8 @@
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M"
#define V_PROMPT "Tegra2 (Plutux) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
@@ -46,7 +44,7 @@
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
@@ -61,4 +59,6 @@
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

85
include/configs/portl2.h
View File

@@ -1,85 +0,0 @@
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2010-2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com.
* Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
#ifndef _CONFIG_PORTL2_H
#define _CONFIG_PORTL2_H
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
#define CONFIG_HOSTNAME portl2
#define CONFIG_PORTL2
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
/*
* Note: This is only valid for HW > P1A if you got an outdated P1A
* use KM_ENV_BUS "pca9544a:70:a"
*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* portl2 has a fixed link to the XMPP backplane
* with 100MB full duplex and autoneg off, for this
* reason we have to change the default settings
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
/*
* portl2 does use the PCIe Port0
*/
#define CONFIG_KIRKWOOD_PCIE_INIT
#endif /* _CONFIG_PORTL2_H */

35
include/configs/seaboard.h
View File

@@ -41,7 +41,6 @@
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (SeaBoard) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
@@ -54,19 +53,9 @@
#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SPI */
#define CONFIG_TEGRA2_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
@@ -78,7 +67,7 @@
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
@@ -86,13 +75,10 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* USB Host support */
#define CONFIG_USB_EHCI
@@ -100,6 +86,14 @@
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
/* Enable keyboard */
#define CONFIG_TEGRA2_KEYBOARD
#define CONFIG_KEYBOARD
@@ -108,4 +102,7 @@
#define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
"stdout=serial\0" \
"stderr=serial\0"
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

94
include/configs/spear-common.h
View File

@@ -27,18 +27,33 @@
* Common configurations used for both spear3xx as well as spear6xx
*/
/* U-boot Load Address */
#define CONFIG_SYS_TEXT_BASE 0x00700000
/* Ethernet driver configuration */
#define CONFIG_MII
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_SEARCH_PHY
#define CONFIG_DW0_PHY 1
#define CONFIG_NET_MULTI
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* USBD driver configuration */
#if defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DW_UDC
#define CONFIG_USB_DEVICE
#define CONFIG_USBD_HS
#define CONFIG_USB_TTY
#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
#if defined(CONFIG_USB_TTY)
#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
#endif
#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
/* I2C driver configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
@@ -48,27 +63,25 @@
#define CONFIG_I2C_CHIPADDRESS 0x50
/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ (1000)
#define CONFIG_SYS_HZ_CLOCK (8300000)
#define CONFIG_SYS_HZ 1000
/* Flash configuration */
#if defined(CONFIG_FLASH_PNOR)
#define CONFIG_SPEAR_EMI 1
#define CONFIG_SPEAR_EMI
#else
#define CONFIG_SPEARSMI 1
#define CONFIG_ST_SMI
#endif
#if defined(CONFIG_SPEARSMI)
#if defined(CONFIG_ST_SMI)
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_BASE (0xF8000000)
#define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000)
#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000)
#define CONFIG_SYS_FLASH_BASE 0xF8000000
#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_CS1_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_EMPTY_INFO 1
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
@@ -88,11 +101,13 @@
#define CONFIG_SYS_LOADS_BAUD_CHANGE
/* NAND FLASH Configuration */
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_NAND_SPEAR 1
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_QUIET_TEST
/*
* Command support defines
@@ -103,11 +118,13 @@
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
* Default Environment Varible definitions
@@ -124,13 +141,13 @@
* U-Boot Environment placing definitions.
*/
#if defined(CONFIG_ENV_IS_IN_FLASH)
#ifdef CONFIG_SPEARSMI
#ifdef CONFIG_ST_SMI
/*
* Environment is in serial NOR flash
*/
#define CONFIG_SYS_MONITOR_LEN 0x00040000
#define CONFIG_ENV_SECT_SIZE 0x00010000
#define CONFIG_FSMTDBLK "/dev/mtdblock8 "
#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
@@ -146,8 +163,7 @@
"0x4C0000; bootm 0x1600000"
#endif
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
#elif defined(CONFIG_ENV_IS_IN_NAND)
/*
@@ -156,28 +172,46 @@
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_RANGE 0x10000
#define CONFIG_FSMTDBLK "/dev/mtdblock12 "
#define CONFIG_FSMTDBLK "/dev/mtdblock7 "
#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
"0x80000 0x4C0000; " \
"bootm 0x1600000"
#endif
#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \
"console=ttyS0 init=/bin/sh"
#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \
#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
"mem=128M " \
"root="CONFIG_FSMTDBLK \
"rootfstype=jffs2"
#define CONFIG_NFSBOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):$(netdev):off " \
"console=ttyAMA0,115200 $(othbootargs);" \
"bootm; "
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=ttyAMA0,115200 $(othbootargs);" \
CONFIG_BOOTCOMMAND
#define CONFIG_ENV_SIZE 0x02000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_ZERO_BOOTDELAY_CHECK 1
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_MISC_INIT_R
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_AUTOBOOT_PROMPT \
"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
@@ -195,9 +229,9 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Stack sizes */
#define CONFIG_STACKSIZE (128*1024)

62
include/configs/spear3xx.h → include/configs/spear3xx_evb.h
View File

@@ -29,18 +29,44 @@
* (easy to change)
*/
#if defined(CONFIG_spear300)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR300 1
#define CONFIG_SPEAR3XX
#define CONFIG_SPEAR300
#elif defined(CONFIG_spear310)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR310 1
#define CONFIG_SPEAR3XX
#define CONFIG_SPEAR310
#elif defined(CONFIG_spear320)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR320 1
#define CONFIG_SPEAR3XX
#define CONFIG_SPEAR320
#endif
#if defined(CONFIG_usbtty)
#define CONFIG_SPEAR_USBTTY
#endif
#if defined(CONFIG_nand)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_FLASH
#endif
#include <configs/spear-common.h>
/* Ethernet driver configuration */
#define CONFIG_DW_ALTDESCRIPTOR
#if defined(CONFIG_SPEAR310)
#define CONFIG_MACB
#define CONFIG_MACB0_PHY 0x01
#define CONFIG_MACB1_PHY 0x03
#define CONFIG_MACB2_PHY 0x05
#define CONFIG_MACB3_PHY 0x07
#elif defined(CONFIG_SPEAR320)
#define CONFIG_MACB
#define CONFIG_MACB0_PHY 0x01
#endif
/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0 0xD0000000
@@ -85,6 +111,7 @@
#define CONFIG_FLASH_CFI_DRIVER
#if defined(CONFIG_SPEAR310)
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x50000000
#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000
#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000
@@ -100,6 +127,7 @@
#define CONFIG_SYS_MAX_FLASH_BANKS 6
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x44000000
#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000
#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000
@@ -113,19 +141,33 @@
#endif
#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
#define CONFIG_SYS_FLASH_QUIET_TEST 1
#define CONFIG_SYS_FLASH_QUIET_TEST
#endif
/* NAND flash configuration */
#define CONFIG_SYS_FSMC_NAND_SP
#define CONFIG_SYS_FSMC_NAND_8BIT
#if defined(CONFIG_SPEAR300)
#define CONFIG_SYS_NAND_BASE (0x80000000)
#define CONFIG_SYS_NAND_BASE 0x80000000
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_NAND_BASE (0x40000000)
#define CONFIG_SYS_NAND_BASE 0x40000000
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_NAND_BASE (0x50000000)
#define CONFIG_SYS_NAND_BASE 0x50000000
#endif
/* Environment Settings */
#if defined(CONFIG_SPEAR300)
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320)
#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0"
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \
CONFIG_EXTRA_ENV_UNLOCK
#endif
#endif /* __CONFIG_H */

20
include/configs/spear6xx.h → include/configs/spear6xx_evb.h
View File

@@ -28,7 +28,17 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SPEAR600 1
#define CONFIG_SPEAR600
#if defined(CONFIG_usbtty)
#define CONFIG_SPEAR_USBTTY
#endif
#if defined(CONFIG_nand)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_FLASH
#endif
#include <configs/spear-common.h>
@@ -38,6 +48,12 @@
#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_SYS_NAND_BASE (0xD2000000)
/* NAND flash configuration */
#define CONFIG_SYS_FSMC_NAND_SP
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_BASE 0xD2000000
/* Environment Settings */
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
#endif /* __CONFIG_H */

117
include/configs/tegra2-common-post.h Normal file
View File

@@ -0,0 +1,117 @@
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __TEGRA2_COMMON_POST_H
#define __TEGRA2_COMMON_POST_H
#ifdef CONFIG_BOOTCOMMAND
#define BOOTCMDS_COMMON ""
#else
#ifdef CONFIG_CMD_EXT2
#define BOOTCMD_FS_EXT2 "ext2 "
#else
#define BOOTCMD_FS_EXT2 ""
#endif
#ifdef CONFIG_CMD_FAT
#define BOOTCMD_FS_FAT "fat"
#else
#define BOOTCMD_FS_FAT ""
#endif
#ifdef CONFIG_CMD_MMC
#define BOOTCMDS_MMC \
"mmc_boot=" \
"setenv devtype mmc; " \
"if mmc dev ${devnum}; then " \
"run script_boot; " \
"fi\0" \
"mmc0_boot=setenv devnum 0; run mmc_boot;\0" \
"mmc1_boot=setenv devnum 1; run mmc_boot;\0" \
"bootcmd_mmc=run mmc1_boot; run mmc0_boot\0"
#define BOOTCMD_MMC "run bootcmd_mmc; "
#else
#define BOOTCMDS_MMC ""
#define BOOTCMD_MMC ""
#endif
#ifdef CONFIG_CMD_USB
#define BOOTCMDS_USB \
"usb_boot=" \
"setenv devtype usb; " \
"if usb dev ${devnum}; then " \
"run script_boot; " \
"fi\0" \
"usb0_boot=setenv devnum 0; run usb_boot;\0" \
"bootcmd_usb=run usb0_boot\0"
#define BOOTCMD_USB "run bootcmd_usb; "
#define BOOTCMD_INIT_USB "usb start 0; "
#else
#define BOOTCMDS_USB ""
#define BOOTCMD_USB ""
#define BOOTCMD_INIT_USB ""
#endif
#ifdef CONFIG_CMD_DHCP
#define BOOTCMDS_DHCP \
"bootcmd_dhcp=" \
"if dhcp ${scriptaddr} boot.scr.uimg; then "\
"source ${scriptaddr}; " \
"fi\0"
#define BOOTCMD_DHCP "run bootcmd_dhcp; "
#else
#define BOOTCMDS_DHCP ""
#define BOOTCMD_DHCP ""
#endif
#define BOOTCMDS_COMMON \
"scriptaddr=0x400000\0" \
"rootpart=1\0" \
"script_boot=" \
"for fs in " BOOTCMD_FS_EXT2 BOOTCMD_FS_FAT "; do " \
"for prefix in / /boot/; do " \
"for script in boot.scr.uimg boot.scr; do " \
"echo Scanning ${devtype} ${devnum}:${rootpart} ${fs} ${prefix}${script} ...; " \
"if ${fs}load ${devtype} ${devnum}:${rootpart} ${scriptaddr} ${prefix}${script}; then " \
"echo ${script} found! Executing ...;" \
"source ${scriptaddr};" \
"fi; " \
"done; " \
"done; " \
"done;\0" \
BOOTCMDS_MMC \
BOOTCMDS_USB \
BOOTCMDS_DHCP
#define CONFIG_BOOTCOMMAND BOOTCMD_INIT_USB BOOTCMD_USB BOOTCMD_MMC BOOTCMD_DHCP
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA2_DEVICE_SETTINGS \
BOOTCMDS_COMMON
#endif /* __TEGRA2_COMMON_POST_H */

10
include/configs/tegra2-common.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2010,2011
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
@@ -139,12 +139,6 @@
"stdout=serial\0" \
"stderr=serial\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttyS0,115200n8\0" \
"mem=" TEGRA2_SYSMEM "\0" \
"smpflag=smp\0" \
TEGRA2_DEVICE_SETTINGS
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
@@ -196,6 +190,6 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_TEGRA2_GPIO
#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#endif /* __TEGRA2_COMMON_H */

130
include/configs/tk71.h Normal file
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@@ -0,0 +1,130 @@
/*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __CONFIG_TK71_H__
#define __CONFIG_TK71_H__
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKa-Ro TK71"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_NR_DRAM_BANKS 1
#define MACH_TYPE_TK71 2399
#define CONFIG_MACH_TYPE MACH_TYPE_TK71
/*
* Commands configuration
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* NAND flash
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV "nand0,3"
#endif
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0}
#define CONFIG_PHY_BASE_ADR 0x08
#endif
/*
* USB/EHCI
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_KIRKWOOD
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_ADDR 0x80000
#define CONFIG_ENV_OFFSET 0x80000
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
"update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
"update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
"update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
"mtdids=nand0=orion_nand\0" \
"mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
"bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
#define MTDIDS_DEFAULT "nand0=orion_nand"
#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS
#define PHYS_SDRAM_1 0x00000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#endif /* __CONFIG_TK71_H__ */

99
include/configs/trimslice.h Normal file
View File

@@ -0,0 +1,99 @@
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
#include "tegra2-common.h"
/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra2-trimslice
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define V_PROMPT "Tegra2 (TrimSlice) # "
#define CONFIG_TEGRA2_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTA
#define CONFIG_TEGRA2_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
#define CONFIG_BOARD_EARLY_INIT_F
/* SPI */
#define CONFIG_TEGRA_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 4
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_ENV_OFFSET (512 * 1024)
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

29
include/configs/ventana.h
View File

@@ -28,12 +28,11 @@
#include "tegra2-common.h"
/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
#define CONFIG_DEFAULT_DEVICE_TREE tegra2-ventana
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Ventana) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana"
@@ -43,14 +42,13 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
@@ -58,6 +56,25 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/* Environment not stored */
#define CONFIG_ENV_IS_NOWHERE
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

463
include/configs/vl_ma2sc.h Normal file
View File

@@ -0,0 +1,463 @@
/*
* (C) Copyright 2009-2012
* Jens Scharsig <esw@bus-elekronik.de>
* BuS Elektronik GmbH & Co. KG
*
* Configuation settings for the VL_MA2SC board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*--------------------------------------------------------------------------*/
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
#define CONFIG_AT91FAMILY
#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MISC_INIT_R
#include <asm/hardware.h>
#define MACH_TYPE_VL_MA2SC 2412
#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
#define CONFIG_SYS_DCACHE_OFF
#ifdef CONFIG_RAMLOAD
#define CONFIG_SYS_TEXT_BASE 0x21000000
#else
#define CONFIG_SYS_TEXT_BASE 0x00000000
#endif
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_IDENT_STRING " on MiS Activ 2"
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AT91_GPIO
#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
#define CONFIG_SYS_USE_NORFLASH
#define CONFIG_SYS_USE_BOOT_NORFLASH
#endif
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
* Hardware drivers
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_WATCHDOG
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/* LCD */
#define CONFIG_LCD
#define CONFIG_ATMEL_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SYS_BLACK_ON_WHITE
#define LCD_BPP LCD_COLOR8
#define CONFIG_ATMEL_LCD_BGR555
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_MD5SUM
#define CONFIG_CMD_SHA1SUM
/*
#define CONFIG_CMD_SPI
*/
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
#define CONFIG_SYS_LONGHELP
#define CONFIG_MD5
#define CONFIG_SHA1
/*----------------------------------------------------------------------------
* Hardware confuguration
*---------------------------------------------------------------------------*/
/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_AT91C_PQFP_UHPBUG
/* I2C-Bus */
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
#ifndef CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C
/* Software I2C driver configuration */
#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
#define I2C_INIT i2c_init_board();
#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
#define I2C_SDA(bit) \
do { \
if (bit) \
writel(AT91_PIN_SDA, &pio->piob.sodr); \
else \
writel(AT91_PIN_SDA, &pio->piob.codr); \
} while (0);
#define I2C_SCL(bit) \
do { \
if (bit) \
writel(AT91_PIN_SCL, &pio->piob.sodr); \
else \
writel(AT91_PIN_SCL, &pio->piob.codr); \
} while (0);
#endif
/* I2C-RTC */
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_MR_URSTEN | \
AT91_RSTC_MR_ERSTL(15))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xFFF) | \
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xFFF))
/* clocks */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
#define MHZ180
#if defined(MHZ199)
/* 199,8994 MHZ */
#define MASTER_PLL_MUL 911
#define MASTER_PLL_DIV 56
#define MASTER_PLL_OUT 2
#elif defined(MHZ180)
/* 180 MHZ */
#define MASTER_PLL_MUL 1875
#define MASTER_PLL_DIV 128
#define MASTER_PLL_OUT 2
#elif defined(MHZTEST)
/* Test MHZ */
#define CONFIG_DISPLAY_CPUINFO
#define MASTER_PLL_MUL 8
#define MASTER_PLL_DIV 1
#define MASTER_PLL_OUT 2
#else
/* 176.9472 MHZ */
#define MASTER_PLL_MUL 72
#define MASTER_PLL_DIV 5
#define MASTER_PLL_OUT 2
#endif
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | \
AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
AT91_PMC_PLLXR_PLLCOUNT(63) | \
AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
#define CONFIG_SYS_SDRC_MR_VAL1 0
#define CONFIG_SYS_SDRC_TR_VAL1 700
#define CONFIG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
AT91_SDRAMC_CAS_3 | \
AT91_SDRAMC_DBW_32 | \
(2 << 8) | /* Write Recovery Delay */ \
(7 << 12) | /* Row Cycle Delay */ \
(2 << 16) | /* Row Precharge Delay */ \
(2 << 20) | /* Row to Column Delay */ \
(5 << 24) | /* Active to Precharge Delay */ \
(8 << 28)) /* Exit Self Refresh to Active Delay */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* NOR flash */
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define PHYS_FLASH_1 0x10000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x21e00000
/* Address and size of Primary Environment Sector */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x20000
#else
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
38400, 57600, 9600 }
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifndef CONFIG_RAMLOAD
#define CONFIG_BOOTCOMMAND "run nfsboot"
#endif
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_BOOT_RETRY_MIN 15
#define CONFIG_NFSBOOTCOMMAND \
"dhcp $(copy_addr) $(kernelname);" \
"run bootargsdefaults;" \
"set bootargs $(bootargs) boot=nfs " \
";echo $(bootargs)" \
";bootm"
#define CONFIG_EXTRA_ENV_SETTINGS \
"ubootaddr=10000000\0" \
"splashimage=10080000\0" \
"kerneladdr=100A0000\0" \
"kernelsize=00800000\0" \
"minifsaddr=108A0000\0" \
"minifssize=00060000\0" \
"rootfsaddr=10900000\0" \
"copy_addr=20200000\0" \
"rootfssize=01700000\0" \
"kernelname=uImage_vl_ma2sc\0" \
"bootargsdefaults=set bootargs " \
"console=ttyS0,115200 " \
"video=atmel_lcdfb " \
"mem=62M " \
"panic=10 " \
"boardrevison=\\\"${revision}\\\" " \
"uboot=\\\"${ver}\\\" " \
"\0" \
"update_all=run update_kernel;run update_root;" \
"run update_splash; run update_uboot\0" \
"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
"dhcp $(copy_addr) $(kernelname);" \
"erase $(kerneladdr) +$(kernelsize);" \
"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
"protect on $(kerneladdr) +$(kernelsize)" \
"\0" \
"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
"dhcp $(copy_addr) vl_ma2sc.root;" \
"erase $(rootfsaddr) +$(rootfssize);" \
"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
"\0" \
"update_splash=protect off $(splashimage) +20000;" \
"dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
"erase $(splashimage) +20000;" \
"cp.b $(fileaddr) 10080000 $(filesize);" \
"protect on $(splashimage) +20000\0" \
"update_uboot=protect off 10000000 1005FFFF;" \
"dhcp $(copy_addr) u-boot_vl_ma2sc;" \
"erase 10000000 1005FFFF;" \
"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
"protect on 10000000 1005FFFF;reset\0" \
"emergency=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=emergency " \
";bootm $(kerneladdr)\0" \
"netemergency=run bootargsdefaults;" \
"dhcp $(copy_addr) $(kernelname);" \
"set bootargs $(bootargs) root=initramfs boot=emergency " \
";bootm $(copy_addr)\0" \
"norboot=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=local quiet " \
";bootm $(kerneladdr)\0" \
"nandboot=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=nand " \
";bootm $(kerneladdr)\0" \
"setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
"clearenv=protect off 10060000 1007FFFF;" \
"erase 10060000 1007FFFF;reset\0" \
" "
/*--------------------------------------------------------------------------*/
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif

94
include/configs/whistler.h Normal file
View File

@@ -0,0 +1,94 @@
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
#include "tegra2-common.h"
/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra2-whistler
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define V_PROMPT "Tegra2 (Whistler) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTA
#define CONFIG_TEGRA2_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 4
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
* the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If
* they didn't, the boot sector layout may be different. However, use of that
* particular card is standard practice as far as I know.
*/
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra2-common-post.h"
#endif /* __CONFIG_H */

1
include/configs/zipitz2.h
View File

@@ -32,6 +32,7 @@
#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_PREBOOT
/*
* Environment settings

101
include/linux/mtd/fsmc_nand.h Normal file
View File

@@ -0,0 +1,101 @@
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSMC_NAND_H__
#define __FSMC_NAND_H__
#include <linux/mtd/nand.h>
struct fsmc_regs {
u32 ctrl; /* 0x00 */
u8 reserved_1[0x40 - 0x04];
u32 pc; /* 0x40 */
u32 sts; /* 0x44 */
u32 comm; /* 0x48 */
u32 attrib; /* 0x4c */
u32 ioata; /* 0x50 */
u32 ecc1; /* 0x54 */
u32 ecc2; /* 0x58 */
u32 ecc3; /* 0x5c */
u8 reserved_2[0xfe0 - 0x60];
u32 peripid0; /* 0xfe0 */
u32 peripid1; /* 0xfe4 */
u32 peripid2; /* 0xfe8 */
u32 peripid3; /* 0xfec */
u32 pcellid0; /* 0xff0 */
u32 pcellid1; /* 0xff4 */
u32 pcellid2; /* 0xff8 */
u32 pcellid3; /* 0xffc */
};
/* ctrl register definitions */
#define FSMC_WP (1 << 7)
/* pc register definitions */
#define FSMC_RESET (1 << 0)
#define FSMC_WAITON (1 << 1)
#define FSMC_ENABLE (1 << 2)
#define FSMC_DEVTYPE_NAND (1 << 3)
#define FSMC_DEVWID_8 (0 << 4)
#define FSMC_DEVWID_16 (1 << 4)
#define FSMC_ECCEN (1 << 6)
#define FSMC_ECCPLEN_512 (0 << 7)
#define FSMC_ECCPLEN_256 (1 << 7)
#define FSMC_TCLR_1 (1 << 9)
#define FSMC_TAR_1 (1 << 13)
/* sts register definitions */
#define FSMC_CODE_RDY (1 << 15)
/* comm register definitions */
#define FSMC_TSET_0 (0 << 0)
#define FSMC_TWAIT_6 (6 << 8)
#define FSMC_THOLD_4 (4 << 16)
#define FSMC_THIZ_1 (1 << 24)
/* peripid2 register definitions */
#define FSMC_REVISION_MSK (0xf)
#define FSMC_REVISION_SHFT (0x4)
#define FSMC_VER8 0x8
/*
* There are 13 bytes of ecc for every 512 byte block and it has to be read
* consecutively and immediately after the 512 byte data block for hardware to
* generate the error bit offsets
* Managing the ecc bytes in the following way is easier. This way is similar to
* oobfree structure maintained already in u-boot nand driver
*/
#define FSMC_MAX_ECCPLACE_ENTRIES 32
struct fsmc_nand_eccplace {
u32 offset;
u32 length;
};
struct fsmc_eccplace {
struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
};
extern int fsmc_nand_init(struct nand_chip *nand);
#endif

117
include/linux/mtd/st_smi.h Normal file
View File

@@ -0,0 +1,117 @@
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef ST_SMI_H
#define ST_SMI_H
/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */
/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */
#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE
#define SMIBANK0_BASE (FLASH_START_ADDRESS)
#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE)
#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE)
#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE)
#define BANK0 0
#define BANK1 1
#define BANK2 2
#define BANK3 3
struct smi_regs {
u32 smi_cr1;
u32 smi_cr2;
u32 smi_sr;
u32 smi_tr;
u32 smi_rr;
};
/* CONTROL REG 1 */
#define BANK_EN 0x0000000F /* enables all banks */
#define DSEL_TIME 0x00000060 /* Deselect time */
#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */
#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */
#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */
#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */
#define SW_MODE 0x10000000 /* enables SW Mode */
#define WB_MODE 0x20000000 /* Write Burst Mode */
#define FAST_MODE 0x00008000 /* Fast Mode */
#define HOLD1 0x00010000
/* CONTROL REG 2 */
#define RD_STATUS_REG 0x00000400 /* reads status reg */
#define WE 0x00000800 /* Write Enable */
#define BANK0_SEL 0x00000000 /* Select Banck0 */
#define BANK1_SEL 0x00001000 /* Select Banck1 */
#define BANK2_SEL 0x00002000 /* Select Banck2 */
#define BANK3_SEL 0x00003000 /* Select Banck3 */
#define BANKSEL_SHIFT 12
#define SEND 0x00000080 /* Send data */
#define TX_LEN_1 0x00000001 /* data length = 1 byte */
#define TX_LEN_2 0x00000002 /* data length = 2 byte */
#define TX_LEN_3 0x00000003 /* data length = 3 byte */
#define TX_LEN_4 0x00000004 /* data length = 4 byte */
#define RX_LEN_1 0x00000010 /* data length = 1 byte */
#define RX_LEN_2 0x00000020 /* data length = 2 byte */
#define RX_LEN_3 0x00000030 /* data length = 3 byte */
#define RX_LEN_4 0x00000040 /* data length = 4 byte */
#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */
#define WCIE 0x00000200 /* WCF Interrupt Enable */
/* STATUS_REG */
#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */
#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */
#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */
#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */
#define RSR 0x00000005 /* Read Status regiser */
#define TFF 0x00000100 /* Transfer Finished FLag */
#define WCF 0x00000200 /* Transfer Finished FLag */
#define ERF1 0x00000400 /* Error Flag 1 */
#define ERF2 0x00000800 /* Error Flag 2 */
#define WM0 0x00001000 /* WM Bank 0 */
#define WM1 0x00002000 /* WM Bank 1 */
#define WM2 0x00004000 /* WM Bank 2 */
#define WM3 0x00008000 /* WM Bank 3 */
#define WM_SHIFT 12
/* TR REG */
#define READ_ID 0x0000009F /* Read Identification */
#define BULK_ERASE 0x000000C7 /* BULK erase */
#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */
#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */
struct flash_dev {
u32 density;
ulong size;
ushort sector_count;
};
#define SFLASH_PAGE_SIZE 0x100 /* flash page size */
#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
#define WMODE_TOUT 15 /* write enable timeout(in ms) */
extern void smi_init(void);
#endif

17
include/net.h
View File

@@ -122,6 +122,23 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
#ifdef CONFIG_RANDOM_MACADDR
/*
* The u-boot policy does not allow hardcoded ethernet addresses. Under the
* following circumstances a random generated address is allowed:
* - in emergency cases, where you need a working network connection to set
* the ethernet address.
* Eg. you want a rescue boot and don't have a serial port to access the
* CLI to set environment variables.
*
* In these cases, we generate a random locally administered ethernet address.
*
* Args:
* enetaddr - returns 6 byte hardware address
*/
extern void eth_random_enetaddr(uchar *enetaddr);
#endif
extern int usb_eth_initialize(bd_t *bi);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(void *packet, int length); /* Send a packet */

2
include/netdev.h
View File

@@ -52,7 +52,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr);
int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
int dm9000_initialize(bd_t *bis);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);